SPICE Device Model SUP80N15-20L Vishay Siliconix N-Channel 150-V (D-S) 175°C MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72425 12-Jun-04 www.vishay.com 1 SPICE Device Model SUP80N15-20L Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Simulated Data VGS(th) VDS = VGS, ID = 250 µA 1.7 ID(on) VDS = 5 V, VGS = 10 V 314 VGS = 10 V, ID = 30 A 0.016 VGS = 10 V, ID = 30 A, TJ = 125°C 0.023 VGS = 10 V, ID = 30 A, TJ = 175°C 0.026 VGS = 4.5 V, ID = 20 A 0.017 Measured Data Unit Static Gate Threshold Voltage On-State Drain Current a Drain-Source On-State Resistancea Forward Transconductance a Forward Voltagea rDS(on) V A 0.016 Ω gfs VDS = 15 V, ID = 30 A 93 VSD IS = 80 A, VGS = 0 V 0.92 1 S 6590 6500 V Dynamicb Input Capacitance Ciss Output Capacitance Coss 510 520 Reverse Transfer Capacitance Crss 320 270 Total Gate Chargec Qg 114 110 c VGS = 0 V, VDS = 25 V, f = 1 MHz VDS = 50 V, VGS = 10 V, ID = 80 A Gate-Source Charge Qgs 21 21 Gate-Drain Chargec Qgd 33 33 Turn-On Delay Timec td(on) 176 20 43 100 43 70 49 135 c tr Turn-Off Delay Timec td(off) Rise Time Fall Timec tf VDD = 50 V, RL = 0.93 Ω ID ≅ 80 A, VGEN = 10 V, RG = 2.5 Ω Pf NC Ns Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 72425 12-Jun-04 SPICE Device Model SUP80N15-20L Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72425 12-Jun-04 www.vishay.com 3