Click Here & Upgrade PDF Complete Expanded Features Unlimited Pages Documents SPICE Device Model Si6801DQ Vishay Siliconix N- and P-Channel Dual Enhancement-Mode MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The model subcircuit is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC a This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71023 22-May-04 www.vishay.com 1 Click Here & Upgrade Expanded Features Unlimited Pages PDF Complete SPICE Device Model Si6801DQ Vishay Siliconix Documents SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Symbol Test Conditions Typical Unit Static Gate Threshold Voltage On-State Drain Current VGS(th) a ID(on) Drain-Source On-State Resistance Forward Transconductance a a a Diode Forward Voltage rDS(on) gfs VSD VDS = V, VGS, ID = 250 µA N-Ch 1.02 VDS = V, VGS, ID = −250 µA P-Ch 1.15 VDS 5 V, VGS = 4.5 V N-Ch 23 VDS = −5 V, VGS = −4.5 V P-Ch 18 VGS = 4.5 V, ID = 1.9 A N-Ch 0.112 VGS = −4.5 V, ID = −1.7 A P-Ch 0.154 VGS = 3 V, ID = 1.5 A N-Ch 0.149 VGS = −3 V, ID = −1.3 A P-Ch 0.217 V A VDS = 15 V, ID = 1.9 A N-Ch 5 VDS = −15 V, ID = −1.7 A P-Ch 4.1 IS = 1 A, VGS = 0 V N-Ch 0.77 IS = −1 V, VGS = 0 V P-Ch −0.77 N-Ch 1.6 Ω S V Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs N-Channel VDS = 3.5 V, VGS = 4.5 V, ID = 0.3 A P-Channel VDS = −3.5 V, VGS = −4.5 V, ID = −0.3 A Qgd td(on) tr td(off) N-Channel VDD = 3.5 V, RL = 11.5 Ω ID ≅ 0.3 A, VGEN = 4.5 V, RG = 6 Ω P-Channel VDD = −3.5 V, RL = 11.5 Ω ID ≅ −0.3 A, VGEN = −4.5 V, RG = 6 Ω tf trr P-Ch 3 N-Ch 0.41 P-Ch 0.76 N-Ch 0.26 P-Ch 0.70 N-Ch 5.2 P-Ch 6 N-Ch 6.2 P-Ch 10 N-Ch 9 P-Ch 11 N-Ch 15 nC ns P-Ch 22 IF = 1 A, di/dt = 100 A/µs N-Ch 31 IF = −1 A, di/dt = 100 A/µs P-Ch 30 Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. www.vishay.com 2 Document Number: 71023 22-May-04 Click Here & Upgrade PDF Complete Expanded Features Unlimited Pages Documents SPICE Device Model Si6801DQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-CHANNEL MOSFET Document Number: 71023 22-May-04 www.vishay.com 3 Click Here & Upgrade Expanded Features Unlimited Pages PDF Complete SPICE Device Model Si6801DQ Vishay Siliconix Documents P-CHANNEL MOSFET www.vishay.com 4 Document Number: 71023 22-May-04