SAMSUNG K3S7V2000M-TC20

K3S7V2000M-TC
Synch. MROM
64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Address: Row address: RA0 ~ RA12
Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16)
• Switchable organization
4,194,304 x 16(word mode) /
2,097,152 x 32(double word mode)
• All inputs are sampled at the rising edge of the system clock
• Read Performance at memory point of view
@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)
@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)
@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)
• tSAC : 6ns
• Default mode by user requirement
• MRS cycle with address key programs
-. RAS Latency(1 & 2)
-. CAS Latency(3 ~ 6)
-. Burst Length : 4, 8
-. Burst Type : Sequential & Interleaved
• DQM for data-out masking
• Package :86TSOP2 - 400
The K3S7V2000M-TC is a synchronous high bandwidth mask
programmable ROM fabricated with SAMSUNG′s high performance CMOS process technology and is organized either as
4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double
word mode) depending on polarity of WORD pin.(see pin function description). Synchronous design allows precise cycle control, with the use of system clock, I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part NO.
MAX Freq.
K3S7V2000M-TC10
100MHz
K3S7V2000M-TC12
83MHz
K3S7V2000M-TC15
66MHz
K3S7V2000M-TC20
50MHz
K3S7V2000M-TC30
33MHz
Interface
Package
LVTTL
86TSOP2
FUNCTIONAL BLOCK DIAGRAM
Q0
Q16
.
Output
Q15
Q31
Buffer
4M x 16 /2M x 32
Cell Array
Sense AMP.
ADD
.
Row Decoder
Row Buffer
Column Decoder
Col. Buffer
LRAS
Address Register
CLK
.
Latency & Burst Length
LCKE
Programming Register
LRAS
LMR
LCAS
Timing
CLK
CKE
MR
Register
RAS
CAS
CS
DQM
* Samsung Electronics reserves the right to
change products or specification without notice.
K3S7V2000M-TC
Synch. MROM
PIN CONFIGURATION (TOP VIEW)
VDD
Q0
VDDQ
Q16
1
86
2
85
84
3
4
83
Vss
Q31
VssQ
Q15
Q1
5
82
Q30
VssQ
6
7
81
80
VDDQ
Q14
Q29
VssQ
Q17
8
79
9
10
78
77
VssQ
11
12
76
75
VDDQ
Q19
13
74
Q12
MR#
14
73
NC
VDD
15
72
Vss
DQM
16
71
NC
NC
CAS#
17
18
70
69
NC
NC
RAS#
CS#
19
20
68
CLK
67
CKE
WORD#
21
Q2
VDDQ
Q18
Q3
86TSOPII - 400
(0.5 mm Pin Pitch)
Q13
Q28
66
A9
65
64
A8
A7
A12
22
A11
23
A10
A0
24
63
A6
25
26
62
61
A4
27
28
60
59
NC
29
30
58
57
Vss
NC
Q4
31
56
Q27
VssQ
Q20
32
33
55
VDDQ
Q11
Q5
34
53
Q26
VDDQ
Q21
35
36
52
51
VssQ
Q10
Q6
37
VssQ
Q22
38
50
49
VDDQ
39
40
48
47
Q9
46
VssQ
Q23
41
42
43
45
44
Q8
VDD
A1
A2
NC
VDD
Q7
VDDQ
54
A5
A3
NC
Q25
Q24
Vss
K3S7V2000M-TC
Synch. MROM
PIN FUNCTION DESCRIPTION
PIN
NAME
INPUT FUNCTION
CLK
System Clock
Active on the rising edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK and CKE.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE should be
enabled at least one cycle prior to new command. Disables input buffers for power down
in standby mode.
A0 ~ A12
Address
Row / Column addresses are multiplexed on the same pins.
Row address: RA 0 ~ RA12, Column address: CA0 ~ CA7 (x32): CA 0 ~ CA8 (x16)
RAS
Row Address Strobe
Latches row addresses on the rising edge of the CLK with RAS low.
Enables row access
CAS
Column Address Strobe
Latches column addresses on the rising edge of the CLK with CAS low.
Enables column access.
MR
Mode Register Set
Enables mode register set with MR low. (Simultaneously CS,RAS and CAS are low)
Q0 ~ Q31
Data Output
VDD/VSS
Power Supply/Ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ
Data Output Power/
Ground
Power and ground for the output buffers.
WORD
x32/x16 Mode Selection
Double word mode/word mode, depending on polarity of WORD pin.
Should be set before CAS enabling.
DQM
Data-out Masking
It works similar to OE during read operation.
N.C
No Connection
This pin is recommended to be left No Connection on the device.
Note1. VDD and VDDQ is same voltage.
K3S7V2000M-TC
Synch. MROM
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on VDD Relative to Vss
Voltage on Any Pin Relative to Vss
Symbol
Min
Max
Unit
VDD, VDDQ
VIN, VOUT
-0.5
4.6
V
-0.5
VDD + 0.5≤4.6
V
TA
0
70
°C
TSTG
-55
125
°C
Short circuit current
IOS
-
50
mA
Power Dissipation
PD
-
1
W
Operating Temperature
Storage Temperature
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
DC OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced to VSS, TA=0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD, VDDQ
3.0
3.3
3.6
V
Supply Voltage(Ground)
VSS,VSSQ
0
0
0
V
DC CHARACTERISTICS
Parameter
Standby Current ( Note3)
Symbol
Min
Max
Unit
Test Condition
ICC3P
-
150
uA
CKE≤VIL(Max), tCC=Min
ICC3PS
-
150
uA
CKE=0, tCC=Min
Active Standby Current
ICC3N
-
50
mA
CS≥VIH(Min), tCC=Min,
All Outputs Open
Burst Mode Operating Current
ICC4
-
100
mA
tCC=Min, All Outputs Open
Input Leakage Current
IIL
-10
10
uA
0V≤VIN≤VDD + 0.3V
Pins not under test=0V
Output Leakage Current (Dout Disabled)
IOL
-10
10
uA
(0V≤VOUT≤VDD Max)
Q# in High-Z
Input High Voltage, All Inputs
VIH
2.0
VDD + 0.3
V
(Note1)
Input Low Voltage, All Inputs
VIL
-0.3
0.8
V
(Note2)
Output High Voltage Level (Logic 1)
VOH
2.4
-
V
IOH=-2mA
Output Low Voltage Level (Logic 0)
VOL
-
0.4
V
IOL=2mA
Note : 1. VIH(Max)=4.6V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.
2. VIL (Min)=-1.5V for pulse width≤10ns acceptable, pulse width measured at 50% of pulse amplitude.
3. The condition is the same as Self Refresh Mode of SDRAM, that is, in this case CS,RAS,CAS have to be set to Low, MR has to be set to High.
K3S7V2000M-TC
Synch. MROM
AC OPERATING TEST CONDITIONS(TA = 0 to 70°C, VDD = 3.3V±0.3V, unless otherwise noted.)
Parameter
Value
Timing Reference Levels of Input/Output Signals
1.4V
Input Signal Levels
VIH/VIL=2.4V/0.4V
Transition Time (Rise & Fall) of Input Signals
tr/tf=1ns/1ns
Output Load
LVTTL
Note : If CLK transition time is longer than 1ns, timing parameters should be compensated. Add [(tr+tf)/2-1]ns for transition time longer than 1ns. Transition time is measured between VIL(Max) and VIH(Min).
3.3V
Vtt=1.4V
1200Ω
50Ω
VOH (DC)=2.4V, IOH =-2mA
Output
VOL (DC)=0.4V, IOL=2mA
870Ω
Output
Z0=50Ω
50pF
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETERS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
up to 100MHz
Min
CLK Cycle Time
tCC
Max
10
up to 83MHz
up to 66MHz
up to 50 Mhz
Min
Min
Max
Min
Max
15
-
20
-
ns
Max
12
Unit
CLK to Valid Output Delay
tSAC
-
6
-
6
-
6
-
6
ns
Data Output Hold Time
tOH
2
-
2
-
2
-
2
-
ns
CLK High Pulse Width
tCH
3
-
3.5
-
4
-
6.5
-
ns
CLK Low Pulse Width
tCL
3
-
3.5
-
4
-
6.5
-
ns
Row-active to Row-active
tRC
10
-
10
-
8
-
8
-
clks
Input Setup Time
tSS
2
-
3
-
4
-
4
-
ns
Input Hold Time
tSH
1
-
1
-
2
-
2
-
ns
CLK to Output in Low-Z
tSLZ
0
-
0
-
0
-
0
-
ns
CLK to Output in High-Z
tSHZ
-
7
-
8
-
10
-
15
ns
tT
0.1
10
0.1
10
0.1
10
0.1
10
ns
tVCVC
8
-
8
-
7
-
7
-
clks
Transition Time
Valid CAS Enable to Valid
CAS Enable
Notes
1
2
Note :
1. These tRC values are for BL=8. For BL=4, tRC=6 clks for up to 100MHz, tRC=6 clks for up to 83MHz, tRC=4 clks for up to 66MHz, tRC=4 clks for up to
50MHz, and tRC=3 clks for up to 33MHz.
RAS latency increase means, a simultaneous tRC increase in the same number of cycles.
( If RAS latency is 3 clks, tRC is 12 clks for BL=8.) Refer to attached technical note for gapless operation.
2. These tVCVC values are for BL=8. For BL=4, tVCVC=4clks for up to 100MHz, tVCVC=4clks for up to 83MHz, tVCVC=3clks for up to 66MHz, tVCVC=3clks for
up to 50MHz, and tVCVC=2clks for up to 33MHz.
Refer to attached technical note for gapless operation.
K3S7V2000M-TC
Synch. MROM
CAPACITANCE(TA=25°C, f=1MHz)
Parameter
Symbol
Min
Max
Unit
Input Capacitance
CIN
-
5
pF
Output Capacitance
COUT
-
7
pF
FUNCTION TRUTH TABLE
Command
Register
CKEn
CS
RAS
CAS
MR
DQM
Add.
WORD
Notes
1
H
X
L
L
L
L
X
Code
X
Row Active
Row Access & Latch
Row Access& Latch
H
X
L
L
H
H
X
RA
X
Read
Column Access & Latch
H
X
L
H
L
H
X
CA
X
(Burst Stop on Synch.DRAM)
H
X
L
H
H
L
X
X
X
(Precharge on Synch.DRAM)
Burst Stop
Power Down &
Clock Suspend
Mode Register Set
CKEn-1
Two Standby Mode
H
X
L
L
H
L
X
X
X
Entry
H
L
X
X
X
X
X
X
X
Exit
L
H
X
X
X
X
X
X
X
DQM
Illegal
H
V
X
3
(Write on Synch.DRAM)
H
X
L
H
L
L
X
CA
X
(Refresh on Synch.DRAM)
H
X
L
L
L
H
X
X
X
H
X
H
X
X
X
X
X
X
H
X
L
H
H
H
X
X
X
H
X
L
H
L
H
X
CA
No Operation Command
Organization Control
X
2
H
4
5
L
(V=Valid, X=Don't Care, H=Logic High, L=Logic Low)
Abbreviations (RA: Row Address, CA: Column Address, NOP: No Operation Command, DWM: Double Word Mode, WM: Word Mode)
Notes :
1. A0 ~ A6: Program keys (@MRS). After power up, mode register set, can be set before issuing other input command. After the mode register set command is completed, no new commands can be issued for 3 CLK Cycles, and CS or MR state must be defined "H" within 3 CLK cycles. Refer to the
Mode Register Field Table
2. In the case CKE is low, two standby modes are possible. Those are stand-by mode in power-down.
Power Down: CKE="L" (at all the parts except the range of Row Active, Read & Data out)
Clock Suspend: CKE="L" (at the range of Row Active, Read & Data Out)
3. DQM sampled at rising edge of a CLK makes a Hi-Z state the data-out state, delayed by 2CLK cycles.
4. Precharge command on Synch.DRAM can be used for Burst Stop operation during burst read operation only.
5. Mode selection control is decided simultaneously with column access start, and according to the polarity of WORD pin, "H" state is DWM,
"L" state is WM.
K3S7V2000M-TC
Synch. MROM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
A6
A5
A4
A3
A2
A1
A0
Function
RAS Latency
CAS Latency
Burst Type
Burst Length
RAS Latency
CAS Latency
Burst Type
Burst Length
A6
Length
A5
A4
A3
Length
A2
Type
A1
A0
Length
0
1
0
0
0
Reserved
0
Sequential
0
0
Reserved
1
2
0
0
1
Reserved
1
Interleave
0
1
4
0
1
0
3
1
0
8
0
1
1
4
1
1
Reserved
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
Reserved
Notes :
-. After power up, when user wants to change mode register set, user must exit from power down mode
and start mode register set before entering normal operation mode.
ADDRESSING MAP
(1) WORD = "H" : x32 Organization
Function
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Row Address
RA0
RA1
RA 2
RA3
RA4
RA5
Column Address
CA0
CA1
CA 2
CA3
CA4
CA5
RA6
RA7
RA 8
RA9
RA 10
RA11
RA12
CA6
CA7Note
X
X
X
X
X
Note : Column Address MSB (at x32 organization)
(X=Don't Care)
(2) WORD="L" : x16 Organization
Function
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Row Address
RA0
RA 1
RA2
RA 3
RA4
RA 5
RA6
RA7
RA8
RA9
RA10
RA11
RA 12
Column Address
CA0
CA 1
CA2
CA 3
CA4
CA 5
CA6
CA7
CA 8Note
X
X
X
X
Note : Column Address MSB (at x16 organization)
(X=Don't Care)
(3) Each address is arranged as follows
for X32 operation,
LSB
MSB
Address Register
AR20
AR19
AR18
...
AR9
AR8
AR7
AR6
...
AR3
AR2
AR1
AR0
Address
RA12
RA11
RA10
...
RA1
RA0
CA7
CA6
...
CA3
CA2
CA1
CA0
* Initial Address
- BL=4(CA0,CA1)
- BL=8(CA0,CA1,CA2)
BL=4
BL=8
for X16 operation,
when CA8 is set to Low, data belonging to 0~15th registers are output to Q0~Q15 pins, and when CA8 is set to High, data belonging
to16~31th registers are output to Q0~Q15 pins.
K3S7V2000M-TC
Synch. MROM
x32 operation (double word mode)
Column Address
D15 ~ D0 (Hexadecimal)
D31 ~ D16 (Hexadecimal)
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
0
0
0
0
0
0
0
0
A
A
A
A
0
0
0
0
0
0
0
0
0
0
0
1
B
B
B
B
1
1
1
1
0
0
0
0
0
0
1
0
C
C
C
C
2
2
2
2
0
0
0
0
0
0
1
1
D
D
D
D
3
3
3
3
0
0
0
0
0
1
0
0
E
E
E
E
4
4
4
4
0
0
0
0
0
1
0
1
F
F
F
F
5
5
5
5
x16 operation (word mode)
Column Address
Data Out (Hexadecimal)
Comment
CA8
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
0
0
0
0
0
0
0
0
0
A
A
A
A
D15 ~ D0
0
0
0
0
0
0
0
0
1
B
B
B
B
D15 ~ D0
0
0
0
0
0
0
0
1
0
C
C
C
C
D15 ~ D0
0
0
0
0
0
0
0
1
1
D
D
D
D
D15 ~ D0
0
0
0
0
0
0
1
0
0
E
E
E
E
D15 ~ D0
0
0
0
0
0
0
1
0
1
F
F
F
F
D15 ~ D0
:
1
0
0
0
0
0
0
0
0
0
0
0
0
D31 ~ D16
1
0
0
0
0
0
0
0
1
1
1
1
1
D31 ~ D16
1
0
0
0
0
0
0
1
0
2
2
2
2
D31 ~ D16
BURST SEQUENCE(BURST LENGTH = 4)
Initial address
A1
A0
0
0
Sequential
0
1
Interleave
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
BURST SEQUENCE(BURST LENGTH = 8)
Initial address
A2
A1
Sequential
Interleave
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
K3S7V2000M-TC
Synch. MROM
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as a reference for SMROM operation. A square wave signal(CLK) must be applied externally at cycle time
tCC. All operations are synchronized to the rising edge of the clock. The clock transitions must be monotonic between VIL and VIH.
During operation with CKE high, all inputs are assumed to be in valid state (low or high) for the duration of set-up and hold time
around the positive edge of the clock for proper functionality and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock into the SMROM and is asserted high during all cycles, except for power down, stand-by and
clock suspend mode. If CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen for as long as the CKE remains low. All other
inputs are ignored from the next clock cycle after CKE goes low. The SMROM remains in the power down mode ignoring other inputs
for as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at
least "1 CLK + tSS" before the rising edge of the clock, then the SMROM becomes active from the same clock edge accepting all the
input commands.
NOP and DEVICE DESELECT
When RAS, CAS and MR are high, the SMROM performs no operation (NOP). NOP does not initiate any new operation. Device
deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, MR and all
the address inputs are ignored. In addition, entering a mode register set command in the middle of a normal operation, results in an
illegal state in SMROM.
POWER-UP
The following power-up sequence is recommended.
1. Apply power and start clock, Attempt to maintain MR, CKE and DQM inputs to pull them high and the other pins are NOP condition
at the inputs before or along with VDD(and VDDQ) supply.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 20us.
3. When user wants to change the default mode register set values, perform a MODE REGISTER SET cycle to program the RAS
latency, CAS latency, burst length and burst type.
4. At the end of three clock cycles after the mode register set cycle, the device is ready for operation. When the above sequence is
used for power-up, all outputs will be in high impedance state. The high impedance of outputs is not guaranteed in any other
power-up sequence.
MODE SELECTION CONTROL
Mode selection control is decided simultaneously with column access, and according to WORD pin voltage level. High level signifies
double word mode(x32) and low level signifies word mode(x16).
ADDRESS DECODING
The address bits required to decode one of the available cell locations out of the total depth are multiplexed onto the address select
pins and latched by externally applying two commands. The first command, RAS asserted low, latches the row address into the
device. A second command, CAS asserted low, subsequently latches the column address.
K3S7V2000M-TC
Synch. MROM
DEVICE OPERATIONS
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various operating modes of SMROM. It programs the RAS latency, CAS latency,
burst length, burst type. On power-up, the mode register is set to the default value defined by the user requirement. When and if the
user wants to change its values, the user must exit from power down mode and start mode register set before entering normal operation mode. The mode register is reprogrammed by asserting low on CS, RAS, CAS and MR (The SMROM should be in active mode
with CKE already high prior to writing the mode register). The state of address pins A 0 ~ A7 in the same cycle as CS, RAS, CAS and
MR going low is the data written in the mode register. Three clock cycles are required to complete the program in the mode register,
therefore after mode register set command is completed, no new commands can be issued for 3 clock cycles and CS or MR must be
fixed to high within 3 clock cycles. The mode register is divided into various fields depending on functionality. The burst length field
uses A0 ~ A1, burst type uses A2, CAS latency (read latency from column address) uses A3 ~ A5, RAS latency uses A6 (RAS to CAS
delay). Refer to the table for specific codes for various burst length, burst type, CAS latencies and RAS latencies.
LATENCY
There are latencies between the issuance of a Row active command and when data is available on the I/O buffers. The RAS to CAS
delay is defined as the RAS latency. The CAS to data out delay is the CAS latency. The CAS and RAS latencies are programmable
through the mode register. RAS latencies of 1 and 2, and CAS latencies of 3 through 6 are supported. It is understood that some
RAS and CAS latency values are reserved for future use, and may not be available in the first generation for SMROM. The followings
are the supported minimum values in the first generation. RAS latency=2, and CAS latency=5 for 100MHz operation, and RAS
latency=2, and CAS latency=5 for 83MHz operation, and RAS latency=1, and CAS latency=4 for 66MHz operation, and RAS
latency=1, and CAS latenecy=4 for 50MHz operation, and RAS latency=1, and CAS latenecy=3 for 33MHz operation.
DQM OPERATION
The DQM is used to mask output operations when a complete burst read is not required. It works similar to OE during a read operation. The read latency is two cycles from DQM, which means DQM masking occurs two cycles later in the read cycle. DQM operation
is synchronous with the clock. The masking occurs for a complete cycle. (Also refer to the DQM timing diagram)
BURST READ
The burst read command is used to access a burst of data on consecutive clock cycles from an active row state. The burst read command is issued by asserting low CS and CAS with MR being high on the rising edge of the clock. The first output appears in CAS
latency number of clock cycles after the issuance of the burst read command. The burst length, burst sequence and latency from the
burst read command are determined by the mode register which is already programmed. Burst read can be initiated on any column
address of the active row. The output goes into high-impedance at the end of the burst, unless a new burst read is initiated to keep
the data output gapless. The burst read can be terminated by issuing another burst read.
K3S7V2000M-TC
Synch. MROM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. MRS
Mode Register Set
CLK
CMD
MRS
ACT
Note 1
3CLK
2. CLOCK Suspend
Clock Suspended During Burst Read (BL=4)
CLK
CMD
RD
CKE
Masked by CKE
Internal
CLK
Data
Q0
D
Q01
Q2
Q3
Suspended Dout
: This command do not be activated.
3. Clock Suspend Exit & power Down Exit
1) Clock Suspend Exit
2) Power Down Exit
CLK
CKE
CLK
tSS
CKE
Internal
CLK
CMD
tSS
Internal
CLK
RD
CMD
NOP ACT
Note :
1. After mode register set command is completed, no new commands can be issued for 3 clock cycles, and MR or CS should be fixed "H"
within a minimum of 3 clock cycles.
K3S7V2000M-TC
Synch. MROM
4. DQM Operation
1) Read Mask (BL=4)
CLK
CMD
RD
DQM
Data(CL2)
Q0
Q1
Data(CL3)
Q0
Masked by DQM
Hi-Z
Q3
Hi-Z
Hi-Z
Data(CL4)
Q2
Q3
Q1
Q2
Q3
DQM to Data-out Mask = 2CLKs
2) DQM with Clock Suspended (BL=8)
CLK
CMD
RD
CKE
DQM
Note 1
Data(CL2)
Data(CL3)
Data(CL4)
Q0
D 1 Q1
Q0
Hi-Z
Hi-Z
Hi-Z
Q3
Q2
Q1
*Note :
1. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
Hi-Z
Hi-Z
Hi-Z
Q5
Q4
Q3
Hi-Z
Hi-Z
Hi-Z
Q7
Q8
Q6
Q7
Q8
Q5
Q6
Q7
K3S7V2000M-TC
Synch. MROM
Read Cycle I : Normal @RAS Latency=2, CAS Latency=5, Burst Length=4
0
1
2
3
tCH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCL
tCC
HIGH
CKE
tRC
tSH
CS
RAS
Latency
tSS
tSH
RAS
tSS
CAS
tSH
ADDR
RAa
CAa
RAb
CAb
tSS
tRC=6 clocks at BL=4
*Note 1
tOH
Qa0 Qa1 Qa2 Qa3
Data
tSAC
Qb0 Qb1 Qb2 Qb3
tSHZ
MR
Row Active
Read
Row Active
Read
*Note:
1. When the burst length is 4 at 100MHz, tRC is equal to 6 clock cycles.
: Don't Care
K3S7V2000M-TC
Synch. MROM
Read Cycle II : Consecutive Column Access @RAS Latency = 2, CAS Latency=5, BL = 4
0
1
2
3
tCH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCL
tCC
HIGH
CKE
tSH
CS
tSS
RAS
Latency
tSH
RAS
tSS
CAS
tSH
ADDR
RAa
CAa
CAb
*Note 1
tSS
tVCVC=4 clocks at BL=4
tOH
Data
Burst Length=4
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
tSAC
tSHZ
MR
Row Active
Read
Read
: Don't Care
Note:
When column access is initiated beyond tVCVC,
1. at BL=4, CAa access read is completed, CAb access read begins.
K3S7V2000M-TC
Synch. MROM
Read Cycle III : Clock Suspend @RAS Latency = 2, CAS Latency=5, Burst Length=4
0
1
2
3
tCH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCL
tCC
CKE
*Note 1
Internal
CLK
CS
RAS
Latency
tSH
RAS
tSS
CAS
tSH
ADDR
RAa
CAa
tSS
tVCVC= 4 clocks at BL=4
*Note 2
Data
Burst Length=4
Qa0
Qa1
Qa2 Qa3
MR
Row Active
Read
Clock Suspend Resume
Note :
1. From next clock after CKE goes low, clock suspension begins.
2. For clock suspension, data output state is held & maintained.
: Don't Care
K3S7V2000M-TC
Synch. MROM
Read Interrupted by Precharge Command & Burst Read Stop Cycle @Burst Length=8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
HIGH
CKE
CS
RAS
CAS
ADDR
RAa
CAa
CAb
Note1
Note1
CL=2
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5
Qa0 Qa1 Qa2 Qa3 Qa4
Data
Note2
Note2
Qa0 Qa1 Qa2 Qa3 Qa4
CL=3
Qb0 Qb1 Qb2 Qb3 Qb4 Qb5
MR
DQM
*Note1, 2
Row Active
Read
Burst Stop
Read
Precharge
: Don't Care
*Note :
1. The burst stop command is valid at every page burst length.
The data bus goes to High-Z after the CAS latency from the burst stop command is issued.
2. The interval between read command (column address presented) and burst stop command is 1 cycle(min).
K3S7V2000M-TC
Synch. MROM
Power Down & Clock Suspend Cycle :
@RAS Latency = 2, CAS Latency=5, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
tSS
CKE
*Note 1
*Note 1
Power Down
Clock Suspend
CLK
(internal)
CS
RAS
CAS
*Note 2
ADDR
tSH
NOP RAa
CAa
tSS
Data
MR
Data Hi-Z State
Qa0 Qa1
Qa2
Qa3
(High)
Row Active Read
Power-down
Entry
Power-down
Exit
Clock Suspend
Entry
Note :
1. From next clock after CKE goes low, clock suspend and power down begins.
2. After power down exit, NOP should be issued and new command can be issued after 1clock.
Clock Suspend
Exit
: Don't Care
K3S7V2000M-TC
Synch. MROM
Mode Register Set:
@RAS Latency = 2, CAS Latency=5, Burst Length=4
0
1
2
3
tCH
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CLK
tCC
tCL
HIGH
CKE
tSH
CS
tSS
RAS
RAS
Latency
CAS
ADDR
Code
RAa
Data Hi-Z State
Data
CAa
Qa0 Qa1 Qa2 Qa3
MR
MRS
Row Active
: Don't Care
Note :
1. After the mode register set is completed, no new commands can be issued for 3CLK cycles.
2. After power up, necessarily mode register set should be completed at least one time and CS or MR must be fixed "H" within
3clock cycles, and when user wants to change mode register set, user must exit from power down mode and start mode register set before chip enters normal operation mode.
K3S7V2000M-TC
Synch. MROM
FUNCTION TRUTH TABLE
Current
State
After
Power Up*
Row Active
Input Signal
CS
RAS
CAS
MR
Add.
L
X
X
X
X
X
H
L
L
H
H
RA
H
L
L
L
L
Code
H
L
L
H
H
RA
-. If consecutive row access is issued within
tRCmin. without CAS enabling, only the final
RA is valid.
H
L
H
L
H
CA
-. Begin READ ; latch CA
H
L
L
L
L
Code
L
X
X
X
X
X
H
READ
Next State Operation
CKE
L
L
H
H
-. Power Down
-. Row Active ; latch RA
-. Mode Register Set
Illegal *
-. Clock Suspend
RA
-. Row Access in Read State,
within the tRC, previous read is ignored and
new row is activated.
beyond the tRC, previous read is completed
and new read begins.
H
L
H
CA
-. Consecutive Column Access,
within the t VCVC, only the final CA is valid
and the previous burst read is ignored.
Beyond the tVCVC, the previous read is
completed and new read begins.
L
L
H
L
X
-. NOP (After Burst Read) / Read Interrupt
L
H
H
L
X
-. NOP (After Burst Read) / Read Interrupt
H
L
H
H
H
L
L
L
L
Code
L
X
X
X
X
X
-. Clock Suspend / Power Down
Any State
L
L
L
L
H
X
-. Low Power Consumption Mode
Any State
H
L
H
H
H
X
NOP
H
L
L
L
H
X
Illegal
H
L
H
L
L
CA
Illegal
Any State
Illegal *
* : After the power up, when user wants to change MR set, user must exit from power down mode and start MR set before chip enters normal operation
mode.
K3S7V2000M-TC
Synch. MROM
Technical Notes
1. Frequency vs. AC Parameter Relationship Table
K3S7V2000M-TC10
( unit : number of clock )
Burst Length
RAS Latency
4
2
8
CAS Latency
tRCmin.
tVCVCmin.
5
6
4*
6
7
5
5
10
8*
6
11
9
2
K3S7V2000M-TC12
( unit : number of clock )
Burst Length
RAS Latency
4
2
8
CAS Latency
tRCmin.
tVCVCmin.
5
6
4*
6
7
5
5
10
8*
6
11
9
2
K3S7V2000M-TC15
Burst Length
( unit : number of clock )
RAS Latency
1
CAS Latency
tRCmin.
tVCVCmin.
4
4*
3/ 4*
5
5
4*
6
6
5
4
5
3/ 4*
5
6
4*
6
7
5
4
8*
7/ 8*
5
9
8*
6
10
9
4
9
7/8*
5
10
8*
6
11
9
4
2
1
8
2
K3S7V2000M-TC
Synch. MROM
K3S7V2000M-TC20
Burst Length
( unit : number of clock )
RAS Latency
CAS Latency
tRCmin.
tVCVCmin.
4
4*
3/ 4*
5
5
4*
6
6
5
4
5
3/4*
5
6
4*
6
7
5
4
8*
7/8*
5
9
8*
6
10
9
4
9
7/ 8*
5
10
8*
6
11
9
1
4
2
1
8
2
K3S7V2000M-TC30
Burst Length
( unit : number of clock )
RAS Latency
CAS Latency
tRCmin.
tVCVCmin.
3
3/ 4*
2/ 4*
4
4*
3/ 4*
5
5
4*
6
6
5
3
4*
2/4*
4
5
3/4*
5
6
4*
6
7
5
3
7/ 8*
6/ 8*
4
8*
7/ 8*
5
9
8*
6
10
9
3
8*
6/8*
4
9
7/8*
5
10
8*
6
11
9
1
4
2
1
8
2
Note :
Above tables are not specification values, rather actual values.
There are no gapless operations for CAS latency 6.
* : Minimum clocks for Gapless Operation.
K3S7V2000M-TC
Synch. MROM
Technical Notes (Continuous)
2. CAS Interrupt
Read interrupted by Read (BL=4)Note 1
CLK
CMD
RD
RD
ADD
A
B
Data(CL2)
QB0
Data(CL3)
QB1
QB2
QB3
QB0
QB1
QB2
QB3
QB0
QB1
QB2
Data(CL4)
QB 3
Note 2
*Note :
1. By " Interrupt", It is meant to stop burst read by external command before the end of burst.
By "CAS Interrupt", to stop burst read by CAS access.
2. CAS to CAS delay. (=1CLK)
3. Read interrupt operation by issuing the precharge or Burst Stop Command
CASE I ) Issued read Interrupt command during burst read operation period.
CLK
CMD
CLK
RD
PRE
CMD
RD
STOP
Note 1
Data(CL2)
Q0
Q1
Q0
Data(CL3)
Note 1
Data(CL4)
Q0
Data(CL2)
Q1
Q0
Q0
Data(CL3)
Q1
Q1
Q1
Q0
Data(CL4)
CASE II ) Issued read Interrupt command between read command and data out.
CLK
CMD
CLK
RD
PRE
CMD
Note 2
Data(CL2)
Data(CL3)
Data(CL4)
RD
STOP
Note 2
Q0
Data(CL2)
Q0
Data(CL3)
Q0
Data(CL4)
*Note :
1. The data bus goes to High-Z after CAS Latency from the burst stop (or precharge) command.
2. Valid output data will last up to CL-1 clock cycle from PRE command.
Q0
Q0
Q0
Q1
K3S7V2000M-TC
Synch. MROM
4. Read cycle depending on t RC
@ RL = 2, CL = 5, BL = 4 ; 100MHz
CLK
tRC(min)=6
tCC=10ns
CMD ACT
RDa
RDb
ACT
CASE I )
RDb
ACT
ACT
CASE II )
RDb
CASE III )
High-Z
CASE I )
Qb0
CASE II )
Qa0
Qa1
Qa2
Qa3
CASE III )
Qa0
Qa1
Qa2
Qa3
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb3
@ RL = 2, CL = 5, BL = 4 ; 83MHz
CLK
tRC(min)=6
tCC=12ns
CMD ACT
RDa
RDb
ACT
CASE I )
RDb
ACT
ACT
CASE II )
RDb
CASE III )
High-Z
CASE I )
Qb0
CASE II )
Qa0
Qa1
Qa2
Qa3
CASE III )
Qa0
Qa1
Qa2
Qa3
@ RL = 1, CL = 4, BL = 4 ; 66MHz
CLK
tRC(min)=4
tCC=15ns
CMD ACT RDa
CASE I )
ACT RDb
RDb
ACT
CASE II )
ACT RDb
CASE I )
CASE III )
High-Z
Qb0 Qb1
Qb2
Qb3
Qb1
Qb2
Qb3 (Gapless Operation)
Qb0
Qb1
Qb2
CASE II )
Qa0
Qa1
Qa2
Qa3
CASE III )
Qa0
Qa1
Qa2
Qa3
Qb0
Qb3
Qb3
K3S7V2000M-TC
Synch. MROM
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tRC(min)=4
CMD ACT RDa
tCC=20ns
ACT RDb
CASE I )
ACT RDb
CASE II)
ACT RDb
CASE III)
CASE I )
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
(Gapless Operation)
CASE II )
Qa0
Qa1
Qa2
Qa3
CASE III )
Qa0
Qa1
Qa2
Qa3
Qb3
: Invalid Data
@ RL = 1, CL = 3, BL = 4 ; 33MHz
CLK
tRC(min)=3
tCC=30ns
CMD ACT RDa ACT RDb
ACT
CASE I)
RDb
CASE II)
ACT
RDb
CASE III)
Qb0
CASE I )
CASE II )
Qa0
Qa1 Qa2
CASE III )
Qa0
Qa1
Qb1
Qb2
Qb3
Qb1
Qb2
Qb3
Qb0
Qb1
Qb2
(Gapless Operation)
Qa2
Qa3
Qb3
: Invalid Data
K3S7V2000M-TC
Synch. MROM
5. Read cycle depending on tVCVC
@ RL = 2, CL = 5, BL = 4 ; 100MHz
CLK
tCC=10ns
tVCVC=4
CMD ACT
RDb
RDa
CASE I)
RDb CASE II)
RDb CASE III)
CASE I )
Qb0 Qb1 Qb2 Qb3
(Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
CASE II )
CASE III )
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 2, CL = 5, BL = 4 ; 83MHz
CLK
tVCVC=4
CMD ACT
tCC=12ns
RDb
RDa
CASE I)
RDb CASE II)
RDb CASE III)
CASE I )
Qb0 Qb1 Qb2 Qb3
(Gapless Operation)
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
CASE II )
CASE III )
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 4, BL = 4 ; 66MHz
CLK
tCC=15ns
tVCVC=3
CMD ACT RDa
RDb
CASE I)
RDb CASE II)
RDb CASE III)
CASE I )
Qb0 Qb1 Qb2 Qb3
CASE II )
Qa0 Qa1 Qb2
Qb1 Qb2 Qb3
CASE III )
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
(Gapless Operation)
: Invalid Data
K3S7V2000M-TC
Synch. MROM
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=3
RDb
CMD ACT RDa
tCC=20ns
CASE I)
RDb
CASE II)
RDb
CASE III)
CASE I )
Qb0 Qb1
Qa0 Qa1 Qa2
CASE II )
Qb2 Qb3
Qb1 Qb2 Qb3
(Gapless Operation)
CASE III )
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
: Invalid Data
@ RL = 1, CL = 3, BL = 4 ; 33MHz
CLK
tVCVC=2
CMD ACT RDa RDb
tCC=30ns
CASE I)
RDb
CASE II)
RDb
CASE I )
CASE III)
Qb0 Qb1 Qb2 Qb3
CASE II )
Qa0 Qa1
CASE III )
Qa0 Qa1 Qa2
Qb1 Qb2 Qb3
Qb1 Qb2 Qb3
: Invalid Data
K3S7V2000M-TC
Synch. MROM
6. Read Cycle depending on tVCVC and tRC
@ RL = 1, CL = 4, BL = 4 ; 50MHz (Gapless Operation)
CLK
tVCVC=4
CMD ACT RDa
tCC=20ns
RDb
ACT RDc
RDd
ACT RDe
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 Qd0 Qd1 Qd2
Read out
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4
CMD ACT RDa
tCC=20ns
RDb
ACT RDc
Qa0 Qa1 Qa2 Qa3
Read out
RDd
ACT RDe
RDf
Qe0
Qc0 Qc1 Qc2 Qc3
: Invalid Data
@ RL = 1, CL = 4, BL = 4 ; 50MHz
CLK
tVCVC=4
CMD ACT RDa
Read out
tCC=20ns
RDb ACT RDc
RDd ACT RDe
RDf
Qa0 Qa1 Qa2
Qc0 Qc1 Qc2
Qe0 Qe1 Qe2
: Invalid Data