PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L OVERVIEW 80-QFP-1420C The KB9223 is a 1-chip BICMOS integrated circuit to perform the function of RF amp and servo signal processor for compact disc player applications.It consist of blocks for RF signal processing ,focus, tracking, sled and spindle servo.Also this IC has adjustment free function and embedded opamp for audio post filter. FEATURES • RF amplifier & RF equalizer ORDERING INFORMATION • Focus error amplifier & servo control • Tracking error amplifier & servo control Device • Mirror & defect detector circuit KB9223 • Focus OK detector circuit KB9223-L Package Tempe. Range 80-QFP-1420C -20°C ~ +70°C • APC(Auto Laser Power Control) circuit for constant laser APPLICATIONS power • FE bias & focus servo offset adjustment free • CD Player • EF balance & tracking error gain adjustment free • Video-CD • Embedded audio post filter RELATED PRODUCT • The circuit for Interruption countermeasure • Double speed play available • KS9286 Data Processor • Operating voltage range • KS9284 Data Processor • KA9258D/KA9259D Motor Driver KB9223 : 5V KB9223-L : 3.4V M/M-97-P006 1997. 10. 17 1 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L RF- ISTAT RESET MLT MDATA MCK ATSC TZC 29 31 38 37 36 35 51 52 73 RFO 74 PD1 65 PD2 66 FEBIAS 63 58 26 28 27 3 Focus Phase Compensation Micom Data Interface Logic RF Amp FRSH LOCK 30 FS3 TRCNT 22 FGD WDCH 54 FE2 TE1 59 FLB FE1 BLOCK DIAGRAM & Offset cancel circuit Focus Error Amp FE-BIAS Adjustment F 67 E 68 EI 79 PD Tracking Error Amp E/F Balance & Gain Control MICOM TO SERVO CONTROL AUTO SEQUENCER 69 APC Amp LD Tracking Phase Compensation Block & Jump Pulse GEN. LDON 70 Sled Servo Amplifier ADJUSTMENT-FREE CONTROL 33 RFI 77 DCB DCC2 2 4 Spindle Servo LPF ( Double Speed ) EFM Comparator Mirror Detection Circuit Built-in Post Filter Amp ( L&R ) Defect Detection Circuit FOK Detection Circuit 5 15 16 13 14 19 17 12 11 9 10 GC2O EFM GC2I 32 GA1~ GA5 CH2I ASY TM1~ BAL1~ PS1~ TM6 BAL5 PS4 CH2O 75 FS1~ FS4 RRC IRF RF Level AGC & Equalizer MUTEI 76 CH1I EQO CH1O 78 & Sled Kick GEN. GC1I EQC Center Voltage Amp. GC1O 71 DCC1 VR 60 FDFCT 47 FE- 48 FEO 57 TDFCT 49 TE- 50 TEO 53 TE2 55 LPFT 62 TG2 61 TGU 43 SLO 44 SL- 42 SL+ 46 SPDLO 45 SPDL- 23 SMDP 24 SMON 25 SMEF 6 FSET 39 MIRROR 1 MCP 40 FOK Figure 1. Block diagram M/M-97-P006 1997. 10. 17 2 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L PIN CONFIGURATION 65 PD1 SSTOP SL+ SLO SL- SPDL- SPDLO FE- FEO TE- TEO TZC ATSC TE2 TE1 LPFT DVDD TDFCT FE2 FE1 TGU FDFCT TG2 FEBIAS DVEE 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 FOK 40 66 PD2 MIRROR 39 67 F RESET 38 68 E MLT 37 69 PD MDATA 36 70 LD MCK 35 71 VR VSSA 34 KB9223 72 VCC EFM 33 73 RF- ASY 32 74 RFO ISTAT 31 75 IRF TRCNT 30 76 EQO LOCK 29 77 RFI FGD 28 78 EQC FS3 27 79 EI FLB 26 SMON SMDP WDCK GC2O VREG GC2I 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ISET VCCP MUTEI VDDA 5 VSSP FSET 4 RRC DCC1 3 GC1I DCC2 GC1O FRSH 2 CH1I DCB 1 CH2I MCP CH1O SMEF 25 CH2O 80 GND Figure 2. Pin configuration M/M-97-P006 1997. 10. 17 3 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L PIN DESCRIPTION Table 1. PIN DESCRIPTION Pin No. Symbol Description 1 MCP Capacitor connection pin for mirror hold 2 DCB Capacitor connection pin for defect Bottom hold 3 FRSH Capacitor connection pin for time constant to generate focus search waveform 4 DCC2 The input pin through capacitor of defect bottom hold output 5 DCC1 The output pin of defect bottom hold 6 FSET The peak frequency setting pin for focus,tracking servo and cut off frequency of CLV LPF 7 VDDA Analog VCC for servo part 8 VCCP VCC for post filter 9 GC2I Amplifier negative input pin for gain and low pass filtering of DAC output CH2 10 GC2O Amplifier output pin for gain and low pass filtering of DAC output CH2 11 CH2I The input pin for post filter channel2 12 CH2O The output pin for post filter channel2 13 CH1O The output pin for post filter channel1 14 CH1I The input pin for post filter channel1 15 GC1O Amplifier output pin for gain and low pass filtering of DAC output CH1 16 GC1I Amplifier negative input pin for gain and low pass filtering of DAC output CH1 17 RRC The pin for noise reduction of post filter bias 18 VSSP VSS for post filter 19 MUTEI The input pin for post filter muting control 20 ISET 21 VREG The output pin of regulator 22 WDCK The clock input pin for auto sequence 23 SMDP The input pin of CLV control output pin SMDP of DSP 24 SMON The input pin for spindle servo ON through SMON of DSP 25 SMEF The input pin of provide for an external LPF time constant 26 FLB The input pin for current setting of focus search,track jump and sled kick voltage Capacitor connection pin to perform rising low bandwidth of focus loop M/M-97-P006 1997. 10. 17 4 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 1. PIN DESCRIPTION (Continued) Pin No. Symbol Description 27 FS3 The pin for high frequency gain change of focus loop with internal FS3 switch 28 FGD Reducing high frequency gain with capacitor between FS3 pin 29 LOCK Sled runaway prevention pin 30 TRCNT Track count output pin 31 ISTAT Internal status output pin 32 ASY The input pin for asymmetry control 33 EFM EFM comparator output pin 34 VSSA Analog VSS for servo part 35 MCK Micom clock input pin 36 MDATA Micom data input pin 37 MLT 38 RESET 39 MIRROR 40 FOK The output pin of focus OK comparator 61 TGU The capacitor connection pin for high frequency tracking gain switch 62 TG2 The pin for high frequency gain change of tracking servo loop with internal TG2 switch 63 FEBIAS 64 DVEE 65 PD1 The negative input pin of RF I/V amplifier1(A+C signal) 66 PD2 The negative input pin of RF I/V amplifier2(B+D signal) 67 F The negative input pin of F I/V amplifier (F signal) 68 E The negative input pin of E I/V amplifier(E signal) 69 PD The input pin for APC 70 LD The output pin for APC 71 VR The output pin of (AVEE+AVCC)/2 voltage 72 VCC VCC for RF part 73 RF- RF summing amplifier inverting input pin 74 RFO RF summing amplifier output pin Micom data latch input pin Reset input pin The mirror output for test Focus error bias voltage control pin The DVEE pin for logic circuit M/M-97-P006 1997. 10. 17 5 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 1. PIN DESCRIPTION (Continued) Pin No. Symbol Description 75 IRF 76 EQO 77 RFI Tne input pin for EFM comparision 78 EQC The capacitor connection pin for AGC 79 EI 80 GND The input pin for AGC The output pin for AGC Feedback input pin of E I/V amplifier for EF Balance control GND for RF part M/M-97-P006 1997. 10. 17 6 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Characteristic Symbol Value Unit Vmax 6 V PD 200 mW Operating Temperature TOPR -20 ~ +70 o C Storage temperature TSTG -55 ~ +150 o C Supply Voltage Power Dissipation ELECTRICAL CHARACTERISTICS Table 3. Electrical Characteristics (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Supply Current High ICCHI Supply Current Typ Test Conditions Output Min Typ Max Unit VCC=6V,No load - 20 40 60 mA ICCTY VCC=5V,No Load - 12 30 48 mA Supply Current Low ICCLO VCC=3.4V,No Load - 10 25 40 mA RF Amp Offset Voltage Vrfo input open pin 74 -80 0 +80 mV RF Amp Voltage Gain Grf SG3 f=10KHz,40mVp-p,sine pin 74 25.1 28.1 31.1 dB RF THD Grfmd SG3 f=1KHz,40mVp-p,sine pin 74 - - 5 % RF Amp Max. Output Voltage Vrfpp1 SG3 DC 2.7V pin 74 3.8 - - V RF Amp Min. Output Voltage Vrfpp2 SG3 DC 2.3V pin 74 - - 1.2 V Focus Error Amp Offset Voltage Vfeo1 input open pin 59 -450 -250 -50 mV Focus Error Amp Auto Offset Voltage Vfeo2 WDCH=88.2KHz Pulse ,$841 pin 59 -35 0 35 mV Focus Error Amp PD1 Voltage Gain Gfe1 SG3 f=10KHz,32mVp-p,sine pin 59 27 30 33 dB Focus Error Amp PD2 Voltage Gain Gfe2 SG3 f=10KHz,32mVp-p,sine pin 59 27 30 33 dB Focus Error Amp Voltage Difference Gfe∆ ∆Gfe1-∆Gfe1 pin 59 -3 0 +3 dB Focus Error Amp Max. Output Voltage Gfepp1 SG3 DC 2.7V pin 59 4.4 - - V Focus Error Amp Min. Output Voltage Gfepp2 SG3 DC2.3V pin 59 - - 0.6 V AGC Max Gain Gagc SG4 f=500KHz,20mVp-p,sine pin 76 16 19 22 dB AGC EQ Gain Geq Gain Difference of Gagc at f=1.5MHz pin 76 0 1 2 dB AGC Gain2 Gagc2 SG4 f=500KHz,0.5Vp-p,sine pin 76 3.5 6 9 dB AGC Cpmpress Ratio Cagc Gain Difference of Gagc2 at 0.1Vp-p pin 76 0 2.5 5 dB AGC Frequency Fagc Gain Difference SG4 f=1.5MHz,0.1Vp-p,sine and f=500KHz,0.1Vp-p,sine pin 76 -1.5 0 2.5 dB M/M-97-P006 1997. 10. 17 7 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Tracking Error Offset Voltage Vteo Tracking Error Amp Voltage Gain F Test Conditions Output Min Typ Max Unit $800,$820,input open pin 54 -50 0 +50 mV Gtef $800,$820 SG3 0.3Vp-p,10KHz,sine pin 54 2.1 5.1 8.1 dB Tracking Error AmpVoltage Gain E Gtee SG3 0.3Vp-p,40KHz,sine pin 54 -0.75 2.25 5.25 dB Tracking Error Amp Voltage Gain Difference Gte∆ Gtef-Gtee pin 54 -0.25 2.75 5.75 dB Tracking Error Amp Maximum Output Voltage H Vtepp1 DG3 DC 4.5V pin 54 3.5 - - V Tracking Error Amp Minimum Output Voltage L Vtepp2 SG3 DC 0.5V pin 54 - - 1.5 V Tracking Error Amp Gain up F Tguf $830 SG3 0.3Vp-p,10KHz,sine pin 54 8.0 11.0 14.0 dB Tracking Error Amp Gain up E Tgue $830 SG3 0.3Vp-p,10KHz,sine pin 54 5.3 8.3 11.3 dB Tracking Gain Normal Fgfn SG3 0.3Vp-p,10KHz,sine,$820 pin 54 2.1 5.1 8.1 dB Tracking F Gain 1 Fgf1 SG3 0.3Vp-p,10KHz,sine,$821 pin 54 0.1 3.1 6.1 dB Tracking F Gain 2 Fgf2 SG3 0.3Vp-p,10KHz,sine,$822 pin 54 -1.7 1.3 4.3 dB Tracking F Gain 3 Fgf3 SG3 0.3Vp-p,10KHz,sine,$824 pin 54 -5.0 -2.0 1.0 dB Tracking F Gain 4 Fgf4 SG3 0.3Vp-p,10KHz,sine,$824 pin 54 -9.2 -6.2 -3.2 dB Tracking E Balance Normal Tben SG3 0.3Vp-p,10KHz,sine,$800 pin 54 -0.27 2.27 5.27 dB Tracking E Balance 1 Tbe1 SG3 0.3Vp-p,10KHz,sine,$801 pin 54 -0.51 2.51 5.51 dB Tracking E Balance 2 Tbe2 SG3 0.3Vp-p,10KHz,sine,$802 pin 54 -0.74 2.74 5.74 dB Tracking E Balance 3 Tbe3 SG3 0.3Vp-p,10KHz,sine,$804 pin 54 0.17 3.17 6.17 dB Tracking E Balance 4 Tbe4 SG3 0.3Vp-p,10KHz,sine,$808 pin 54 1.03 4.03 7.03 dB Tracking E Balance 5 Tbe5 SG3 0.3Vp-p,10KHz,sine,$810 pin 54 2.63 5.63 8.63 dB FGFN-FGF1 ∆FG1 - - 0 1.5 3 dB FGFN-FGF2 ∆FG2 - - 0.5 2.0 3.5 dB FGFN-FGF3 ∆FG3 - - 2.0 3.25 4.5 dB FGFN-FGF4 ∆FG4 - - 3.0 4.25 5.5 dB TBE5 - TBE4 ∆TB1 - - 0.6 1.6 2.6 dB TBE4 - TBE3 ∆TB2 - - -0.14 0.86 1.86 dB TBE3 - TBE2 ∆TB3 - - -0.57 0.43 1.43 dB TBE2 - TBE1 ∆TB4 - - -0.77 0.23 1.23 dB APC PSUB Voltage 1 Vapc1 LDON,$853,PN=open, SG4 GND+85mV pin 70 - - 1.2 V APC PSUB Voltage 2 Vapc2 LDON,$853,PN=open, SG4 GND+185mV pin 70 3.8 - - V M/M-97-P006 1997. 10. 17 8 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol APC NSUB Voltage 1 Vapc3 APC NSUB Voltage 2 Test Conditions Output Min Typ Max Unit LDON,$857,PN=2.5V, SG4 GND+95mV pin 70 3.8 - - V Vapc4 LDON,$857,PN=2.5V, SG4 GND+165mV pin 70 - - 1.2 V APC LD Off Voltage 1 Vapc5 LDOFF,$85C,PN=open,SG4 2.5V pin 70 4.0 - - V APC LD Off Voltage 2 Vapc6 LDOFF,$858,PN=2.5V.SG4 2.5V pin 70 - - 1.0 V APC Maximum Output Current H Vapc7 LDON,$854,PN=open, SG4 GND + 185mV pin 70 2.5 - - V APC Minimum Output Current L Vapc8 LDON,$854,SG4 GND + 85mV pin 70 - - 2.5 V Mirror Maximum Output Voltage H Vmirh SG4 2.1V+0.8Vp-p,1KHz,sine pin 39 4.3 - - V Mirror Minimum Output Voltage L Vmirl SG4 2.1V+0.8Vp-p,1KHz,sine pin 39 - - 0.7 V Mirror Minimum Operating Frequency Fmirh SG4 2.1V+0.8Vp-p,900Hz,sine pin 39 - 550 900 Hz Mirror Maximum Operating Frequency Fmirb SG4 2.1V+0.8Vp-p,30KHz,sine pin 39 30 75 - KHz Mirror AM Frequency Characteristic Fmir SG4 2.1V+0.8Vp-p 600Hz,fc=500KHz 55% modulation pin 39 - 400 600 Hz Mirror Minimum Input Voltage Vmir SG4 2.1V+0.2Vp-p,10KHz,sine pin 39 - 0.1 0.2 V Mirror Maximum Input Voltage Vmih SG4 2.1V+1.8Vp-p,10KHz,sine pin 39 1.8 - - V FOK Threshold Voltage Vfokt SG4 2.25V~2.0V,DCsweep, 10mV step pin 40 -420 -360 -300 mV FOK Output Voltage H Vfokh SG4 DC 1.5V pin 40 4.3 - - V FOK Output Voltage L Vfokl SG4 DC 2.5V pin 40 - - 0.7 V Defect Output Voltage H Vdfcth $863,SG3 2.520V+0.04Vp-p, f=1Khz,sine pin 41 4.3 - - V Output Voltage L Vdfcth $863,SG3 2.520V+0.04Vp-p, f=1Khz,sine pin 41 - - 0.7 V Focus Loop Mute Fmute SG2 2.5V+0.1Vp-p,1KHz,sine pin 48 -100 0 100 mV Tracking Loop Mute Tmute SG2 2.5V+0.1Vp-p,1KHz,sine pin 50 -100 0 120 mV Interruption Imute SG2 2.5V+0.1Vp-p,1KHz,sine pin 50 -100 0 120 mV Defect Bottom Voltage Fdfct1 SG3 2.520 V+0.04Vp-p, 1KHz,sine pin 41 - 670 1000 Hz Defect Max Freq. Voltage Fdfct2 SG3 2.520V+0.04Vp-p, 2KHz,sine pin 41 2.0 4.7 - KHz Defect Minimum Input Voltage Vdfct1 SG 3 2.510V+0.020Vp-p, 1KHz,sine pin 41 - 0.3 0.5 V M/M-97-P006 ELECTRONICS 1997. 10 .17 14 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Test Conditions Output Min Typ Max Unit Defect Maximum Input Voltage Vdfct2 SG32.535V+0.070Vp-p, 1KHz,sine pin 41 1.8 - - V EFM Duty Voltage 1 Defm1 SG4 2.5V+0.75Vp-p, 750KHz,sine pin 32 -50 0 50 mV EFM Duty Voltage 2 Defm2 SG42.75V+0.75Vp-p, 750KHz,sine pin 32 0 50 100 mV EFM Minimum input Voltage Vefm1 SG4 2.5V+0.12Vp-p, 750KHz,sine pin 33 - - 0.12 V EFM Maximum input Voltage Vefm2 SG4 2.5V+1.8Vp-p,750KHz,sine pin 33 1.8 - - V EFM Maximum Operating Frequency Fefm SG4 2.5V+0.75Vp-p,4MHz pin 33 4 - - MHz FZC Threshold Voltage Vfzc DC 2.5V+38mV,100mV pin 31 39 69 100 mV ATSC Threshold Voltage 1 Vatsc1 $10,SG2 DC 2.5V-6mV,-45mV pin 31 -67 -32 -7 mV ATSC Threshold Voltage 2 Vatsc2 SG2 DC 2.5V+6mV,+45mV pin 33 7 32 67 mV TZC Threshold Voltage Vtzc $20,SG2 DC 2.5V-20mV,+20mV pin 31 -30 0 30 mV SSTOP Threshold Voltage Vsstop $30,SG2 DC 2.5V-71mV,-30mV pin 31 -100 -50 -30 mV VtGW $840+$830 SG2 2.5V 2.9V 5mV DC pin 30 200 250 300 mV VTGW2 $848+$830 SG2 2.5V 5mV DC sweep pin 30 100 150 200 mV VTBW $844+$810 SG2 2.555V ~ 2.475V 5mV DC sweep pin 31 -25 15 55 mV VTBW2 $844+$810 SG2 2.555V ~ 2.470V 5mV DC sweep pin 31 -25 15 55 mV Vreg Threshold Voltage Vreg - pin 21 3.2 3.4 3.6 V Center Voltage VCVO 2.5V Reference pin 71 -100 0 100 mV VREF Current Drive Voltage 1 VCVO1 2.5V Reference pin 71 -100 0 100 mV VREF Current Drive Voltage 2 VCVO2 2.5V Reference pin 71 -100 0 100 mV Post CH1 Freq. Characteristic Fpos1 SG1 2.5V+1Vp-p,40KHz,sine pin 13 -4.5 -3.0 -1.5 dB Post CH2 Freq. Characteristic Fpos2 SG1 2.5V+1Vp-p,40KHz,sine pin 12 -4.5 -3.0 -1.5 dB Post CH1 Mute Mute1 Mute=5V SG1 2.5V+1Vp-p,1KHz,sine pin13 - - -35 dB Post CH2 Mute Mute2 Mute=5V SG1 2.5V+1Vp-p,1KHz,sine pin 12 - - -35 dB Focus Loop DC Gain Gf $08,SG2 DC 2.6V,2.4V average pin 48 19.0 21.5 24.0 dB Focus Off Offset Vosf1 $00 pin 48 -100 0 100 mV Focus On Offset Vofs2 $08,DC 2.5V pn 48 0 250 500 mV Focus Auto Offset Vaof $842,WDCK,after100ms pin 48 -65 0 65 mV Tracking gain window voltage Tracking gain window range Tracking balance window voltage Tracking balance window range M/M-97-P006 1997. 10. 17 10 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Focus Output Voltage H Vfoh1 Focus Output Voltage L Test Conditions Output Min Typ Max Unit $08,DC 3.0V pin 48 4.40 - - V Vfol1 $08,DC 2.0V pin 48 - - 0.60 V Focus Output Drive Voltage H Vfoh2 $08,DC 3.0V pin 48 3.68 - - V Focus Output Drive Voltage L Vfol2 $08,DC 2.0V pin 48 - - 1.32 V Focus Oscillation Voltage Vosc $08,DC2.5V pin 48 0 100 200 mV Focus Feed Through Gff Gain Difference at Servo on and off pin 48 - - -35 dB Focus AC Gain 1 Gfa1 $08, SG2 2.5V+0.1Vp-p,1.2KHz,sine pin 48 19.0 23.0 27.0 dB Focus AC Phase 1 Pfa1 $08, SG2 2.5V+0.1Vp-p,1.2KHz,sine pin 48 40 65 90 deg Focus AC Gain 2 Gfa2 $08, SG2 2.5V+0.1Vp-p,2.7KHz,sine pin 48 14.0 18.5 23.0 dB Focus AC Phase 2 Pfa2 $08, SG2 2.5V+0.1Vp-p,2.7KHz,sine pin 48 40 65 90 deg Focus Search Voltage1 Vfs1 $30+$02 pin 48 -0.64 -0.50 -0.36 V Focus Search Voltage2 Vfs2 $30+$03 pin 48 0.36 0.50 0.64 V Focus Loop Total Gain Gftg Focus PD gain + Focus loop DC gain pin 48 49.5 51.5 53.5 dB Tracking DC Gain Gto $25 SG2 DC 2.3V,2.7V average gain pin 50 13.5 15.5 17.5 dB Tracking Off Offset Vost1 $20 pin 50 -100 0 100 mV Tracking On Offset Vost2 SG2 DC 2.5V,$25 pin 50 -100 0 120 mV Tracking Oscillation Voltage Vosa1 $25,SG2 DC2.5V pin 50 0 100 200 mV Tracking gain boost for ATSC Gatsc 2.5V+0.1Vp-p,1KHz,sine pin 50 17.5 20.5 23.5 dB Tracking gain boost on LOCK (L) Glock 2.5V+0.1Vp-p,1KHz,sine pin 50 17.5 20.5 23.5 dB Tracking Output Voltage H Vth1 $25,SG2 DC 1.0V pin 50 4.48 - - V Tracking Output Voltage L Vtl1 $25SG2 ,DC 4.0V pin 50 - - 0.52 V Tracking Output Drive Voltage H Vth2 $25,SG2 DC2.0V pin 50 3.68 - - V Tracking Output Drive Voltage L Vtl2 $25, SG2 DC3.0V pin 50 - - 1.32 V Tracking Jump Voltage 1 Vtj1 $2C pin 50 -0.64 -0.5 -0.36 V Tracking Jump Voltage 2 Vtj2 $28 pin 50 0.36 0.5 0.64 V Tracking Feed Through Gtf Gain Difference at Tracking servo on and off pin 50 - - -39 dB Tracking AC Gain 1 Gta1 $10,$25,SG2 2.5V+0.1Vp-p, 1.2KHz,sine pin 50 9.0 12.5 16.0 dB M/M-97-P006 1997. 10. 17 11 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Tracking AC Phase 1 Pta1 Tracking AC Gain 2 Test Conditions Output Min Typ Max Unit $10,$25,SG2 2.5V+0.1Vp-p, 1.2KHz,sine pin 50 -140 -115 -90 deg Gta2 $10,$25,SG2 2.5V+0.1Vp-p, 2.7KHz,sine pin 50 17.5 21.5 25.5 dB Tracking AC Phase 2 Pta2 $10,$25,SG2 2.5V+0.1Vp-p, 2.7KHz,sine pin 50 -195 -150 -100 deg Tracking Loop Gain Gtrt tracking Amp F gain+ servo DC gain - 18.5 20.5 22.5 dB Sled DC Gain Gsl SG2 DC 2.6V,2.4V pin 43 20.5 22.5 24.5 dB Sled Feed Through Gslf Gain Difference at sled servo on and off SG2 2.5V+0.1Vp-p,1.2KHz,sine pin 43 - - -34 dB Sled Output Voltage H Vslh1 $25,SG2 DC 2.9V pin 43 4.48 - - V Sled Output Voltage L Vsll1 $25,SG2 DC 2.1V pin 43 - - 0.52 V Sled Output Drive Voltage H Vslh2 $25,SG2 DC 2.9V pin 43 3.68 - - V Sled Output Drive Voltage L Vsll2 $25,SG2 DC 2.1V pin 43 - - 1.32 V Sled Forward Kick Voltage Vsk1 $22 pin 43 0.38 0.60 0.75 V Sled Reverse Kick Voltage Vsk2 $23 pin 43 -0.75 -0.6 -0.38 V Spindle Normal Speed Gain Gsp $F0 SG1 DC 2.6V,2.4V, average gain pin 46 14.0 16.5 19.0 dB Spindle Double Speed Gain Gsp2 $F3 SG1 DC 2.6V,2.4V, average gain pin 46 19.0 23.0 27.0 dB Spindle Output Voltage H Gsph1 $F0, SG1 DC 3.5V pin 46 4.48 - - V Spindle Output Voltage L Gspl1 $F0, SG1 DC 1.5V pin 46 - - 0.52 V Spindle Output Drive Voltage H Gsph2 $F0,SG1 DC 3.5V pin 46 3.68 - - V Spindle Output Drive Voltage L Gspl2 $F0,SG1 DC 1.5V pin 46 - - 1.32 V Spindle AC Gain Gspa $F0,SG1 2.5V+0.2Vp-p, 2KHz,sine pin 46 -7.0 -3.5 0 dB Spindle AC Phase Pspa $F0,SG1 2.5V+0.2Vp-p, 2KHz,sine pin 46 -120 -90 -60 deg M/M-97-P006 1997. 10. 17 12 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Test Conditions Output Min Typ Max Unit FOCUS output voltage H Vfh1l pin 48 2.88 - - V FOCUS output voltage L Vfl1l pin 48 - - 0.68 V FOCUS SEARCH voltage 1 Vfs1l pin 48 -0.64 -0.50 -0.36 V FOCUS SEARCH voltage 2 Vfs2l pin 48 0.36 0.50 0.64 V Vost21 pin 50 -100 0 +120 mV TRACKING output voltage H Vth1l pin 50 2.88 - - V TRACKING output voltage L Vtl1l pin 50 - - 0.68 V TRACKING jump voltage 1 Vtj1l pin 50 -0.64 -0.50 -0.36 V TRACKING jump voltage 2 Vtj2l pin 50 0.36 0.50 0.64 V SLED output voltage H Vslh1l pin 43 2.88 - - V SLED output voltage L Vsll1l pin 43 - - 0.68 V SLED forward kick voltage Vsk1l pin 43 0.38 0.60 0.75 V SLED reverse kick voltage Vsk2l pin 43 -0.75 -0.60 -0.38 V SPINDLE output voltage H Vsph1l pin 46 2.88 - - V SPINDLE output voltage L Vspl1l pin 46 - - 0.68 V RF amp OFFSET voltage Vrfol pin 74 -80 0 +80 mV Tracking error offset Vteol pin 54 -50 0 +50 mV TRACKING on OFFSET VDD, DVDD, VCC = +3.4V Low Voltage Test for Servo Part & RF part : the test method is the same as 5V test RF amp output voltage H Vrfpp1l pin 74 2.8 - - V RF amp output voltage L Vrfpp2l pin 74 - - 0.6 V FOCUS error output voltage H Vfepp1l pin 59 2.8 - - V FOCUS error output voltage L Vfepp2l pin 59 - - 0.6 V Tracking error output voltage Vtepp1l pin 54 2.2 - - V Tracking error output voltage Vtepp2l pin 54 - - 1.2 V APC output voltage 1L Vapc1l pin 70 - - 1.2 V APC output voltage 2L Vapc2l pin 70 2.5 - - V APC output voltage 3L Vapc3l pin 70 2.5 - - V APC output voltage 4L Vapc4l pin 70 - - 1.2 V APC output voltage 5L Vapc5l pin 70 - - 1.1 V APC output voltage 6L Vapc6l pin 70 2.7 - - V FOK threshold voltage Vfoktl pin 40 -420 -360 -300 V pin 13 1.1 1.3 - Vrms Post Filter Output Voltage max. 1 Vpom1 SG1 2.5V+3.2Vp-p,1KHz, within THD 1% M/M-97-P006 ELECTRONICS 1997. 10 .17 14 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Post Filter Output Voltage max. 2 Vpom2 Total Harmonic Distoration 1 Output Min Typ Max Unit SG1 2.5V+3.2Vp-p,1KHz, within THD 1% pin 12 1.1 1.3 - Vrms THD11 SG1 f=100Hz,0dBm pin 13 - 0.01 0.05 % Total Harmonic Distoration 1 THD12 SG1 f=1KHz,0dBm pin 13 - 0.01 0.05 % Total Harmonic Distoration 1 THD13 SG1 f=10KHz,0dBm pin 13 - 0.05 0.1 % Total Harmonic Distoration 1 THD14 SG1 f=16KHz,0dBm pin 13 - 0.1 0.2 % Total Harmonic Distoration 1 THD15 SG1 f=20KHz,0dBm pin 13 - 0.1 0.2 % Total Harmonic Distoration 2 THD21 SG1 f=100Hz,0dBm Pin 12 - 0.01 0.05 % Total Harmonic Distoration 2 THD22 SG1 f=1KHz,0dBm Pin 12 - 0.01 0.05 % Total Harmonic Distoration 2 THD23 SG1 f=10KHz,0dBm Pin 12 - 0.05 0.1 % Total Harmonic Distoration 2 THD24 SG1 f=16KHz,0dBm Pin 12 - 0.1 0.2 % Total Harmonic Distoration 2 THD25 SG1 f=20KHz,0dBm Pin 12 - 0.1 0.2 % Frequency Characteristics 1 fv11 SG1 f=100Hz,0dBm pin 13 -0.1 0 0.1 dB Frequency Characteristics 1 fv12 SG1 f=1KHz,0dBm pin 13 -0.25 0 +0.25 dB Frequency Characteristics 1 fv13 SG1 f=10KHz,0dBm pin 13 -0.5 0 0.5 dB Frequency Characteristics 1 fv14 SG1 f=16KHz,0dBm pin 13 -1.0 0 1.0 dB Frequency Characteristics 1 fv15 SG1 f=20KHz,0dBm pin 13 -1.5 0 1.5 dB Frequency Characteristics 2 fv21 SG1 f=100Hz,0dBm Pin 12 -0.1 0 0.1 dB Frequency Characteristics 2 fv22 SG1 f=1KHz,0dBm Pin 12 -0.25 0 +0.25 dB Frequency Characteristics 2 fv23 SG1 f=10KHz,0dBm Pin 12 -0.5 0 0.5 dB Frequency Characteristics 2 fv24 SG1 f=16KHz,0dBm Pin 12 -1.0 0 1.0 dB Frequency Characteristics 2 fv25 SG1 f=20KHz,0dBm Pin 12 -1.5 0 1.5 dB Crosstalk 1 CT11 SG1 100Hz,0dBm,ratio on Ch2 pin 13 70 80 - dB Crosstalk 1 CT12 SG1 1KHz,0dBm,ratio on Ch2 pin 13 65 75 - dB Crosstalk 1 CT13 SG1 10KHz,0dBm,ratio on Ch2 pin 13 60 65 - dB Crosstalk 2 CT21 SG1 100Hz,0dBm,ratio on Ch1 pin 12 70 80 - dB Crosstalk 2 CT22 SG1 1KHz,0dBm,ratio on Ch1 pin 12 65 75 - dB Crosstalk 2 CT23 SG1 10KHz,0dBm,ratio on Ch1 pin 12 60 65 - dB Output Min Typ Max Unit Characteristic Symbol Test Conditions Test Conditions Signal to Noise Ratio 1 S/N 1 DC 2.5V 0dbm,ratio on Noise pin 13 73 80 - dB Signal to Noise Ratio 2 S/N 2 DC 2.5V 0dbm,ratio on Noise pin 12 73 80 - dB CB Gain Difference Ch1 and Ch2 - -0.1 0 +0.1 dB Channel Balance M/M-97-P006 1997. 10. 17 14 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 3. Electrical Characteristics (Continued) (Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V ) Characteristic Symbol Post filter output voltage mix.1L Output Min Typ Max Unit Vpom1L pin 13 0.5 0.55 - Vrms Post filter output voltage mix. 2L Vpom2L pin 12 0.5 0.55 - Vrms Total harmonic distortion 1L THD11L pin 13 - 0.01 0.05 % Total harmonic distortion 1L THD12L pin 13 - 0.01 0.05 % Total harmonic distortion 1L THD13L pin 13 - 0.05 0.1 % Total harmonic distortion 1L THD14L pin 13 - 0.1 0.2 % Total harmonic distortion 1L THD15L pin 13 - 0.1 0.2 % Total harmonic distortion 2L THD21L pin 12 - 0.01 0.05 % Total harmonic distortion 2L THD22L pin 12 - 0.01 0.05 % Total harmonic distortion 2L THD23L pin 12 - 0.05 0.1 % Total harmonic distortion 2L THD24L pin 12 - 0.1 0.2 % Total harmonic distortion 2L THD25L pin 12 - 0.1 0.2 % Frequency Characteristics 1L fv11L pin 13 -0.1 0 0.1 dB Frequency Characteristics 1L fv12L pin 13 -0.25 0 +0.25 dB Frequency Characteristics 1L fv13L pin 13 -0.5 0 0.5 dB Frequency Characteristics 1L fv14L pin 13 -1.0 0 1.0 dB Frequency Characteristics 1L fv15L pin 13 -1.5 0 1.5 dB Frequency Characteristics 2L fv21L pin 12 -0.1 0 0.1 dB Frequency Characteristics 2L fv22L pin 12 -0.25 0 +0.25 dB Frequency Characteristics 2L fv23L pin 12 -0.5 0 0.5 dB Frequency Characteristics 2L fv24L pin 12 -1.0 0 1.0 dB Frequency Characteristics 2L fv25L pin 12 -1.5 0 1.5 dB Cross talk 1L CT11L pin 13 67 80 - dB Cross talk 1L CT12L pin 13 62 75 - dB Cross talk 1L CT13L pin 13 57 65 - dB Cross talk 2L CT21L pin 12 67 80 - dB Cross talk 2L CT22L pin 12 62 75 - dB Cross talk 2L CT23L pin 12 57 65 - dB Signal to noise ratio 1L S/N1L pin 13 67 80 - dB Signal to noise ratio 2L S/N2L pin 12 67 80 - dB CBL - -0.1 0 +0.1 dB Channel balance L Test Conditions VDD, DVDD, VCC VCCP= +3.4V Low voltage test for post filter. The test method is the same as 5V test except for input signal : SG1 1.7V + 1.55Vp-p Note1) The notation $ means hexa decimal of micom command Note2) Low voltage test items only refer to KB9223-L M/M-97-P006 1997. 10. 17 15 PRELIMINARY DC SG3 33UF GND(0V) AC 10K SW30 10K SW31 390K SW32 390K SW33 SW34 3K SW35 3K SW36 0.5K SW37 65 PD1 66 PD2 67 F 68 E 69 PD 70 LD + SG2 AC 1 2 1 2 SW17 1 SW16 SW18 2 1 2 SW15 SW13 72 VCC 74 RFO 76 EQO 78 EQC 80 GND 5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 4 8 3 7 2 6 1 + 3300PF 27K LPFT 330PF + 330PF 5.6K 5.6K + VSSP FE+ 10PF AC + FEO 27K KB9223 TE2 5.6K 5.6K 10PF + TE1 CH2I + SG_D12 RESET 38 VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN SG-D3 SG-D4 SG-D5 SG-D6 SG-D7 SG-D8 FOK 40 MLT 37 VECTOR_TEST_IN SW11 SW10 SW8 VECTOR_TEST_IN SW9 1000PF SG-D2 MCK 35 11K 0.01UF + MDATA 36 SMEF 25 FLB 26 FS3 27 FGD 28 LOCK 29 VECTOR_TEST_OUT TRCNT 30 ISTAT 31 VECTOR_TEST_OUT ASY 32 EFM 33 VSSA 34 MIRROR 39 SL+ VECTOR_TEST_IN SW19 SW20 0.25K DC + 13K 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 200K 13K RRC DC SG1 MUTEI SSTOP SMON SW7 + SW14 SLO SMDP VECTOR_TEST_IN WDCK SW6 71 VR 100K TEO GC1O 0.5K SW38 13K SL- SG-D1 73 RF- 60K VREG SW5 SPDLISET 240K 22K 100K 0.1UF SW3 2PF 0.25K TE- 4.7UF 0.01UF SW39 0.25K 5K 13K SPDLO 0.25K GC1I SWP2 ATSC CH1I 5.6K 10K 4.7UF 27K SW2 TZC CH1O 3.3UF CH2O 3.3UF 75 IRF SW22 VERTOR_TEST_IN SG-_D10 DVDD 10K SW-VC AC SW21 GC2I GC2O 5.6K VCC(5V) DC SW23 VERTOR_TEST_IN SG-_D11 TDFCT 0.001UF SW40 SW24 VCCP SW1 VC(2.5V) SG4 SW25 FE2 4.7UF 27K 77 RFI VERTOR_TEST_IN FE1 VDDA SWP1 SW41 100K 0.01UF SW26 FSET DCC1 + SW27 FDFCT DCC2 0.01PF 79 EI 96K FRSH SW44.7UF 1997. 10. 17 200K 0.01UF SW28 TG2 TGU 510K DVEE DCB 16 M/M-97-P006 SW29 FEBIAS MCP 1000PF 1uF SW42 3300PF RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L TEST CIRCUIT Figure 3. Test Circuit PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L FUNCTION DESCRIPTION 1.RF Amp Block 1.1 RF Amplifier The optical currents inputted through pins PD1(A+C) and PD2(B+D) are converted into voltages through I-V amp, and they are added to RF summing amp. The voltage, converted from the photo diode (A+B+C+D) signal, is outputted through RFO(pin74) and the eye pattern can be checked at this pin. 58K PD1 - 65 VA + 10K - RFO 74 I-V amp(1) + VC RF summing amp VC 58K PD2 - 66 VB RF- 10K 73 + I-V amp(2) VC Figure 4. RF amp circuit 1.2 Focus Error Amp The output of the focus error amp is the difference between I-V amp(1) output VA and RF I-V amp(2) output VB. The focus error bias voltage applied to the (+) of focus error amp can be changed by output voltage of D/A converter as shown in diagram, so that the offset of focus error amp can be adjusted automatically by controlling 5 bits counter switches. Focus error bias can be adjusted from the range of +100mV ~ -100mV by connecting the resistor on pin 63 (FEBIAS). 164K 32K VB > - FE1 59 32K VA > + sev-stopb 160K FEBIAS SW1 63 sev-stop <5 Bit Counter> 4K - 3K X1 X2 X4 X8 X16 + fcmpo + FEBIAS vc fe-stopb Figure 5. Focus error amp circuit note1> VA and VB refer to output signal of PD1 and PD2 I/V amp. note2> sev-stopb,sev-stop,fe-stopb and fcmpo are internal signals M/M-97-P006 1997. 10. 17 17 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 1.3 Tracking Error Amp The optical currents detected from the side photo diode (E and F) pf pick-up are inputted to the E and F pin and converted into voltage signals by E I-V and F I-V amp. The output of tracking error amp generates the difference between E I-V AMP and F I-V AMP voltage output. The E-F balance can be adjusted by modifying the gain of E I-V AMP, and the tracking gain can be adjusted automatically by controlling the peak voltage at pin TE2 by micom program. TE1 F 67 I-V AMP - 68 I-V AMP + TE2 54 55 53 LPFT Balance Window Comp 3.3K Gain Window Comp 1.5K 16K 7.5K 27K BAL < 4 : 0 > 13K 56K 110K 79 75K EI 220K E 13K - To ISTAT To ISTAT To TRCNT GAIN_UP/DOWN GAIN < 3 : 0 > Figure 6. Tracking error amp circuit 1.4 Focus OK Circuit The FOK is the output. The focus OK circuit generates a timing window to enable focus servo operation from focus search status. When the difference of the RFO (pin74)signal and DC coupled signal IRF(pin75) are above the predefined voltage the Focus OK circuit output (pin40) becomes active(High output). The predefined voltage is -0.39V 40K 40K RFO IRF 74 - 75 + 40K 57K FOK 40 90K + VC+0.625V Figure 7. Focus OK circuit M/M-97-P006 1997. 10. 17 18 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 1.5 Mirror Circuit IRF signal is amplified by the mirror amp, and the peak and bottom component of amplified signal are detected by peak and bottom hold circuit. The peak hold circuit covers traverse signal of up to 100KHz component and bottom hold circuit capable of covering the envelope frequency of disc rotation. The time constant for the mirror hold must be sufficiently larger than that of the traverse signal. 38K IRF 75 17K 2.5K - Peak and Bottom Hold + 19K 1.5K 1 MCP 39 MIRROR + 17K + 96K + - Figure 8. Mirror Circuit 1.6 EFM Comparator The EFM comparator converts a RF signal into a binary signal. Beacuse the asymmetry generated due to variations in disc manufacturing can not be eliminated by the AC coupling alone, this circuit uses to control reference voltage of EFM comparator for eliminating asymmetry. 40K RFI + 77 1 EFM 39 ASY 100K + 19K + 20K 100K 85K Figure 9. EFM Comparator & asymmetry circuit M/M-97-P006 1997. 10. 17 19 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 1.7 Defect Circuit The RFO signal bottom, after being inverted, is held with two time constants of long and short. The short time-constant bottom hold is done for a disc mirror defect more than 0.1msec, the long timeconstant bottom hold is done with the mirror level prior to the defect. By differentiating this with a capacitor coupling and shifting the level, both signals are compared to generate the mirror defect detection signal. DCC1 DCC2 5 4 75K RFO 75 37.5K - BOTTOM + HOLD 28K 75K - BOTTOM VC+0.6254V HOLD DFCT 41 43K SSTOP/DFCT + 2 DCB Figure 10. Defect Circuit 1.8 APC (Auto Power Control) Circuit The laser diode has large negative temperature characteristic in its optical output when driven with a constant current on laser diode. Therefore, the output on processing monitor photo diode, must be a controlled current for getting regular output power, thus the APC (Auto Power Control) circuit is composed. PN (From micom command) 150K + PD 69 43.5K 0.75K 70 - 150K LD 300K 150K 1.25V + 5.5K LDON (From micom command) Figure 11. APC Circuit M/M-97-P006 1997. 10. 17 20 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 1.9 AGC Stability Circuit The AGC block is the function used to maintain the constant level of RF peak to peak voltage. After the operation of RF envelop detection and comparing with reference voltage, RFO level is kept stable in 1Vpp, and inputted to EFM Slice. IRF VCA 75 EQUALIZE 78 EQC 76 EQO Figure 12. AGC block 1.10 Post Filter The adjustment of audio output gain and the integration of possible de-emphasis output are executed by this circuit. This block has amps of 2 channel for gain and filter setting and mute pin for audio signal muting. CH2I VCC 12 CH2O + GC2I 25K - 10 GC2O + + + GC1I 25K CH1I 15 GC1O + 13 CH1O - 19 MUTEI Figure 13. Post Filter circuit VCC 1.11 Center Voltage Generation Circuit The center voltage is generated by voltage divide using resistor . 30K 71 VR + Figure 14. Center Voltage Generation Circuit M/M-97-P006 1997. 10. 17 30K 21 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 2.Servo Block 2.1 Focus Servo Block When defect is "H"(the defect signal is detected), the focus servo loop is muting in case of focus phase compensation. At this time, the focus error signal is outputted through the low pass filter formed by connecting a capacitor(0.1uF) and a built-in 470KΩ resistor to the FDFCT pin(pin 60). Accordingly, the focus error output is held at the error value just before defect error during defect occurring. The peak frequency of focus loop phase compensation is at about 1.2KHz when the resistor connected to FSET pin(pin 6) is 510KΩ, and it is inversely proportional to the resistor connected to the FSET pin. While the focus search is operating, the FS4 switch is on and then the focus error signal is isolated, accordingly the focus search signal is outputted by FEO pin(pin 48). When the FS2 switch is on(focus on), the focus servo loop is on and the focus error signal from FE2 pin(pin 58) is outputted through the focus servo loop. 3.6K 60K VC - FZCI 48 + 20K 58 48K X4 92K Focus Phase Compensation 470K FDFCT FSCMPO - + FE2 + X3 X2 FEO X1 - 60 + 40K FS4B FS2B 130K FE- 47 DFCTI 10K 470K FGD 28 50K 40K PS 3.6K FS3 27 4 3 X1 0 0 X2 0 1 X3 1 0 X4 1 1 FS1 46K 580K + FS3 26 3 6 FLB FSET FRCH Figure 15. Focus servo block M/M-97-P006 1997. 10. 17 22 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 2.2 Tracking Servo Block During detection of defect, the tracking error signal is outputted through the tracking servo loop after passing the low pass filter formed by connecting a capacitor(0.1uF) and a built-in 470KΩ resistor to the TDFCT pin(pin57) in case of tracking phase compensation. The value of tracking gain up/down can be controlled by TGU and TG2 pin. The peak frequency of tracking loop phase compensation, the dynamic range and offset of opamp can be adjusted by changing the value of resistor connected to FSET pin same as focus loop. In case of unstable status of actuator after jumping, the ON/OFF of tracking loop is controlled by TM7 switch of break circuit. After 10-track jumping, servo circuit gets out of the liner range and actuator's tracking becomes occasionally unstable. Hence unnecessary jumping with many tracking error should be prevented. TE2 TM4 53 470K 680K 57 TDFCT 49 680K TG1 TE- TM3 TG1 DFCTI 10K 66PF TM1 TGU 110K 61 20K TG2 TRACKING PHASE COMPENSATION 10K 90K 50 TEO + 82K TM7 62 TG2 470K 6 FSET Figure 16. Tracking servo block M/M-97-P006 1997. 10. 17 23 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 2.3 Sled Servo Block The moving of pick-up is controlled by tracking servo output through a low pass filter. The sled kick voltage is outputted for track jump operation. 43 TM6 TM7 - 44 + 42 PS SLO SLSL+ 4 3 X1 0 0 X2 0 1 X3 1 0 X4 1 1 TM2 Figure 17. Sled servo block 2.4 Spindle Servo Block The 20KΩ resistor and 0.33uF capacitor form the 200Hz low pass filter, and the carrier component of spindle servo error signals is eliminated. In CLV-S mode, SMEF becomes "L" and pin 25 low pass filter fc lowers, strengthening the filter further. The characteristics of high frequency phase compensation in focus tracking servo and the characteristics of cut off frequency in CLV low pass filter are tested by FSET pin. SMON 24 22K 22K 220K 15K 220K SMDP 23 20K - + 220K 25 46 SPDLO 50K 220K 15K + 100K - Double speed 45 SPDL- 6 SMEF FSET Figure 18. Spindle servo block M/M-97-P006 1997. 10. 17 24 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 3.Digital Block 3.1 Description Digital block is transferred serial data by micom and 8-bit serial data is converted to parallel data by serial to parallel register. This data is decoded by latch signal. The status output of focus servo,tracking servo,and sled servo system,etc is determined by each data. The auto-sequence function process 2~4 micom command by one auto-sequence command. MDATA D0 D1 D2 D4 D3 D6 D5 D7 tsu twck twck tsn MCK MLT td twl Figure 19. CPU serial interface timing chart Table 4. CPU serial interface timing characteristics Item Symbol Min Typ Max Unit fck - - 1 MHz fwck 500 - - ns Hold Time tsu 500 - - ns Setup Time tn 500 - - ns Delay Time td 500 - - ns Latch Pulse Width twl 1000 - - ns Clock Frequency Clock Pulse Width M/M-97-P006 1997. 10. 17 25 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 3.2 Micom Command Set Table 5. Servo control command set Item Hexa Address Data ISTA D7 D6 D5 D4 D3 D2 D1 D0 TOUT Focus Control $0X 0 0 0 0 FS4 Focus On FS3 Gain Down FS2 Search On FS1 Search Up FZC Tracking Control $1X 0 0 0 1 Anti Shock Brake On TG2 Gain Set TG1 Gain Set A.S Tracking Mode $2X 0 0 1 0 Select $3X 0 0 1 1 PS4 Focus Search+2 PS3 Focus Search+2 PS2 Sled Kick+2 PS1 Sled Kick+1 STOP Auto Sequence $4X 0 1 0 0 AS3 AS2 AS1 AS0 / BUSY 0.18ms 0.09ms 0.045ms 0.022ms $5X 0 1 0 1 0.36ms 0.18ms 0.09ms 0.045ms 11.6ms 5.80ms 0.09ms 0.045ms 64 32 16 8 128 64 32 16 R A M Blind/ overflow S E T Break Kick $6X 0 1 1 0 2N jump Tracking Mode Sled Mode TZC Hi-Z $7X 0 1 1 1 Auto Adj. $8XX 1 0 0 0 Offset,Balance,Gain,APC Control - Speed $FX 1 1 1 1 $F0:Normal Speed, $F3:Double Speed - move (M) M/M-97-P006 1997. 10. 17 26 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 3.2.1 Focus Control($0X) This command consists of 8 bits data and expressed by two hexa $0X. D7 D6 D5 D4 D3 D2 D1 D0 ISTAT 0 0 0 0 FS4 FS3 FS2 FS1 FZC FS4,FS3,FS2,FS1:internal switch for focus control -Focus Search Operation(FS2,FS1) $02:FS2 switch become off and the value of servo output pin is as below. (10uA-5uA)*50k*(feedback Resistor/50k) $03:If FS1 switch is 1, the current supply is cut off and the discharge is performed. The waveform is as below and the time constant is determined by internal resistor 50K and external capacitor. 0V Figure 20. Waveform at pin 3 when FS1 is switched from 0 to 1 The waveform of servo output pin according to FS1 and FS2 switches is as below. $00 02 03 02 03 02 03 00 Figure 21. Focus search waveform at pin 48 by $02 and $03 FS4 is switch for on/off control of focus servo loop $00:Focus servo off $08:Focus servo on M/M-97-P006 1997. 10. 17 27 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 3.2.2 Tracking Control($1X) This command is used for tracking loop gain control, break circuit and anti-shock on/off control. D7 D6 D5 D4 D3 D2 D1 D0 ISTAT 0 0 0 1 Anti shock on/off Break circuit on/off TG2 TG1 Anti shock TG2 and TG1 are internal switch for tracking gain set. 3.2.3 Tracking mode($2X) This command is used for tracking and sled servo on/off and jump for searching track. D7 D6 D5 D4 0 0 1 0 D3 D2 Tracking control D1 D0 ISTA T Sled control TZC <Tracking control & Sled control> D3 D2 Tracking mode D1 D0 Sled mode 0 0 Tracking servo off 0 0 Sled servo off 0 1 servo on 0 1 servo on 1 0 Forward jump 1 0 Forward kick 1 1 Reverse jump 1 1 Reverse kick 3.2.4 Peak value set($3X) This command is used for the peak value setting of focus search and sled kick . D0,D1:Sled kick D2,D3:Focus search peak value 3.2.5 Auto Sequencer command($4X) This command is used for reducing control time and replacing several command by one auto- sequence command. •Auto sequencer mode is performed from the first falling edge of WDCK clock after the falling of the latch pulse. •Auto sequencer does not carry out tracking gain up,brake,anti-shock and focus gain down. •Micom checks ISTAT pin(/BUSY) and sends to $40 command to reset preceding auto sequencer status M/M-97-P006 1997. 10. 17 28 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L Table 6. Auto sequence command Hexa AS3 AS2 AS1 AS0 Remark Cancel $40 0 0 0 0 Reset Auto focus $47 0 1 1 1 - 1 Track jump $48 $49 1 1 0 0 0 0 0 1 Forward Reverse 10 Track jump $4A $4B 1 1 0 0 1 1 0 1 Forward Reverse 2N track jump $4C $4D 1 1 1 1 0 0 0 1 Forward Reverse M track move $4E $4F 1 1 1 1 1 1 0 1 Forward Reverse 3.2.6 RAM Set($5X~$7X) The value of RAM set is somewhat different to the actual count and the initial value is like below Table 7. RAM set table Item Initial value Blind $55 actual count value Set value +4~5 WDCK clock overflow, Brake Set value +3 WDCK clock Kick $67 Set value +5 WDCK clock 2N ,M Track jump $7E Set value +3 WDCK clock 4.Auto Adjustment Command This command is used for auto control of offset,balance,gain adjustment and reference voltage setting. . This command is also in control of on/off and sub type of laser diode and test or set mode. 4.1 Tracking balance ($800~$81F) Item Hexa Data(5bits) initial value ISTAT(pin31) TRCNT(pin30) Tracking balance $800~$81F D4~D0 $81F BAL TRCNT M/M-97-P006 1997. 10. 17 29 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 4.2 Tracking gain ($820~$83F) Item Hexa Data(5bits) initial value ISTAT(pin31) TRCNT(pin30) Tracking gain $820~$83F D4~D0 $820 GAIN TGL 4.3 Tracking balance & gain window level setting Item Hexa D3 D2 D1 D0 initial value window level setting $84X gain balance 0 0 $840 •The tracking balance and gain window level is set by D2,D3 data and the value has two kinds of window levels set 4.3.1 Tracking balance window level D2 data 0 1 Tracking balance window level -10~+15mV -20~+20mV 4.3.2 Tracking gain window level D3 data 0 1 Tracking gain window level 250~400mV 150~300mV 4.4 Focus loop offset adjustment start command($841,$842) This command is used for adjusting focus error bias and removing focus servo offset. This command is executed during laser diode off. Hexa command meaning $841 Focus error bias adjustment start command $842 Focus servo offset cancel adjustment start command 4.5 APC circuit operation and Interruption on/off setting condition($85X) This command is used for setting of laser diode on/off ,sub type(P_sub or N_sub) of laser diode and interruption countermeasure circuit on/off. Item Hexa D3 D2 APC & Interruption on/off condition $85X LD on/off 0 : On 1 : Off Sub-type 0:N_sub 1:P_sub D1 Interruption ON/OFF and time setting M/M-97-P006 1997. 10. 17 D0 initial value $858 30 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 4.5.1 Time setting for Interruption countermeasure circuit on/off D1 D0 Meaning 0 0 Countermeasure circuit on for all mirror signal 0 1 Countermeasure circuit on up to 20KHz mirror signal 1 0 Countermeasure circuit off 1 1 Countermeasure circuit on up to 10KHz mirror signal 4.6 Focus servo offset reset command and set mode command (86X) This command is used for set and release before focus servo loop offset adjustment and mode change. Item Hexa D3 D2 D1 D0 Set mode & focus servo offset reset command $86X 0:offset release 1:offset reset option (Pin41 output) 0:Defect 1:SSTOP 1 1 (note1) The set mode command is sent by micom right after tracking gain is tuned. (note2) The ISTAT pin is outputted the internal status of $00 ~ $7X command. 4.7 Direct command(DIRC) and focus bias reset command($87X) This command is used for direct 1 track jump on/off setting and focus bias adjustment set and release Item Hexa D3 D2 D1 D0 DIRC & focus bias reset $87X 0:DIRC On 1:DIRC Off 0:reset 1:reset release X X M/M-97-P006 1997. 10. 17 31 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 5.The Example of Adjustment Free Algorithm 5.1 Focus Error Bias & Servo Offset Cancel Adjustment Focus_RF_Offset Adjustment [Command:841] Increment Count 5bit Counter 17mV/Bit Tuning range : + 260mV ISTAT Check L--> H no Time Max 100msec yes Finish [RF CNT value Latch] Focus_Servo_Offset Adjustment [Command:842] Increment Count 4bit Counter 40mV/Bit tuning range : + 280mV ISTAT Check L--> H no Time Max 100msec yes Finish [Servo value Latch] Figure 22. Focus error bias & servo offset cancel adjustment flow chart M/M-97-P006 1997. 10. 17 32 PRELIMINARY RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L 5.2 Tracking Balance Adjustment Balance adjustment Range window setting + 20mv, + 15mv setting ISTAT Check L--> H YES Micom Balance 5Bit adjustment Command Up NO ISTAT Check L--> H $844 $800 ~ $81F YES NO Finish [RF CNT value Latch Figure 23. Tracking balance adjustment flow chart 5.3 Tracking Gain Adjustment Gain adjustment range setting Command ISTAT Check L--> H NO $848 5 Bit Gain adjustment Command $820 ~ $83F YES Gain adjustment finish TOC READ Figure 24. Tracking gain adjustment flow chart M/M-97-P006 1997. 10. 17 33 VC GNDVCC + A GND 104p VCC 100K 150K 102p 1K 222p 100K 39K to KA9258D + 391p 120K 120K 47K + 683p 103p 56K to KA9258D 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TZC KB9223 331p + 5.6K 331p 5.6K + TEO 5.6K FE+ VSSP 150p FEO 27K SL+ from deck to MOCOM from MOCOM from MOCOM from MOCOM from MOCOM 333p 103p from DSP to MOCOM to MOCOM to DSP MCK 35 VSSA 34 EFM 33 + 104p ASY 32 0.47uF + ISTAT 31 LOCK 29 TRCNT 30 FGD 28 FS3 27 FLB 26 SMEF 25 104p MDATA 36 MLT 37 100K RESET 38 MIRROR 39 FOK 40 8 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 2 FE2 SL- WDCK SLO 3.3uF to KA9258D RRC + ISET B C 65 PD1 68 E 67 F 66 PD2 22K D E F 69 PD 70 LD 71 VR 72 VCC 73 RF74 RFO 75 IRF 76 EQO 78 EQC 77 RFI 222p VDDA VCC 1K from pick-up 102 + 4pF 472p 103p 1uF 79 EI SSTOP SMON from DSP(SMON) VREG from DSP SMDP from DSP(SMDP) 1997. 10. 17 47K 15K 10uF SPDL180K 34 M/M-97-P006 0.47uF TE- GND (POST) MUTEI from MICOM 1 5.6K 152p 12K 333p ATSC CH1I 5.6K CH1O CH2 out 4.7uF TE2 CH2O CH1 out 150p 27K 152p GC1I 27K TE1 CH2I 5.6K GC1O 4.7uF from DSP(SMEF) 104p 333p 27K LPFT 4.7uF + 1M 0.47uF 104p DVDD from DAC CH1 8.2K to KA9258D SPDLO 103p TDFCT GC2I GC2O VCC(POST) 100uF 10K FE1 VCC from DSP(SMSD) 104p VCCP from DAC CH2 + 10K FSET 510K VCC to pick-up + 33uF FDFCT DCC1 22K TG2 103p RF AMP & SERVO SIGNAL PROCESSOR KB9223 / KB9223-L TGU DCC2 4.7uF FRSH 103p 33uF + DVEE DCB 80 GND 152p FEBIAS MCP + PRELIMINARY APPLICATION CIRCUIT Figure 25. Application circuit