SANYO LA9242M

Ordering number:ENN7097
Monolithic Linear IC
LA9242M
Analog Signal Processor (ASP)
for CD Players
Overview
Package Dimensions
The LA9242M is an analog signal processing and servo
control bipolar IC designed for use in compact disc players
; a compact disc player can be configured by combining
this IC with a CD-DSP such as the LC78922E and
LC78620E, with a small number of additional components
required. In addition, this IC allows CD-RW disk playback
due to the on-chip gain switching function.
unit:mm
3159A-QFP64E
[LA9242M]
48
0.8
17.2
14.0
33
14.0
Functions
64
17
1
16
0.8
0.35
0.15
3.0max
(2.7)
(1.0)
SANYO : QFP64E
0.1
I/V amplifier, RF amplifier (with AGC), SLC, APC, FE,
TE (with VCA and auto-balance function), focus servo amplifier (with offset cancellation function), spindle servo amplifier (with gain switching function), sled servo amplifier (with off function), focus detection (DRF, FZD), track
detection (HFL, TES), defect detection, and shock detection.
17.2
32
49
Features
• The following automatic adjustment functions are built
in.
• Focus offset auto cancel : FE (pin 20)
• Tracking offset auto cancel : TE (pin 7).
• EF balance auto adjustment.
• RF level AGC function.
• Tracking servo gain RF level following function.
• Focus search smoothing setting pin : FSC (pin 46)
• EF balance adjustment variable range setting pin : (pin
47)
• Focus search mode switching pin : (pin 55)
• Play disc (Normal, CD-RW) mode switching pin : (pin
38)
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
41902AS (KT) No.7097–1/20
LA9242M
Specifications
Maximum Ratings at Ta = 25˚C, Pins 22, 45=GND
Parameter
Maximum supply voltage
Allowable power dissipation
Symbol
VCC max
Conditions
Ratings
Unit
Pin 56, 64
7
Pd max
350
V
mW
Operating temperature
Topr
–25 to +75
˚C
Storage temperature
Tstg
–40 to +150
˚C
Operating Conditions at Pins 22, 45=GND
Parameter
Recommended supply voltage
Allowable operating supply voltage
Symbol
Conditions
Ratings
VCC
VCC op
Unit
5
V
3.2 to 5.5
V
Operating Supply Voltage at Limit of Operating Temperature at Pins 22, 45=GND
Parameter
Operating temperature
Allowable operating supply voltage
Symbol
Conditions
Ratings
Unit
Topr2
–10 to +75
˚C
VCC op2
3.0 to 5.5
V
Operating Characteristics at Ta=25°C, Pins 22, 45=GND, VCC (pins 56, 64)=5V
Parameter
Current drain
Symbol
Conditions
Ratings
min
typ
max
Unit
ICCO
VREF
VCC1 (pin 64)+VCC2 (pin 56)
24
34
44
mA
VR
2.3
2.5
2.7
V
CE-Vth
CEvth
CE
0.8
V
CL-Vth
CLvth
CL
0.8
V
DAT
0.8
Reference voltage
[Interface]
DAT-Vth
DATvth
Maximum CL frequency
CL max
V
500
kHz
[RF amplifier]
RFSM no signal voltage
RFSMo
RF amplifier (Normal)
RFSMgmin1
RF amplifier (CD-RW)
RFSMgmin2
FIN1, FIN2 : 1MΩ-input, PH1=4V, freq=200kHz,
RFSM, RW=H
FIN1, FIN2 : 1MΩ-input, PH1=4V, freq=200kHz,
RFSM, RW=L
1.35
1.60
1.85
V
–12.0
–10.5
–9.0
dB
0
1.5
3.0
dB
dB
[Focus amplifier]
FDO gain (Normal)
FDg1
FIN2 : 1MΩ-input, FDO, RW=H
3.5
5.0
6.5
FDO gain (CD-RW)
FDg2
FIN2 : 1MΩ-input, FDO, RW=L
15.5
17.0
18.5
dB
FDO offset (Normal)
FDost1
Difference from reference voltage, servo on, RW=H
–170
0
+170
mV
FDO offset (CD-RW)
FDost2
Difference from reference voltage, servo on, RW=L
–190
0
+190
mV
Off time offset (Normal)
FDofost1
Difference from reference voltage, servo off, RW=H
–40
0
+40
mV
Off time offset (CD-RW)
FDofost2
Difference from reference voltage, servo off, RW=L
–40
0
+40
mV
Offset adjustment step
FDstep
FE
19
mV
F search voltage H1
FSmax1
FDO, FSS=GND
0.8
V
F search voltage L1
FSmin1
FDO, FSS=GND
–0.8
V
F search voltage H2
FSmax2
FDO, FSS=VCC
0.8
V
F search voltage L2
FSmin2
FDO, FSS=VCC
0
V
[Tracking amplifier]
TE gain MAX (Normal)
TEgmax1
f=10kHz, E : 1MΩ-input, PH1=4V, RW=H
6.0
7.5
9.0
dB
TE gain MAX (CD-RW)
TEgmax2
f=10kHz, E : 1MΩ-input, PH1=4V, RW=L
18.0
19.5
21.0
dB
TE gain MIN (Normal)
TEgmin1
f=10kHz, E : 1MΩ-input, PH1=1V, RW=H
–0.5
+1.8
+4.0
dB
TE gain MIN (CD-RW)
TEgmin2
f=10kHz, E : 1MΩ-input, PH1=1V, RW=L
11.5
13.8
16.0
TE–3dB (Normal)
TEfc1
E : 1MΩ-input, RW=H
TE–3dB (CD-RW)
TEfc2
E : 1MΩ-input, RW=L
TO gain
TGL offset (Normal)
TOg
TH → TO gain, THLD mode
80
dB
kHz
80
kHz
4.0
6.0
8.0
dB
TGLost1
Servo on, TGL=H, TO, RW=H
–250
0
+250
mV
TGL offset (CD-RW)
TGLost2
Servo on, TGL=H, TO, RW=L
–450
0
+450
mV
TGH offset (Normal)
TGHost1
TGL=L, difference from TGL offset, TO, RW=H
–50
0
+50
mV
TGH offset (CD-RW)
TGHost2
TGL=L, difference from TGL offset, TO, RW=L
–50
0
+50
mV
THLD offset (Normal)
THLDost1
THLD mode, difference from TGL offset, TO, RW=H
–50
0
+50
mV
THLD offset (CD-RW)
THLDost2
THLD mode, difference from TGL offset, TO, RW=L
–50
0
+50
mV
Off 1 offset
OFF1ost
TOFF=H
–50
0
+50
mV
Off 2 offset
OFF2ost
TOFF2 off (IF)
–50
0
+50
mV
Continued on next page.
No.7097–2/20
LA9242M
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
[Tracking amplifier]
Offset adjustment step
TEstep
TE
70
mV
Balance range H
BAL-H
∆ Gain E/F input, TB=5V, TBC=open
3.5
dB
Balance range L
BAL-L
∆ Gain E/F input, TB=0V, TBC=open
–3.5
TOFF-VTH
TGL-VTH
dB
TOFFvth
1.0
2.5
3.0
V
TGLvth
1.0
2.5
3.0
V
[PH]
No signal voltage
PHo
Difference from RFSM
–0.85
–0.65
–0.45
V
BHo
Difference from RFSM
0.45
0.65
0.85
V
Difference from VR at RFSM
–0.4
–0.2
0
V
4.5
4.9
[BH]
No signal voltage
[DRF]
Detection voltage
DRFvth
Output voltage H
DRF-H
Output voltage L
DRF-L
0
V
0.5
V
[FZD]
Detection voltage 1
FZD1
FE, difference from VR
Detection voltage 2
FZD2
FE, difference from VR
0
+0.2
V
0
V
[HFL]
Detection voltage
HFLvth
Output voltage H
HFL-H
Output voltage L
HFL-L
Difference from VR at RFSM
–0.55
–0.4
4.5
4.9
–0.25
V
V
0
0.5
V
[TES]
Detection voltage LH
TES-LH
TESI, difference from VR
–0.15
–0.10
–0.05
V
Detection voltage HL
TES-HL
TESI, difference from VR
0.05
0.10
0.15
V
Output voltage H
TES-H
4.5
4.9
Output voltage L
TES-L
V
0
0.5
V
0.35
0.5
0.65
V
–0.65
–0.5
–0.35
V
[JP]
Output voltage H
JP-H
Output voltage L
JP-L
Difference from JP+=0V, JP–=0V at JP+=0V,
JP–=5V, TO
Difference from JP+=0V, JP–=0V at JP+=5V,
JP–=0V, TO
[Spindle amplifier]
Offset 12
SPD12ost
Difference from VR at SPD, 12cm mode
–40
0
+40
mV
Offset 8
SPD8ost
Difference from VR at SPD, 8cm mode
–40
0
+40
mV
Offset off
SPDof
Difference from VR at SPD, OFF mode
–30
0
+30
mV
0.75
1.0
1.25
V
–1.25
–1.0
–0.75
V
0.35
0.5
0.65
V
Output voltage H12
SPD-H12
Output voltage L12
SPD-L12
Output voltage H8
SPD-H8
Difference from offset–12, 12cm mode,
CV+=5V, CV–=0V
Difference from offset–12, 12cm mode,
CV+=0V, CV–=5V
Difference from offset–8, 8cm mode,
CV+=5V, CV–=0V
[Sled amplifier]
SLEQ offset
SLEQost
Offset SLD
SLDost
Difference from TO at SLEQ
SLEQ=VR, difference from VR
–30
0
+30
mV
–100
0
+100
Offset off
SLDof
mV
Off mode
–40
0
+40
Disc switching
mV
RWvth
RW
1.5
2.0
2.7
V
SLCo
SLC
2.25
2.5
2.75
V
[SLC]
No signal voltage
[Shock]
No signal voltage
SCIo
SCI, difference from VR
–40
0
+40
mV
Detection voltage H
SCIvthH
SCI, difference from VR
60
100
140
mV
Detection voltage L
SCIvthL
SCI, difference from VR
–140
–100
–60
mV
Detection voltage
DEFvth
Difference between LF2 voltage when RFSM=3.5V
and DEF is detected and LF2 voltage when
RFSM=3.5V
0.20
0.35
0.50
V
Output voltage H
DEF-H
4.5
4.9
Output voltage L
DEF-L
[DEF]
V
0
0.5
V
[APC]
Reference voltage
Off voltage
LDS
LDDoff
LDS voltage at which LDD=3V
160
190
220
mV
LDD
3.9
4.3
4.6
V
No.7097–3/20
LA9242M
Pin Functions
Pin No.
Symbol
Contents
1
FIN2
Pickup photodiode connection pin. Added to FIN1 pin to generate the RF signal, subtracted from FIN1 pin to generate
the FE signal.
2
FIN1
Pickup photodiode connection pin.
3
E
Pickup photodiode connection pin. Subtracted from pin F to generate the TE signal.
4
F
Pickup photodiode connection pin.
5
TB
TE signal DC component input pin.
6
TE–
Pin which connects the TE signal gain setting resistor between this pin and TE pin.
7
TE
TE signal output pin.
8
TESI
TES (Track Error Sense) comparator input pin. The TE signal is input through a bandpass filter.
9
SCI
Shock detection input pin.
10
TH
Tracking gain time constant setting pin.
11
TA
TA amplifier output pin.
12
TD–
Pin for configuring the tracking phase compensation constant between the TD and VR pins.
13
TD
Tracking phase compensation setting pin.
14
JP
Tracking jump signal (kick pulse) amplitude setting pin.
15
TO
Tracking control signal output pin.
16
FD
Focusing control signal output pin.
17
FD–
18
FA
Pin for configuring the focusing phase compensation constant between the FD and FA pins.
Pin for configuring the focusing phase compensation constant between the FD– and FA– pins.
19
FA–
Pin for configuring the focusing phase compensation constant between the FA and FE pins.
20
FE
FE signal output pin.
21
FE–
Pin which connects the FE signal gain setting resistor between this pin and FE pin.
22
AGND
Analog signal GND.
23
NC
24
SP
No connection
CV+ and CV– pins input signal single-end output.
25
SPG
SP–
12-cm spindle mode gain setting resistor connection pin.
26
27
SPD
Spindle control signal output pin.
28
SLEQ
Sled phase compensation constant connection pin.
29
SLD
SL–
Sled control signal output pin.
Input pin for sled movement signal from microcontroller.
32
SL+
JP–
33
JP+
Input pin for tracking jump signal from DSP.
34
TGL
Input pin for tracking gain control signal from DSP. Gain is low when TGL is high.
35
TOFF
Input pin for tracking off control signal from DSP. Tracking servo is off when TOFF is high.
36
TES
Output pin for TES signal to DSP.
37
HFL
The High Frequency Level is used to determine whether the main beam is positioned over a bit or over the mirrored
surface.
38
Input pin for gain setting, according to CD or RW disc. Gain is high (RW disc mode), when RW is low.
39
RW
CV–
40
CV+
Input pin for CLV error singal from DSP.
41
RF output pin.
42
RFSM
RFS–
43
SLC
Slice Level Control is an output pin that controls the data slice level used by the DSP for the RF waveform.
44
SLI
Input pin used by DSP for controlling the data slice level.
45
DGND
Digital system GND pin.
46
FSC
Focus search smoothing capacitor output pin.
47
TBC
Tracking Balance Control ; EF balance adjustment variable range setting pin.
48
NC
No connection
49
DEF
Disc defect detection output pin.
50
CLK
Reference clock input pin. 4.23MHz signal from the DSP is input.
51
CL
Microprocessor command clock input pin.
52
DAT
Microprocessor command data input pin.
53
CE
Microprocessor command chip enable input pin.
30
31
Spindle phase compensation constant connection pin, along with the SPD pin.
Input pin for sled movement signal from microcontroller.
Input pin for tracking jump signal from DSP.
Input pin for CLV error signal from DSP.
RF gain setting and EFM signal 3T compensation constant setting pin, along with the RFSM pin.
Continued on next page.
No.7097–4/20
LA9242M
Continued from preceding page.
Pin No.
Symbol
Contents
54
DRF
RF level detection output (Detect RF).
55
FSS
Focus Search Select ; focus search mode (± search/+search vs. the reference voltage) switching pin.
56
VCC2
Servo system and digital system VCC pin.
57
REFI
By-pass capacitor connection pin for reference voltage.
58
VR
Reference voltage output pin.
59
LF2
Disc detect detection time constant setting pin.
60
PH1
RF signal peak hold capacitor connection pin.
61
BH1
RF signal bottom hold capacitor connection pin.
62
LDD
APC circuit output pin.
63
LDS
APC circuit input pin.
64
VCC1
RF system VCC pin.
BH1
PH1
LF2
VR
REFI
62
61
60
59
58
57 56
DEF
LDD
63
FSS
DRF
CE
DAT
CL
CLK
LDS
64
APC
VCC2
VCC1
Block Diagram
55 54 53 52 51 50
49
REF
48 NC
RF DET
FIN2 1
FIN1 2
47 TBC
VCA
I/V
46 FSC
E 3
microcontrollers
INTERFACE
VCA
BAL
F 4
SLC
45 DGND
44 SLI
43 SLC
TB 5
TE— 6
TE 7
TESI 8
—
42 RFS
TE
41 RFSM
+
40 CV
—
39 CV
RF Amp
T.SERVO & T.LOGIC
SCI 9
38 RW
TH 10
37 HFL
36 TES
35 TOFF
34 TGL
+
33 JP
TA 11
TD— 12
F.SERVO & F.LOGIC
SPINDLE SERVO
SLED SERVO
TD 13
JP 14
TO 15
28
29
SPD
SLEQ
SLD
30 31 32
JP—
27
SL—
SL+
24 25 26
SPG
SP—
NC
AGND
20 21 22 23
FE
FE—
19
FA—
18
FA
FD—
17
SP
FD 16
No.7097–5/20
LA9242M
Test Circuit
62
61
59
58
DEF
CLK
CL
DAT
47µF
0.1µF
CE
DRF
VCC2
LF2
60
REFI 0.1µF
REF
0.01µF
PH1
BH1
LDD
VCC1
LDS
63
0.47µF
VR
+
0.33µF
64
10µF
+
FSS
+
0.1µF
+
47µF
VCC
57 56 55 54 53 52 51 50 49
48
FIN2
F2I
1MΩ 1MΩ
F2IAC
0.01µF
F1I
FIN1
1MΩ 1MΩ
F1IAC
0.01µF
EI
E
1MΩ 1MΩ
EIAC
FI
1MΩ 1MΩ
FIAC
0.01µF
TB
REF
0.01µF
47
2
46
3
44
4
20kΩ
TE
TESI
TESIAC
0.01µF
SCI
TH
REF
0.068µF
TA
68kΩ
TD–
43
5
42
8
10
11
12
SLC
100kΩ
SLII
100kΩ
RFS–
20kΩ
14
15
16
REF
20kΩ
SL–
100pF
SL+
JP–
30 31 32
SLD
SLEQ
REF
29
20kΩ
30kΩ
15kΩ SPD
27 28
SPG
SP–
50kΩ SP
20 21 22 23 24 25 26
NC
19
AGND
18
15kΩ
FE–
17
39kΩ
20kΩ FE
FD
13
FA–
TO
SLI
RFSM
9
FA
2kΩ
DGND
41 +
CV
40 –
CV
39
RW
38
HFL
37
TES
36
TOFF
35
TGL
34 +
JP
33
LA9242M
FD–
JP
REF
FSC
10kΩ
6
7
68kΩ
TD
TBC
100pF
100kΩ
TE–
REF
1
45
F
0.01µF
NC
SLI— SLI+
No.7097–6/20
LA9242M
Description of Operation
1. APC (auto laser power control)
This circuit controls the pickup laser power. The laser is turned on and off by commands from the microcontroller.
2. RF amplifier (eye pattern output)
The pickup photodiode output current (A+C) is input to FIN2 (pin 1), and (B+D) is input to FIN1 (pin 2). The
current that is input is converted to the voltage, passes through the AGC circuit, and is then output from the RFSM
amplifier output RFSM (pin 41). The internal AGC circuit has a variable range of ±3dB, and the time constant can
be changed through the external capacitor connected to PH1 (pin 60). In addition, this circuit also controls the
bottom level of the EFM signal (RFSM output), and the response can be changed through the external capacitor
connected to BH1 (pin 61). The center gain setting for the AGC variable range is set by the resistance between
RFSM (pin 41) and RFS– (pin 42) ; if necessary, this resistance is also used for 3T compensation for the EFM
signal. If RW disc is detected, input signal gain is set high by RW (pin 38) which accepts Low from the DSP.
3. SLC (slice level control)
The SLC sets the duty ratio for the EFM signal that is input to the DSP to 50%. The DC level determined by
integrating the EFMO signal output from the DSP to determine the duty factor.
4. Focus servo
The focus error signal is derived by detecting the difference between (A+C) and (B+D), which is (B+D) – (A+C),
and is then output from FE (pin 20). The focus error signal gain is set by the resistance between FE (pin 20) and
FE– (pin 21). If RW disc is detected, input signal gain is set high by RW (pin 38) which accepts Low from the DSP.
Offset cancellation is performed by the FE amplifier. “Offset cancellation” cancels the offset for the IC’s internal
IV amplifier, etc. Adjustment is initiated by the FOCUS-OFFSET ADJUST START command, and terminates after
about 30 ms. The FOCUS-OFFSET ADJUST OFF command is used to return to the state before offset
cancellation.The FA amplifier is the pickup phase compensation amplifier, and the equalizer curve is set by the
external capacitor and resistance. Furthermore, this amplifer has a mute function which is applied when VCC is
turned on, when the F-SERVO OFF command is sent, and during F-SEARCH. In order to turn the focus servo on,
send either the LASER ON command or the F-SERVO ON command.
The FD amplifier has a phase compensation circuit, a focus search signal composition function and is completed in
about 560 ms. Focus seach is initiated by the F-SEARCH command, and a ramp waveform is generated by the
internal clock. This waveform is used for focus detection (focus zero cross) with the focus error signal and then
turn the focus servo on. The ramp waveform amplitude is set by the resistance between FD (pin 16) and FD– (pin
17). FSC (pin 46) is for smoothing the focus search ramp waveforms, and a capacitor is connected between FSC
and REF. FSS (pin 55) is the focus search mode switching pin. If FSS is shorted with VCC, the “+ search” is set ; if
FSS is left open or is shorted with GND, the “± search” is set.
5. Tracking servo
The pickup photodiode output current is input to E (pin 3) and F (pin 4). The current that is input is converted to
the voltage, passes through the balance adjustment VCA circuit and then the VCA circuit that follows the gain in
the RFAGC circuit, and is then output from TE (pin 7). The tracking error gain is set by the resistance between TE–
(pin 6) and TE (pin 7). If RW disc is detected, input signal gain is set high by RW (pin 38) which accepts Low
from the DSP.
Offset cancellation is performed by the TE amplifier. Offset cancellation terminates after about 30 ms. The
TRACK-OFFSET ADJUST OFF command is used to return to the state before the offset.
The TH amplifier alters the servo response characteristics according to the THLD signal, etc., generated internally
after detection of the TGL signal from the DSP or the JP signal. When a defect is detected, the THLD mode goes
into effect internally. To avoid this, short DEF (pin 49) to L=GND. By inserting an external bandpass filter to
remove the shock component from the tracking error signal at SCI (pin 9), the gain is automatically boosted when
a defect is detected.
The TA output (pin 11) has a built-in resistance to allow configuration of a low-pass filter.
The TD amplifier performs servo loop phase compensation ; the characteristics are set by external CR. Furthermore, this amplifer has a mute function, which is applied when VCC is turned on or the TRACK-SERVO OFF
command is issued. The muting function is released by the TRACK-SERVO ON command.
The TOFF amplifier that is positioned immediately after TD (pin 13) functions to turn off the servo in response to
the TOFF signal from the DSP.
The TO amplifier has a JP pulse composition function. The JP pulse is set by JP (pin 14). (THLD detection is
performed internally.)
No.7097–7/20
LA9242M
6. Sled servo
The response characteristics are set by SLEQ (pin 28). The amplifier positioned after SLEQ (pin 28) has a mute
function that is applied when the SLED OFF command is issued. The sled is moved by inputting current to SL–
(pin 30) and SL+ (pin 31) ; specifically, the pins are connected to the microprocessor output ports via resistors, and
the movement gain is set by the resistance value of that resistor. It is important to note that if there is a deviation in
the resistance values for SL– (pin 30) and SL+ (pin 31), an offset will arise in the SLD output.
7. Spindle servo
This configures the servo circuit, which maintains the linear velocity of the disc at a constant speed, along with the
DSP. This circuit accepts signals from the DSP through CV– (pin 39) and CV+ (pin 40) and sets the equalizer
characteristics through SP (pin 24), SP– (pin26), and SPD (pin 27), which are output to SPD (pin 27). The 12-cm
mode amplifier gain is set by the resistor connected between SPG (pin 25) and the reference voltage. In 8-cm
mode, this amplifier serves as an internal buffer, and SPG (pin 25) is ignored. Note that the gain setting is made for
8-cm mode first, and then 12-cm mode. If SPG (pin 25) is left open, the gain is forcibly set for 8-cm mode, regardless of whether 8-cm or 12-cm mode is in effect.
8. TES and HFL (traverse signals)
When moving the pickup from the outer track to the inner track, the EF output from the pickup must be connected
so that the phase relationship of TES and HFL is as shown in the diagram below. For the TESI input, the TES
comparator has negative polarity and hysteresis of approximately ±100mV. An external bandpass filter is needed in
order to extract only the required signal from the TE signal.
3.0V
2.1V
1.5V
RFSM
HFL
TES
TE
9. DRF (luminous energy determination)
DRF goes high when the peak of the EFM signal (RFSM output) held by the PH1 (pin 60) capacitor exceeds
approximately 2.3V. The PH1 (pin 60) capacitor affects the DRF detection time constant and the RFAGC response
bidirectional setting. The DRF output is driven by a constant current (250µA).
DRF
3.0V
2.3V
1.5V
RFSM
FE
Pickup position
Focus
10. Focus determination
Focus is assumed to be obtained when the focus error signal S curve reaching REF +0.2V is detected, and the S
curve subsequently returns to REF.
REF+0.2V
Focus
No.7097–8/20
LA9242M
11. DEFECT
The mirrored surface level is maintained by the capacitor for LF2 (pin 59) ; when a drop in the EFM signal (RFSM
output) reaches 0.35V or more, a high signal is output to DEF (pin 49). If DEF (pin 49) goes high, the tracking
servo enters THLD mode. In order to prevent the tracking servo from entering THLD mode when a defect is
detected, prevent DEFECT from being output by either shorting DEF (pin 49) to GND, or shorting LF2 (pin 59) to
GND. The DEFECT output is driven by constant current (approximately 100µA).
EFM signal
(RFSM output)
LF2 (pin 59)
0.35V
DEF (pin 59)
12. Microcontroller interface
Because the Reset (Nothing) command initializes the LA9242M, it must be used carefully.
The LA9242M command acceptance (mode switching) timing is defined by the internal clock (4.23MHz divided to
130kHz) after the falling edge of CE (RWC) ; therefore, when commands are sent consecutively, CE must go low
for at least 10µs. The 4.23MHz clock is required for that reason. 2BYTE-COMMAND DETECT and 2BYTECOMMAND RESET are used only for the purpose of masking two-byte data.
All instructions can be input by setting CE high and sending commands synchronized with the CL clock from the
microcontroller to DAT (pin 52) in LSB first format. Note that the command is executed at the falling edge of CE.
Timing
CE(RWC)
CL(CQCK)
DAT(COIN)
LSB
MSB
* The DSP pin names are shown in parentheses.
13. Reset circuit
The power-on reset is released when VCC exceeds approximately 2.6V.
14. Pattern design notes
To prevent signal jump-in from CV+ (pin 40) to RFSM (pin 41), a shielding line is necessary in between.
15. VCC /REF/GND/NC
VCC1 (pin 64)
: RF system
VCC2 (pin 56)
: SERVO system, DIGITAL system
AGND (pin 22)
: RF system, SERVO system
DGND (pin 45)
: DIGITAL system
NC (pin 23, 48)
: No connection
VR (pin 58)
: Refered voltage
No.7097–9/20
LA9242M
Microcontroller Command List
MSB
Reset mode
Power-on mode
Command
LSB
DSP
00000000
RESET
00001000
FOCUS START
RESET (NOTHING)
FOCUS START #1
11110000
11111000
11111111
2BYTE-COMMAND DETECT
2BYTE-COMMAND DETECT
2BYTE-COMMAND RESET
2BYTE-COMMAND DETECT
2BYTE-COMMAND DETECT
2BYTE-COMMAND RESET
10010000
FOCUS-OFFSET ADJUST START
–
10010001
FOCUS-OFFSET ADJUST OFF
–
10010010
TRACK-OFFSET ADJUST START
–
10010011
TRACK-OFFSET ADJUST OFF
–
10010100
10010101
LASER ON
LASER OFF ; F-SERVO ON
–
–
10010110
LASER OFF ; F-SERVO OFF
–
10010111
SPINDLE 8CM
–
10011000
SPINDLE 12CM
–
10011001
SPINDLE OFF
–
10011010
SLED ON
–
10011011
SLED OFF
10011100
E/F BALANCE START
–
Non-adjusted
–
10011101
TRACK-SERVO OFF
–
10011110
TRACK-SERVO ON
–
Notes Concerning Microcontroller Program Creation
1. Commands
After sending the FOCUS START command and the E/F BALANCE START command, send 11111110 (FEH) in
order to clear the internal registers of the IC.
Reason : Although the above commands are executed at point ¡ in the timing chart below, the same commands will
be executed again at point ™ if there is subsequent input to CE as shown below.
Timing
1
2µs or more
2µs or more
2
10µs or more
CE
1µs or more
CL
1µs or more
DAT
LSB
MSB
0
0
0
1
0
0
0
0 : “FOCUS START” command
0
0
1
1
1
0
0
1 : “E/F BALANCE START” command
When sending the TRACK-OFFSET ADJUST START command or the FOCUS-OFFSET ADJUST START
command after either VCC ON (POWER ON RESET), RESET command, or a corresponding OFFSET ADJUST
OFF command, waiting time is necessary as listed below. (Only when a 4.2MHz clock is input.)
TRACK-OFFSET ADJUST START : 4ms or more
FOCUS-OFFSET ADJUST START : 4ms or more
2. E/F balance adjustment
E/F balance adjustments should be made in a bit region of the disc, not a mirrored region.
Since there is no track-kick for LA9242M, measures must be taken during EF balance adjustment to obtain a stable
TE signal. (By a sled movement signal from a microcontroller, for example.)
No.7097–10/20
LA9242M
Pin Internal Equivalent Circuit
Pin No.
Pin name
Internal equivalent circuit
1
1
2
FIN2
FIN1
(2)
60kΩ
2kΩ
190kΩ
VREF
100kΩ
3
4
E
F
3
(4)
100kΩ
5pF
10pF
5
6
17
21
26
28
44
TB
TE–
FD–
FE–
SP–
SLEQ
SLI
VREF
(6,17,21,
26,28,44)
5
VCC
16
27
43
FD
SP D
SLC
300Ω
(27,43)
16
300Ω
GND
VCC
8
8
36
TESI
TE S
1kΩ
36
200kΩ
GND
Continued on next page.
No.7097–11/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
9
VREF
VCC
9
34
2kΩ
50kΩ
SCI
TGL
2kΩ
50kΩ
50kΩ
34
VREF
GND
VCC
10
30kΩ
7
10
TE
TH
300Ω
33kΩ
300Ω
66kΩ
7
GND
VCC
11
11
12
TA
TD–
10kΩ
300Ω
12
300Ω
GND
VCC
13
10kΩ
VREF
300Ω
13
TD
10kΩ
VREF
300Ω
GND
Continued on next page.
No.7097–12/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
VCC
14
VREF
VREF
14
50kΩ
4kΩ
4kΩ
50kΩ
JP
VREF
GND
20kΩ
10kΩ
VCC
15
VREF
40kΩ
300Ω
15
TO
300Ω
10pF
GND
VCC
18
VREF
VREF
240kΩ
300Ω
15pF
300Ω
19
18
19
20
FA
FA–
FE
GND
40kΩ
20
VCC
300Ω
300Ω
GND
Continued on next page.
No.7097–13/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
80kΩ
24
SP
VCC
VREF
300Ω
25
SPG
300Ω
5pF
25
GND
50kΩ
29
VREF
50kΩ
29
30
31
VCC
VREF
10kΩ
300Ω
10kΩ
SLD
SL–
SL+
300Ω
GND
30
50kΩ
31
VREF
VCC
32
60kΩ
32
33
JP–
JP+
20kΩ
60kΩ
20kΩ
300Ω
33
300Ω
GND
VREF
35
35
TOFF
10kΩ
Continued on next page.
No.7097–14/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
(46,49,54)
37
37
46
49
54
VCC
HFL
FSC
DEF
DRF
1kΩ
GND
38
30kΩ
10kΩ
38
RW
10kΩ
GND
VREF
VCC
39
39
40
24
CV–
CV+
SP
10kΩ
60kΩ
300Ω
60kΩ
40
300Ω
10kΩ
80kΩ
GND
24
42
5kΩ
42
VREF
RFS–
VCC
VREF
VREF
10kΩ
1kΩ
47
TBC
47
GND
Continued on next page.
No.7097–15/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
50
VREF
50kΩ
50
CLK
10kΩ
10kΩ
VREF
(52,53)
51
51
52
53
CL
DAT
CE
VCC
50kΩ
60kΩ
GND
VCC
50kΩ
55
FSS
10kΩ
50kΩ
55
57
VCC
VCC
20kΩ
57
58
300Ω
REFI
VR
20kΩ
300Ω
GND
58
GND
59
50kΩ
VCC
50kΩ
59
LF2
GND
Continued on next page.
No.7097–16/20
LA9242M
Continued from preceding page.
Pin No.
Pin name
Internal equivalent circuit
41
VCC
20kΩ
VCC
5kΩ
VREF
10kΩ
400Ω
41
60
61
RFSM
PH1
B H1
GND
15kΩ
60
GND
61
62
62
VCC
2kΩ
LDD
180kΩ
GND
63
63
LDS
No.7097–17/20
REF
REF
F
DXX
5
4
3
2
P-OP
REF
FD
TO
JP
P-OP
2.2kΩ
TD
TD–
0.0033µF TA
0.22µF TH
16
15
14
13
12
11
10
TE–
6
9.1kΩ TE
7
0.033µF TESI
8
REF 330pF SCI 9
TB
E
DXX
DXX
DXX FIN1
DXX
1
AGND
0.01µF
DXX FIN2
0.22µF
2.2kΩ
560Ω 0.047µF
10kΩ
4.7kΩ 0.1µF 220kΩ
0.15µF 0.047µF
100kΩ
VCC
220kΩ 27kΩ
000kΩ
220µF
64
I/V
AGND
61
VCA
17
18
19
0.001µF
+
+
0.15µF 0.01µF
56
+
330Ω
0.47µF
27
P-OP
56
kΩ
100
pF
24 25 26
REF
+
28
RF Amp
SLC
49
+
29
30 31 32
SLED SERVO
55 54 53 52 51 50
SPINDLE SERVO
REF
AGND
+
DGND
microcontrollers
INTERFACE
REF
57
+
DGND
20 21 22 23
22kΩ 0.22µF 15kΩ 33kΩ 2.7kΩ
15kΩ
LF2 100µF
59 AGND 58
DGND
F.SERVO & F.LOGIC
RF DET
60
+
VCA
T.SERVO & T.LOGIC
BAL
TE
63 AGND 62
APC.ADJ
LDS LASER 10Ω
APC
DGND
D-VCC
BH1
+
0.01µF
47µF
0.001µF
LDD
0.33µF
FD–
VCC1
1µF
PH1
FA
0.022µF
VR 10µF
39kΩ AGND
0.0047µF NC
MONI
FA–
100µF
24kΩ FE
FE–
0.01µF
REFI
47µF
VCC2
47kΩ SP
55kΩ
SPG
SP–
+
15kΩ SPD
D-VCC
SLEQ
10µF
SLD
SLD– SLD+
P-OP
0.0033µF
JP
DGND
FSC
TBC
NC
4.7µF
+
10kΩ
REF
REF
22
kΩ
RFSM
41
CV+
40
CV–
39
RW
38
HFL
37
TES
36
TOFF
35
TGL
34
JP+
33
DGND
SLI
44
0.033µF
0.001µF
SLC
43
10pF
–
10kΩ
RFS
42
10kΩ
DGND
45
46
47
48
4pF
FSS
DRF
CE
DAT
CL
CLK
47µF 1.8kΩ
51
kΩ
DEF
SL–
470kΩ
+
470kΩ SL
JP–
0.01µF 330Ω
1
2
3
0.1µF
VDD
4
5
56kΩ
6
7
1.2kΩ
8
9
33kΩ
10
11
DGND
12
13
14
15
16
580Ω
DEFI
TAI
PDO
VVSS
ISET
VVDD
FR
VSS
EFMO
EFMIN
TEST2
CLV+
CLV–
V/P
HFL
TES
microcontrollers
JP
LC78622E
EPLG
SBSY
XVSS
XIN
XOUT
XVDD
MUTER
RVDD
RCHO
RVSS
LVSS
LCHO
LVDD
MUTEL
N.C.
TEST4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DGND
VDD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TOFF
TGL
JP+
JP–
PCK
FSEQ
20kΩ
100
pF
5.1kΩ
TEST1
CS
TEST5
4.2M
16M
TEST11
RES
CQCK
COIN
SQOUT
RWC
WRQ
FSX
SBCK
SFSY
PW
VDD
CONT1
CONT2
CONT3
CONT4
CONT5
EMPH
C2F
DOUT
TEST3
REF
47µF
10pF
10pF
VDD
DGND
100µF
+
0.1µF
DGND
48
47
46
45
44
43
42
41
40
39
38
37 DGND
36
+
35
34
33
0.1µF
R-VCC
LA9242M
Sample Application Circuit
No.7097–18/20
0.047µF
QFP-64E
LA9230M
No
Yes
Pin 46, 47, 48, 55
No
No
180mV : typ
Available for RW disc
180mV : typ
APC reference voltage
LCD voltage where LDD=3V
Approx. 100µA
No connection
Approx. 100µA
No
No
DRF current capacity
No
No
2.3V
No
No
2.3V
Built in
Built in
Vth for HFL detection
Track-kick signal output
(Track-kick during E/F balance
adjustment)
Focus search smoothing capacitor
pin : FSC
E/F balance variable range setting
pin : TBC
Focus search mode switch pin :
FSS
×2
×2
Yes
Regeneration speed
Yes
1.3Vp-p
Approx. 280ms
1.3Vp-p
Yes
1.8Vp-p
• RE level AGC function
RF waveform amplitude when
VCC=5V
RF waveform amplitude when
VCC min
• Tracking servo gain RF level
following function
Approx. 280ms
Yes
1.8Vp-p
Yes
• E/F balance auto adjustment
Focus search time
Yes
Adjustment position : FD
270ms
Adjustment position : TO
30ms
Adjustment position : FD
270ms
Adjustment position : TO
30ms
32mA
40mA
5.5V
3.6V : t=–25 to +75° C
• Focus offset adjustment
Maximum adjustment time
Tracking offset adjustment
Maximum adjustment time
Auto adjustment function
Current drain (When VCC=5V)
VCO circuit built in
5.5V
3.6V : t=–25 to +75° C
QFP-64E
Allowable operating supply voltage
VCCop max
VCCop min1
VCCop min2
LA9220M
Type
Package
No
Pin 47, 48, 55
180mV : typ
Approx. 100µA
2.3V
No
No
Yes
No output
×2
Approx. 1.1s
Yes
1.3Vp-p
Yes
1.8Vp-p
Yes
Adjustment position : FD
270ms
Adjustment position : TO
30ms
No
32mA
5.5V
3.6V : t=–25 to +75° C
QFP-64E
LA9231M
No
Pin 47, 48, 55
180mV : typ
Approx. 100µA
2.3V
No
No
Yes
No output
×4
Approx. 1.1s
Yes
1.3Vp-p
Yes
1.8Vp-p
Yes
Adjustment position : FD
270ms
Adjustment position : TO
30ms
No
32mA
5.5V
3.6V : t=–25 to +75° C
QFP-64E
LA9233M
No
Pin 48
180mV : typ
Approx. 250µA
2.1V
Yes
Yes
Yes
No output
×4
Approx. 560ms
Yes
1.2Vp-p : VCC=3.4V
Yes
1.8Vp-p
Yes
Adjustment position : FE
30ms
Adjustment position : TE
30ms
No
32mA
5.5V
3.6V : t=–25 to +75° C
3.4V : t=–5 to +75° C
QFP-64E
LA9240M
No
Pin 23, 48
190mV : typ
Approx. 250µA
2 .1 V
Yes
Yes
Yes
No output
×4
Approx. 560ms
Yes
0.9Vp-p : VCC=3.0V
Yes
1.5Vp-p
Yes
Adjustment position : FE
30ms
Adjustment position : TE
30ms
No
32mA
5.5V
3.2V : t=–25 to +75° C
3.0V : t=–10 to +75° C
QFP-64E
LA9241M
Yes
Pin 23, 48
190mV : typ
Approx. 250µA
2.1V
Yes
Yes
Yes
No output
× 4 (Normal)
Approx. 560ms
Yes
0.9Vp-p : VCC=3.0V
Yes
1.5Vp-p
Yes
Adjustment position : FE
30ms
Adjustment position : TE
30ms
No
34mA
5.5V
3.2V : t=–25 to +75° C
3.0V : t=–10 to +75° C
QFP-64E
LA9242M
LA9242M
Function Comparisons for CD-ASP
No.7097–19/20
LA9242M
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer's
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer's products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products(including technical data,services) described or
contained herein are controlled under any of applicable local export control laws and regulations,
such products must not be expor ted without obtaining the expor t license from the authorities
concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of April, 2002. Specifications and information herein are subject to
change without notice.
PS No.7097–20/20