HA12220F CD-ROM Drive Head Amplifier IC ADE-207-230 (Z) Target Specification 1st. Edition April 1997 Functions • RF amplifier (Built-in equalizer changing circuit) • Focus error amplifier (fc = 60kHz Typ) • Tracking error amplifier (Built-in cut-off frequency changing circuit fc = 30kHz, 60kHz, 100kHz, 200kHz Typ) • FOK detection circuit (Built-in Vth changing circuit) • Mirror detection circuit • Defect detection circuit • APC amplifier • RFAGC amplifier Features • Built-in variable resistors (+14 to –16% 2% steps) for adjusting tracking error EF balance • Built-in variable resistors (–8 to +8dB 4dB steps) for rough adjusting tracking gain • Built-in variable resistors (–8 to +8dB 4dB steps) for rough adjusting focus gain • Built-in focus offset insertion circuit (–0.7 to +0.7V in 0.1V steps) • RF amplifier frequency characteristics 30MHz (–3dB) in case of peaking off • High-speed access support (The mirror circuit internal time constant can be switched between normal, 4× and 8× modes.) • Support for CD-RW playback • Few external components • Available to set the stand-by mode • FP-28TB package HA12220F Block Diagram HD49250 10µ 27 RF1 + 28 26 VCC 1µ 25 BYPS 24 GND VCF 23 RFC + – 0.015µ 21 22 AGCF AGC Gain changing BIAS RF2 1 0.1µ + 0.1µ AGCO DFH DEFECT DFT 20 HD49250 VCB EQ – + RF3 2 MIRH 19 RFS – + RF4 3 0.033µ FOK + – FSA MIRR MIRR 18 HD49250 + – FE Gain=12dB Typ FA2 FVR2 + – GND GND – + FA FOK 17 FVR HD49250 Offset + – TR1 4 TR1 TVR + – + – TE TLPF BAL + – TA TVR2 IIL + – TR2 5 TR2 XLT 16 HD49250 TVR Gain=8dB Typ DATA 15 MD 6 HD49250 – + BUF Interface + – APC LD 7 TE 8 FE 9 HD49250 HD49250 Rev.1, Apr. 1997, page 2 of 20 CI 10 µ-COM ADC GND CO 11 VC 12 + µ-COM 100µ DAC CLK XRST 13 14 µ-COM HD49250 HA12220F Pin Description and Equivalent Circuit Pin No. Pin Name 1 RF2 Equivalent Circuit Function RF FE FSA amplifier input2 4k 28 12k 120k 160k 5p 1 12k 120k 160k 10p 2 12k 120k 160k 3 12k 120k 160k 600k 160k 160k 10p 2 RF3 RF FE FSA amplifier input3 3 RF4 RF FE FSA amplifier input4 28 RF1 RF FE FSA amplifier input1 4 TR1 TR1 amplifier input 4k 1.2p 80k 32k 40k 5 TR2 11.4k TR2 amplifier input 4k 1.2p 80k 32k 40k 6 MD 7 LD 11.4k APC amplifier input 4k APC amplifier output 1k 150k 8 TE Tracking error signal output 40k 9 FE Focus error signal output Rev.1, Apr. 1997, page 3 of 20 HA12220F Pin Description and Equivalent Circuit (cont) Pin No. Pin Name 10 CI 11 CO 12 VC Equivalent Circuit Function 2.5k 10k FSA amplifier output monitor Setting FOK reference voltage Reference voltage output 20k 13 XRST 14 CLK Serial data synchronous clock input 15 DATA Serial data input 16 XLT Serial data latch input 17 FOK 4k VCC Reset input FOK detection signal output 20k 18 MIRR VCC Mirror detection signal output 10k 19 MIRH Mirror envelope hold signal output 100k 20 DFT VCC 20k Rev.1, Apr. 1997, page 4 of 20 Defect detection signal output HA12220F Pin Description and Equivalent Circuit (cont) Pin No. Pin Name Equivalent Circuit Function 21 DFH Defect envelope hold signal output 22 AGCO AGC amplifier output 5k 23 AGCF 24 RFC 25 VCF 5k 100k 4k Capacitor connection for AGC 2k 4k Capacitor connection for AGC VCC 40k 4k Capacitor connection for reference voltage ripple filter 40k GND 26 VCC BYPS 20k 27 VCC — Capacitor connection for ripple filter VCC Rev.1, Apr. 1997, page 5 of 20 HA12220F Operation Control by Serial Data The IC’s internal switches can be operated by sending control data from the HD49250. The signal timing is shown in figure 1, and the control commands are listed in table 1 and 2. Pin 15 DATA 0 T1 1 2 3 4 5 6 7 T2 Pin 14 CLK T3 T4 Pin 16 XLT Item Symbol Min Typ Max Unit Clock frequency fCLK — — 520 kHz Clock pulse width T1, T2 0.96 — — µs Delay time T3 1 — — µs Latch pulse width T4 2 — — µs Figure 1 Timing Diagram for Serial Data Control Signals from the HD49250 are input at pins 14 to 16. Pin13 is connected to the microcomputer. A low input at the XRST pin resets the IC. Normally this pin should be kept high. The serial data from the HD49250 switches the following settings. 1. Tracking error EF balance 2. Focus offset 3. Tracking gain, Focus gain 4. FOK Vth 5. Mirror circuit, defect circuit normal speed / 4× speed / 8× speed mode 6. Tracking error cut-off frequency 7. APC amplifier ON/OFF 8. RF equalizer 9. Stand-by mode (cleared by setting XRST on) Rev.1, Apr. 1997, page 6 of 20 HA12220F XLT 16 HD49250 IIL DATA 15 HD49250 Interface XRST CLK 13 14 µ-COM HD49250 Figure 2 Serial Data Control Rev.1, Apr. 1997, page 7 of 20 HA12220F Table 1 Serial Data Control Command 1 DATA D3 D7D6D5 D4 Focus error gain CD-RW 0 0 0 CD-RW *1 Focus error offset 0 0 1 D4 1 0 Variable resistor BAL for tracking error EF balance 0 1 0 D4 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Note D2 D1 Focus error gain 0 D3 0 0 0 1 1 D2 0 1 1 0 1 D1 0 1 0 1 0 Gain (dB) 0 –4 –8 +7.9 +4.3 D3 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 D2 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 D1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Offset (V) +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 ±0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 BAL 336kΩ 344kΩ 352kΩ 360kΩ 368kΩ 376kΩ 384kΩ 392kΩ 400kΩ 408kΩ 416kΩ 424kΩ 432kΩ 440kΩ 448kΩ 456kΩ D0 Ratio –16% –14% –12% –10% –8% –6% –4% –2% ±0% +2% +4% +6% +8% +10% +12% +14% 0 0 Note: 1. Both tracking error and focus error gains are increased by 12dB. The RFAGC block gain is also increased by 12dB. Rev.1, Apr. 1997, page 8 of 20 HA12220F Table 2 Serial Data Control Command 2 Tracking error gain D7D6D5 D4 1 0 0 — DATA D3 1 0 1 Mirror Defect APC ON 1 1 0 FOK Vth Stand-by RFEQ 1 1 1 D1 Tracking error gain D3 0 0 0 1 1 Tracking error filter Note D2 D2 0 1 1 0 1 D1 0 1 0 1 0 0 Gain (dB) 0 –4 –8 +7.9 +4.3 0 Mirror, Defect *1 Mode D3 D2 Normal 0 0 Tracking error filter 4× 0 1 8× 1 1 D4 D1 1 1 30kHz 0 1 60kHz 1 0 100kHz 0 0 200kHz FOK Vth Vth D4 D3 –12dB 1 1 –6dB 0 1 0dB 0 0 Prohibit 1 0 SC4 SC3 D0 Stand-by ON APC ON SC2 SC1 0 Stand-by mode is cleared by setting XRST on. 0 *2 Note: 1. Switches the mirror circuit and the defect circuit internal time constants at the same time. Don’t use D3 = “1”, D2 = “0” mode. 2. The switch name surrouded by circle means that the switch turns on when the corresponding bit is “1”. This switch changes the value of the RF peaking capacitor. In case of peaking off all switches must be set off. Rev.1, Apr. 1997, page 9 of 20 HA12220F RF Amplifiers The output from PDIC is summed by RFS amplifier. Figure 4 shows the equivalent circuit for the EQ block in figure 3. The peaking characteristics can be changed with 4-bit data from the HD49250. On resistance of SC1 to SC4 are 600Ω Typ. 28 1 2 3 RF1 12k RF2 12k RF3 12k RF4 12k EQ – + to AGC RFS Figure 3 RFS Amplifier SC3 4p 8p 16p SC2 SC1 SC4 0.3p 1.58k 4k 4k Figure 4 RFS Amplifier Equalizer Equivalent Circuit The RFS amplifier output is input to the AGC amplifier internally in the IC. Pin 24 is used to connect the capacitor that sets cut-off frequency of high-pass filter between the RFS amplifier and the AGC amplifier. The cut-off frequency will typically be 80Hz with the external constants shown in figure 5. The RF signal is rectified by an internal resistor and an external capacitor connected to pin 23. The pins 28, 1, 2, and 3 expect an input level of about 0.1Vpp. The AGC amplifier output (pin 22) will have an amplitude of 1.2Vpp Typ. When CD-RW mode is set by 1-bit data from the HD49250, the AGC amplifier gain is increased by 12dB. This allows the IC to output a 1.2Vpp Typ amplitude even during CD-RW playback. 1µ 0.1µ + 24 23 RFC to HD49250 22 AGCF AGC Gain changing AGCO to DEFECT MIRR from RFS Figure 5 AGC Amplifier Rev.1, Apr. 1997, page 10 of 20 HA12220F FOK Detection Circuit This detector is a comparator that generates the FOK signal. FOK is one of the signals that activate the focus servo. The FSA amplifier (fc = 53kHz Typ) summes the output from the PDIC. When this output signal becomes lower than the reference voltage by Vth, pin 17 goes high. This Vth can be set by 2-bit data from the HD49250. Vth is set to 0.8V (0dB) after a reset. Using µ-com ADC & DAC the voltage of pin 11 had better be set the same voltage as the voltage of pin 10 before focus searching in order to reduce the effect of DC offset voltage at FSA amplifier output. BUF – + 5p CO 600k 28 1 2 3 RF1 120k RF2 120k RF3 120k RF4 120k – + 11 µ-COM DAC FOK + FOK 17 – FSA CI 10 µ-COM ADC Figure 6 FOK Detection APC This circuit is for the Psub laser diode. This circuit is turned on or off by 1-bit data from the HD49250. MD 6 – + APC 1k LD 7 Figure 7 APC Rev.1, Apr. 1997, page 11 of 20 HA12220F Focus Error Amplifiers The FE amplifier adds and subtracts the output from the PDIC. FVR2 is a variable resistor used to increase the gain by 12dB in CD-RW mode. This variable resistor is set by 1-bit data from the HD49250. FVR is a variable resistor that changes the focus error gain over the range –8 to +8dB in ±4dB steps. This variable resistor is set by 3-bit data from the HD49250. An offset of between –0.7 and 0.7V (in 0.1V steps) is inserted into the focus error signal. This is set by 4bit data from the HD49250. The FE output cut-off frequency (fc) is 60kHz Typ. 10p 28 1 2 3 RF1 160k RF2 160k RF3 160k – + RF4 160k 160k 10p + – FE Gain=12dB Typ FA2 + – FVR2 160k 160k FVR 10p Offset FA 9 FE Figure 8 Focus Error Amplifiers Defect Detection Circuit When a scratched disc is played, the EFM RF signal has the shape shown in figure 10 (a). The defect detection circuit detects the drop-out area of this signal. 0.015µ 21 DFH from AGC DEFECT DFT MIRH MIRR MIRR 20 HD49250 19 0.033µ 18 HD49250 Figure 9 Mirror Detection, Defect Detection (a) Pin 22 ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;; (b) Pin 20 Figure 10 Defect Detection Waveform Rev.1, Apr. 1997, page 12 of 20 HA12220F Mirror Detection Circuit (MIRR) As the pick-up travels across tracks, the EFM RF signal varies as in figure 11 (a). The mirror detection circuit detects the mirror region from this signal. The external capacitor on pin 19 integrates the track-crossing frequency component. The internal time constant of the mirror detection circuit can be set for normal, 4×, or 8× speed by 2-bit data from the HD49250, to raise the trackable range of track-crossing frequencies. The defect circuit internal time constant is also switched at the same time. ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; (a) Pin 22 (b) Pin 18 Figure 11 Mirror Detection Waveform Tracking Error Amplifiers The sub-beam output of PDIC is passed through a resistor and input at pins 4 and 5. External resistances of pins 4 and 5 should be set according to the pick-up so that the traverse signal at pin 8 is about 2Vpp Typ. After a reset, the initial value of the feedback resistance BAL of TR1 amplifier is 400kΩ, the same as the feedback resistance of TR2 amplifier. BAL has a variable resistance value that is changed by 4-bit data from the HD49250. The variability range here is from –16 to +14% in 2% steps. This resistance can be varied to adjust the EF balance of the tracking error. TE amplifier generates the tracking error signal. TVR is a resistor that changes the tracking gain from –8 to +8dB in 4dB steps. This is set by 3-bit data from the HD49250. TVR2 is a variable resistor used to increase the gain by 12dB in CD-RW mode. This variable resistor is set by 1-bit data from the HD49250. TLPF switches the tracking error cut-off frequency. The TE output cut-off frequency is set to either 30, 60, 100, or 200kHz (Typ) by 2-bit data from the HD49250. TR1 4 + TR1 – TVR BAL TR2 5 1.2p + TR2 – TVR + – + – TE TLPF + – TA TVR2 Gain=8dB Typ 400k 8 TE 1.2p Figure 12 Tracking Error Amplifiers Rev.1, Apr. 1997, page 13 of 20 HA12220F Bias, Reference Voltage Pin 26 is for a bypass capacitor to eliminate noise from the IC’s internal bias circuits. Connect a capacitor to pin 25 to remove the ripple component from the reference voltage. The IC’s internal reference voltage is connected internally. 10µ 0.1µ + 27 26 VCC 25 BYPS GND VCF 40k 40k BIAS + – VCB 12 Figure 13 Bias, Reference Voltage Rev.1, Apr. 1997, page 14 of 20 HA12220F Absolute Maximum Rating (Ta=25°C) Item Symbol Rating Unit Power supply voltage VCC 6 V Power dissipation PT 400 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Note: Recommended operating power supply voltage : 5V ± 0.5V Rev.1, Apr. 1997, page 15 of 20 HA12220F Electrical Characteristics (Ta = 25°C, VCC = 5V) Item Symbol Min Typ Max Unit Test Conditions Application Terminal Quiescent current 1 ICC1 — 20 32 mA No signal 27 Quiescent current 2 ICC2 — 0.6 1.0 mA Stand-by mode VC 2.3 2.5 2.7 V I12 ≤ ±4mA Offset voltage * VFE – 100 0 100 mV Max output voltage H 1 VFEH1 4.2 4.5 — V S2, S3, S51, S9a V51 = 4V Max output voltage L 1 VFEL1 — 0.5 0.8 V S1, S28, S51, S9a V51 = 4V Max output voltage H 2 VFEH2 3.8 4.1 — V S2, S3, S51, S9b V51 = 4V Max output voltage L 2 VFEL2 — 0.9 1.2 V S1, S28, S51, S9b V51 = 4V Voltage gain 1 GVFE1 16.0 18.0 20.0 dB S2, S3, S50 V9/VIN50 Voltage gain 2 GVFE2 16.0 18.0 20.0 dB S1, S28, S50 V9/VIN50 Offset voltage *1 VTE –65 0 65 mV Max output voltage H 1 VTEH1 4.2 4.5 — V S4, S51, S8a V51 = 4V Max output voltage L 1 VTEL1 — 0.5 0.8 V S5, S51, S8a V51 = 4V Max output voltage H 2 VTEH2 3.8 4.1 — V S4, S51, S8b V51 = 4V Max output voltage L 2 VTEL2 — 0.9 1.2 V S5, S51, S8b V51 = 4V Voltage gain 1 GVTE1 5.0 8.0 11.0 dB S4, S50 V8/VIN50 Voltage gain 2 GVTE2 5.0 8.0 11.0 dB S5, S50 V8/VIN50 FOK Vth VFOK 110 160 210 mV S28, S51 when V17 ≥ 4V Min (V51 – V12) *2 “H” output voltage VFKH 4.7 — — V “L” output voltage VFKL — — 0.4 V Reference voltage Focus error amp. Tracking error amp. FOK Note: 1 9 8 1. All offset voltages are values referring to VC (pin 12) at reset. 2. V11 = setting the same voltage as the voltage of pin 10 at no signal. Rev.1, Apr. 1997, page 16 of 20 12 17 HA12220F Electrical Characteristics (Ta = 25°C, VCC = 5V) (cont) Item Application Terminal Symbol Min Typ Max Unit Test Conditions Max operation frequency FDH 2 — — kHz S28, S1, S2, S3, S50, S23 20 Min operation frequency FDL — — 1 kHz “H” output voltage VDFH 4.7 — — V “L” output voltage VDFL — — 0.4 V Max operation frequency FMIR 200 — — kHz S28, S1, S2, S3, S50, S23 8× mode 18 “H” output voltage VMIH 4.7 — — V “L” output voltage VMIL — — 0.4 V “H” input voltage VPH 4.0 — — V “L” input voltage VPL — — 1.0 V APC APC voltage VAPC 0.09 0.16 0.23 V RFAGC Output voltage 1 VAGC1 0.8 1.2 1.6 Vp-p S28, S50, f = 200kHz 0.4Vpp ± 6dB input Output voltage 2 VAGC2 0.8 1.2 1.6 Vp-p S1, S50, f = 200kHz 0.4Vpp ± 6dB input Output voltage 3 VAGC3 0.8 1.2 1.6 Vp-p S2, S50, f = 200kHz 0.4Vpp ± 6dB input Output voltage 4 VAGC4 0.8 1.2 1.6 Vp-p S3, S50, f = 200kHz 0.4Vpp ± 6dB input Frequency characteristics 1 FAGC1 — 30 — MHz S28, S50, S23 0.4Vpp input *3 Frequency characteristics 2 FAGC2 — 30 — MHz S1, S50, S23 0.4Vpp input *3 Frequency characteristics 3 FAGC3 — 30 — MHz S2, S50, S23 0.4Vpp input *3 Frequency characteristics 4 FAGC4 — 30 — MHz S3, S50, S23 0.4Vpp input *3 Defect Mirror CLK DATA XLT XRST Note: 13, 14, 15, 16 6 22 3. Setting V23 at the value of the pin 23 voltage when S28 is on, VIN50 = 0.4Vpp, and a 200kHz input. The frequency down –3dB from the output level for f = 200kHz. Rev.1, Apr. 1997, page 17 of 20 HA12220F Test Circuit V23 10k S23 S28 27 1µ + 28 1µ 0.1µ 26 GND 25 0.015µ S22 22 10k 21 S20 AGC Gain changing + – 1 23 24 BIAS S1 0.1µ + VCC DEFECT 20 VCB EQ – + S2 2 0.033µ 19 RFS – + S3 3 FOK + – FSA 10k S18 MIRR 18 S51 GND – + + – FE S50 FA2 FVR2 + – 0.1µ GND V51 FA S17 17 FVR VIN50 Offset S4 + – 4 390k TR1 TVR + – + – TE TLPF BAL + – TA TVR2 IIL S5 + – 5 TR2 TVR 16 390k 560 6 – + BUF APC 15 + – 2SB 561C 7 8 9 S8a S8b S9a S9b 20k 2k 20k 2k 10 GND 12 11 V11 + 13 14 10µ Serial data generator 2k Note: The symbol “●” of transfer switch shows OFF state. Rev.1, Apr. 1997, page 18 of 20 10k HA12220F Package Dimensions 14 21 28 7 6 0.575 2.25 ± 0.1 0.10 M 1.40 1.7 Max 0.13 0.17 ± 0.05 0.15 ± 0.04 1 0.32 ± 0.08 0.30 ± 0.06 0.09 0.13 +– 0.05 9.0 ± 0.2 9.0 ± 0.2 7.0 20 15 0.65 Unit: mm 1.0 0.575 0˚– 8˚ 0.95 ± 0.10 0.50 ± 0.10 Hitachi Code JEDEC Code EIAJ Code Weight FP-28TB — — 0.19 g Rev.1, Apr. 1997, page 19 of 20 HA12220F Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. Semiconductor & Integrated Circuits. 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(Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road, Hung-Kuo Building, Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon, Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://www.hitachi.com.hk Copyright Hitachi, Ltd., 2000. All rights reserved. Printed in Japan. Colophon 2.0 Rev.1, Apr. 1997, page 20 of 20