SAMSUNG KM611001

KM611001/L
CMOS SRAM
1M x 1Bit High-Speed CMOS SRAM
FEATURES
GENERAL DESCRIPTION
• Fast Access Time 20, 25, 35ns(Max.)
• Low Power Dissipation
Standby (TTL) : 40 mA(Max.)
(CMOS): 2 mA(Max.)
0.5 mA(Max.) - L-ver.
Operating KM611001/L -20 : 130 mA(Max.)
KM611001/L -25 : 110 mA(Max.)
KM611001/L -35 : 100 mA(Max.)
• Single 5.0V ± 10% Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Low Data Retention Voltage : 2V(Min.)- L-Ver Only
• Standard Pin Configuration
KM611001P/LP : 28-DIP-400
KM611001J/LJ : 28-SOJ-400A
The KM611001/L is a 1,048,576-bit high-speed Static
Random Access Memory organized as 1,048,576
words by 1 bit. The KM611001/L has separate input
and output lines for fast read and write access. The
device is fabricated using Samsung`s advanced
CMOS process and designed for high-speed circuit
technology. It is particularly well suited for use in highdensity high-speed system applications. The
KM611001/L is packaged in a 400 mil 28-pin plastic DIP
or SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION(TOP VIEW)
Pre-Charge Circuit
Clk Gen.
1
28
Vcc
A1
2
27
A19
A0
A2
3
26
A18
A1
A3
4
25
A17
A2
A4
5
24
A16
A5
6
23
A15
N.C
7
22
A14
A6
8
21
N.C
A7
A7
9
20
A13
A8
A8
10
19
A12
A9
A9
11
18
A11
DOUT
12
17
A10
/WE
13
16
DIN
Vss
14
15
/CS
A3
A5
A6
DIN
DOUT
Row Select
A0
Data
Cont.
MEMORY ARRAY
512 Rows
2048x1 Columns
I/O Circuit
Column Select
Clk
Gen.
SOJ/DIP
PIN DESCRIPTION
A4 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
Pin Name
A0-A19
/WE
/CS
DIN
DOUT
Vcc
Vss
N.C
/CS
/WE
1
Pin Function
Address Inputs
Write Enable
Chip Select
Data Input
Data Output
Power (+5V)
Ground
No Connection
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter
Symbol
Rating
Unit
VIN,OUT
- 0.5 to 7.0
V
Voltage on Vcc Supply Relative to Vss
VCC
- 0.5 to 7.0
V
Power Dissipation
PD
1.0
W
Tstg
- 65 to 150
°C
TA
0 to 70
°C
Voltage on Any Pin Relative to Vss
Storage Temperature
Operating Temperature
* Stresses greater than those listed under "Absolute Maximum Rating" may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS (TA= 0 to 70 °C )
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
4.5
5.0
5.5
V
Ground
VSS
0
0
0
V
Input Low Voltage
VIH
2.2
-
Vcc+0.5**
V
Input High Voltage
VIL
-0.5*
-
0.8
V
* VIL(Min) = -2.0 (Pulse Width ≤ 10ns) for I ≤ 20mA
** VIH(Max) = VCC+2.0V(Pulse width ≤ 10ns) for I ≤ 20mA
DC AND OPERATING CHARACTERISTICS
(TA= 0 to 70 °C, VCC=5.0V ± 10%, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Input Leakage Current
ILI
VIN=Vss to Vcc
-2
2
µA
Output Leakage Current
ILO
/CS=VIH or /OE=VIH or /WE=VIL
-2
2
µA
mA
VOUT=VSS to Vcc
Operating Current
Standby Current
ICC
Min. Cycle, 100% Duty
20ns
-
130
/CS=VIL, VIN=VIH or VIL,
25ns
-
110
IOUT=0mA
35ns
-
100
-
40
mA
mA
ISB
Min. Cycle, /CS=VIH
ISB1
f=0MHz, /CS ≥ Vcc-0.2V,
Normal
-
2
VIN ≥ Vcc -0.2V or VIN ≤ 0.2V
L-ver
-
0.5
-
0.4
V
2.4
-
V
Output Low Voltage
VOL
IOL=8mA
Output High Voltage
VOH
IOH = - 4mA
2
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
CAPACITANCE*(f=1MHz, TA =25 °C)
Item
Symbol
Test Condition
Min.
Max.
Unit
Input Capacitance
CIN
VIN=0V
-
7
pF
Input/Output Capacitance
CI/O
VI/O=0V
-
7
pF
* Note: Capacitance is sampled and not 100% tested.
AC CHARACTERISTICS
TEST CONDITIONS ON DATA RAM (TA= 0 to 70 °C, Vcc=5.0V ±
10%, unless otherwise specified.)
Parameter
Value
Input Pulse Level
0 to 3 V
Input Rise and Fall Time
3ns
Input and Output Timing Reference Levels
1.5V
Output Load
See below
Output Load (A)
Output Load (B)
for tHZ, tLZ, tWHZ, tOW, tOLZ, & tOHZ
+5.0V
+5.0V
480 Ω
480 Ω
DOUT
255 Ω
DOUT
255 Ω
30pF*
5pF*
* Including Scope and Jig Capacitance
3
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
READ CYCLE
KM611001/L-20
Parameter
KM611001/L -25
KM611001/L -35
Unit
Symbol
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
20
-
25
-
35
-
ns
Address Access Time
tAA
-
20
-
25
-
35
ns
Chip Select to Output
tCO
-
20
-
25
-
35
ns
Chip Enable to Low-Z Output
tLZ
5
-
5
-
5
-
ns
Chip Disable to High-Z Output
tHZ
0
12
0
15
0
15
ns
Output Hold from Address Change
tOH
3
-
5
-
5
-
ns
Chip Select to Power Up Time
tPU
0
-
0
-
0
-
ns
Chip Select to Power Down Time
tPD
-
20
-
25
-
35
ns
WRITE CYCLE
KM611001/L -20
Parameter
KM611001/L -25
KM611001/L -35
Unit
Symbol
Min
Max
Min
Max
Min
Max
Write Cycle Time
tWC
20
-
25
-
35
-
ns
Chip Select to End of Write
tCW
17
-
20
-
30
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Valid to End of Write
tAW
17
-
20
-
30
-
ns
Write Pulse Width(/OE High)
tWP
15
-
20
-
25
-
ns
Write Pulse Width(/OE Low)
tWP
20
-
25
-
35
-
ns
Write Recovery Time
tWR
2
-
3
-
3
-
ns
Write to Output High-Z
tWHZ
0
8
0
10
0
12
ns
Data to Write Time Overlap
tDW
12
-
15
-
20
-
ns
Data Hold from Write Time
tDH
0
-
0
-
0
-
ns
End Write to Output Low-Z
tOW
0
-
0
-
0
-
ns
4
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
TIMING DIAGRAMS
TIMING WAVE FORM OF READ CYCLE(1)
(Address Controlled)
(/CS=VIL, /WE=VIH)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVE FORM OF READ CYCLE(2)
(/WE=VIH)
tRC
Address
tAA
tCO
t HZ(3,4,5)
/CS
tOH
High-Z
Data Out
Vcc Supply
Icc
Current
Isb
t LZ (4,5)
Data Valid
tPU
tPD
50%
50%
NOTES (READ CYCLE)
1. /WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ is defined as the time at which the output achieve the open circuit condition and is not referenced to VOH or
VOL levels.
4. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from
device to device.
5. Transition is measured ± 200mV from steady state voltage with Load(B). This parameter is sampled and not 100%
tested.
6. Device is continuously selected with /CS=VIL
7. Address valid prior to coincident with /CS transition low.
5
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
TIMING WAVE FORM OF WRITE CYCLE(1)
(/WE=Controlled)
tRC
Address
t WR(5)
tAW
tCW(3)
/CS
t WP(2)
tAS(4)
/WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
tOW
High-Z
Data Out
TIMING WAVE FORM OF WRITE CYCLE(2)
(/CS=Controlled)
tRC
Address
t WR(5)
tAW
tCW(3)
/CS
t WP(2)
/WE
tDW
High-Z
tDH
Data Valid
Data In
tWHZ
High-Z
Data Out
6
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
NOTES (WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among
/CS going low and /WE going low; A write ends at the earliest transition among /CS going high and /WE going
high. tWP is measured from the beginning of write to the end of write.
3. tCW is measured from the later of /CS going low to end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE
going high.
6. If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance
state.
7. Dout is the read data of the new address.
FUNCTIONAL DESCRIPTION
/CS
/WE
H
X*
L
L
Mode
I/O Pin
Supply Current
Not Select
High-Z
ISB, ISB1
H
Read
DOUT
ICC
L
Write
DIN
ICC
*Note : X means Don't Care.
DATA RETENTION CHARACTERISTICS* (TA= 0
Parameter
Symbol
to 70 °C)
Test Condition
Vcc for Data Retention
VDR
/CS ≥ Vcc-0.2V
Data Retention Current
IDR
Vcc=3.0V, /CS ≥ Vcc-0.2V
Min.
Typ.
Max.
2.0
-
5.5
V
-
-
0.1
mA
Unit
VIN ≥ Vcc-0.2V or VIN ≤ 0.2V
Data Retention Set-Up Time
tSDR
See Data Retention
0
-
-
ns
Recovery Time
tRDR
Wave form(below)
5
-
-
ms
* L-version only
DATA RETENTION WAVE FORM
tSDR
Vcc
(/CS Controlled)
tRDR
Data Retention Mode
4.5V
2.2V
VDR
/CS
GND
/CS ≥ Vcc-0.2V
7
Rev 2.0
July-1996
KM611001/L
CMOS SRAM
PACKAGE DIMENSIONS
Unit: mm / Inch
28-SOJ-400A
9.40 ± 0.25
0.370 ± 0.010
10.16
0.400
11.18 ± 0.12
0.440 ± 0.005
#28
0.69 Min.
0.027
18.82 Max.
0.741
3.76 Max.
0.148
18.42 ± 0.12
0.725 ± 0.005
+0.10
0.43 -0.05
0.017 +0.004
-0.002
0.95
0.037
+ 0.10
0.20 - 0.05
0.008 + 0.004
- 0.002
#1
0.10 Max.
0.004 Max.
1.27
0.050
+0.10
0.71 -0.05
0.028 +0.004
-0.002
28-DIP-400
0° ~ 15°
10.16
0.400
9.09 ± 0.20
0.358 ± 0.008
#28
+0.10
0.25 -0.05
0.010 +0.004
-0.002
1.27
0.050
1.27 ± 0.10
0.050 ± 0.004
0.46 ± 0.10
0.018 ± 0.004
2.54
0.100
5.08
Max.
0.200
35.56 ± 0.20
1.400 ± 0.008
3.18 ± 0.30
0.125 ± 0.012
35.96 Max.
1.46
0.51 Min.
0.020
4.32 ± 0.20
0.170 ± 0.008
#1
*Note : Do not include mold protrusion
8
Rev 2.0
July-1996