KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER November. 1999. Ver. 0.1 Prepared by: Jae il Byeon [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 Specification Revision History Version 2 Content Date 0.0 Original Aug.1999 0.1 The contents of page 9, 10 and 13 have been modified Nov.1999 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 CONTENTS INTRODUCTION .................................................................................................... 4 FEATURES ............................................................................................................ 4 BLOCK DIAGRAM................................................................................................. 5 PIN ASSIGNMENTS ............................................................................................. 6 PIN DESCRIPTIONS.............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATION RATINGS........................................................... 8 DC CHARACTERISTICS ....................................................................................... 9 AC CHARACTERISTICS ..................................................................................... 10 AC TIMING DIAGRAM......................................................................................... 11 OPERATION DESCRIPTION............................................................................... 12 OPERATION METHOD ........................................................................................................ 12 OUTPUT PIN ........................................................................................................................ 12 VOLTAGE BIASING ............................................................................................................. 13 RECOMMENDED TIMING.................................................................................................... 14 3 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER INTRODUCTION The KS0657 is a TFT-LCD gate driver having 263 / 256 outputs. It can drive TFT panel gate ON voltage up to 38 V. It can operate within the logic voltage 2.7 to 5.5 V. FEATURES • 263 / 256 outputs • Maximum TFT panel gate ON voltage = 38 V • Bi - directional shift register • Logic supply voltage = 2.7 to 5.5 V • COF (Chip On Film) 4 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 BLOCK DIAGRAM VDD VLO VOFF SEL U/D CPV DI/O S/R 001 S/R 002 263 Shift Register S/R 262 S/R 263 DO/I Level Shifter OE VGG 263 Ouput Buffer VOFF G001 G002 G262 G263 Figure 1. Block Diagram 5 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER PIN ASSIGNMENTS G263 G262 VGG G261 VOFF G260 DMY1 DMY2 DMY3 DMY4 DOI VDD KS0657 (Top View) U/D VLO CPV OE CPV VLO SEL VDD DIO DMY4 DMY3 DMY2 DMY1 G004 VOFF G003 VGG G002 G001 Figure 2. Pin Assignments 6 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 PIN DESCRIPTIONS Symbol Pin Name I/O Description When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip’s start pulse input. The output pulse is generated I/O at the falling edge of the 263th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) DI/O DO/I Start pulse input/output U/D Shift direction control input I When U/D = H, DI/O → G001 →……→ G263 → DO/I When U/D = L, DO/I → G263 →……→ G001 → DI/O CPV Shift clock input I The shift register operates in synchronization with the rising edge of this input Output selection input I This input selects the number of available outputs When SEL = H, 263 output mode When SEL = L, 256 output mode(G129 - G135 are disabled) SEL OE Output enable input I This input controls the state of the driver outputs. When OE = H, the driver output is fixed to VOFF. When OE = L, the driver output is VGG or VOFF corresponding to the data. G001 to G263 Driver output O The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VOFF. VOFF Negative power supply I This input is logic and driver ground. Always, has negative potential. VLO Logic input low voltage I This input operates as the reference to the level conversion of the other input. The other logic input range: VDD - VLO VGG Driver positive power supply I 6 to 33 V The TFT gate ON voltage is VGG - VOFF. VDD Logic positive power supply I 2.7 to 5.5 V 7 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER ABSOLUTE MAXIMUM RATINGS (VOFF = 0 V) Table 1. Absolute Maximum Ratings Parameter Symbol Ratings Unit Logic positive power supply VDD - 0.3 to 21.0 V Driver positive power supply VGG - 0.3 to 42.0 V Logic input low voltage VLO - 0.3 to VDD + 0.3 V Input voltage VIN - 0.3 to VDD + 0.3 V Operation temperature Top - 20 to 75 °C Storage temperature Tstg - 55 to 150 °C CAUTIONS If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. ON: VLO → VDD → VOFF → Control Input → VGG OFF: VGG → Control Input → VOFF → VDD → VLO RECOMMENDED OPERATION RATINGS (VLO = 0 V) Table 2. Recommended Operation Ratings 8 Parameter Symbol Min. Typ. Max. Unit Logic positive power supply VDD 2.7 - 5.5 V Driver positive power supply VGG 6 - 33 V Negative power supply VOFF - 15 - -5 V Power supply voltage VGG - VOFF 21 - 38 V Operation frequency fCPV - - 100 kHz Output load CL - - 1000 pF 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 DC CHARACTERISTICS (VLO = 0V) Table 3. DC Characteristics (Ta = - 20 to 75 ° C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V) Parameter Symbol High input voltage VIH Low input voltage VIL High output voltage VOH Low output voltage Min. Max. Unit VLO + 0.9VX VDD V VOFF VLO + 0.1VX V IOH = - 40 µA VDD - 0.4 VDD V VOL IOL = 40 µA VOFF VOFF + 0.4 V ROH VOUT = VGG - 0.5 V, VGG = 38 V, VOFF = 0 V - 500 Ω G001 to G263 ROL VOUT = 0.5 V, VGG = 38 V, VOFF = 0 V - 500 Ω G001 to G263 High output current IGG Without output load - 400 µA VGG IDD VDD - VOFF = 3.3 V - 400 µA (1) Low output current VDD - VOFF = 19 V - 1000 µA (3) Input leak current ILK - -5 5 µA (1) LCD driver output ON resistance Condition VX = VDD - VLO Pin used (1) (2) NOTES: 1. DI/O, DO/I, CPV, OE, U/D, SEL used. 2. When U/D = H, DO/I used, and when U/D = L, DI/O used. 3. Input swing voltage = VDD to VDD - 3.3 V 9 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER AC CHARACTERISTICS (VLO = 0 V) Table 4. AC Characteristics (Ta = - 20 to 75 ° C, VGG - VOFF = 21 to 38 V, VLO - VOFF = 15 to 5 V, VDD - VLO = 2.7 to 5.5 V) Parameter Symbol Condition Min. Max. Clock period tCPV - 10 - Clock pulse width tCPVH, tCPVL Duty = 50 % 4 - Output enable input width twOE - 0.8 - Data setup time tsDI - 0.8 - Data hold time thDI - 0.8 - Output delay time (1) tpdDO CL = 30 pF - 0.8 Output delay time (2) tpdG - 0.8 Output delay time (3) tpdOE - 0.8 10 CL = 300 pF Unit µs DO/I (U/D=H) DI/O (U/D=L) G263 (U/D=H) G1 (U/D=L) G2 to G262 OE G1 (U/D=H) G263 (U/D=L) DI/O (U/D=H) DO/I (U/D=L) CPV 50 % tCPVH 50 % thDI 50 % 50 % tpdG 50 % tsDI tCPVL 50 % tpdOE 50 % tpdOE twOE 50 % 50 % 50 % tpdDO 50 % 50 % tCPV 50 % 50 % tpdDO 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 AC TIMING DIAGRAM Figure 3. AC Timing Diagram 11 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER OPERATION DESCRIPTION OPERATION METHOD The start pulse input, DI/O (when U/D is “H”) or DO/I (when U/D = “L”), is synchronized with the rising edge of CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G263) supplies VGG voltage or VOFF voltage to the TFT-LCD panel depending on the pulse of the shift register. The start pulse output, DO/I (when U/D is “H”) or DI/O (when U/D = “L”), is synchronized with the falling edge of CPV and the pulse of the last register (G1 or G263) is transferred to the next IC. The voltage level of the start pulse output is VDD with “H” data, VOFF with “L” data The relationship between U/D and shift data input / out pin is as follows: Table 5. The Relationship between U/D and the Start Pulse Input / Output Shift data U/D state Input Output 263 output “H” DI/O DO/I G1 → G2 → G3 → G4 → G5 →……→ G263 “L” DO/I DI/O G263 → G262 → G261 → G260 →……→ G1 256 output “H” DI/O DO/I G1 → G2 →……→ G128 → G136 →……→ G262 → G263 “L” DO/I DI/O G263 → G262 →……→ G136 → G128 →……→ G2 → G1 Mode Data transfer direction Output level OE = L OE = H Normal (VGG / VOFF) Disable (VOFF) OUTPUT PIN (G1 TO G263) If the data of the shift register to an output drive pin is “H”, the voltage level of the output is VGG and if the data is “L”, the level of the output is VOFF. But, when OE is “H”, the voltage level of the output is VOFF irrespective of the data of the shift register. 12 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 VOLTAGE BIASING The driver negative power supply, VOFF, can be any value between VLO - 5V and VLO - 15V. G1 to G263 VGG (31 V) Input signal Logic Output VDD (3.0V) VLO (0 V) VOFF (-7 V) Figure 4. Example of Voltage Biasing 13 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER RECOMMENDED TIMING - 263 Output mode (When SEL = "H") When U/D = "H" Input DI/O CPV OE G1 G2 G3 G4 VGG G263 VOFF VDD Output DO/I VOFF When U/D = "L" Input DO/I CPV OE G263 G262 G261 G260 VGG G1 VDD Output DI/O Figure 5. Recommended Timing 14 VOFF VOFF 263 / 256 CHANNEL TFT-LCD GATE DRIVER KS0657 - 256 Output mode (When SEL = "L") When U/D = "H" Input DI/O CPV OE G1 G2 G3 G4 G129 to G135 G263 VOFF VGG Output DO/I VOFF VDD VOFF When U/D = "L" Input DO/I CPV OE G263 G262 G261 G260 G135 to G129 G1 VOFF VGG Output DI/O VOFF VDD VOFF Figure 5. Recommended Timing (Continued) 15 KS0657 263 / 256 CHANNEL TFT-LCD GATE DRIVER NOTES 16