S6C0649 256 CHANNEL TFT-LCD GATE DRIVER November. 1999. Ver. 0.1 Prepared by: Jae il Byeon [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. S6C0649 256 CH. TFT-LCD GATE DRIVER S6C0649 Specification Revision History Version 2 Content Date 0.0 Original Aug.1999 0.1 The contents of page 9 and 10 have been modified Nov.1999 256 CH. TFT-LCD GATE DRIVER S6C0649 CONTENTS INTRODUCTION .................................................................................................... 4 FEATURES............................................................................................................. 4 BLOCK DIAGRAM ................................................................................................. 5 PIN ASSIGNMENTS ............................................................................................. 6 PIN DESCRIPTIONS.............................................................................................. 7 ABSOLUTE MAXIMUM RATINGS ........................................................................ 8 RECOMMENDED OPERATION RATINGS ........................................................... 8 DC CHARACTERISTICS ....................................................................................... 9 AC CHARACTERISTICS ..................................................................................... 10 AC TIMING DIAGRAM ......................................................................................... 11 OPERATION DESCRIPTION............................................................................... 12 OPERATION METHOD .........................................................................................................12 OUTPUT PIN.........................................................................................................................12 VOLTAGE BIASING ..............................................................................................................13 RECOMMENDED TIMING ....................................................................................................14 3 S6C0649 256 CH. TFT-LCD GATE DRIVER INTRODUCTION The S6C0649 is a TFT-LCD gate driver having 256 outputs. It can drive TFT panel gate ON voltage up to 40 V. It can operate within the logic voltage 2.7 to 5.5 V. FEATURES • 256 outputs • Maximum TFT panel gate ON voltage = 40 V • Bi - directional shift register • Logic supply voltage = 2.7 to 5.5 V • TCP available 4 256 CH. TFT-LCD GATE DRIVER S6C0649 BLOCK DIAGRAM VDD VLO VSS1 U/D CPV DI/O S/R S/R 001 002 256 Shift Register S/R S/R 255 256 DO/I OE1 Level Shifter OE2 OE3 VGG 256 Ouput Buffer VSS2 G001 G002 G255 G256 Figure 1. Block Diagram 5 S6C0649 256 CH. TFT-LCD GATE DRIVER PIN ASSIGNMENTS G256 G255 G254 G253 VGG VSS2 VSS1 VDD DO/I S6C0649 (Top View) OE3 OE2 OE1 CPV VLO U/D DI/O VLO VSS1 VSS2 VGG G004 G003 G002 G001 Figure 2. Pin Assignments 6 256 CH. TFT-LCD GATE DRIVER S6C0649 PIN DESCRIPTIONS Symbol Pin Name I/O Description When these inputs operate as the input, the start pulse data is read at the rising edge of shift clock, CPV. When these inputs operate as the output, the start pulse output is the next chip’s start pulse input. The output pulse is generated I/O at the falling edge of the 256th shift clock, CPV. When U/D = H, the shift register does right shifting operation. (Input = DI/O and output = DO/I) When U/D = L, the shift register does left shifting operation. (Input = DO/I and output = DI/O) DI/O DO/I Start pulse input/output U/D Shift direction control input I When U/D = H, DI/O → G001 →……→ G256 → DO/I When U/D = L, DO/I → G256 →……→ G001 → DI/O CPV Shift clock input I The shift register operates in synchronization with the rising edge of this input OE1 OE2 OE3 Output enable input I These inputs control the state of the driver outputs. When OE = H, the driver output is fixed to VSS2. When OE = L, the driver output is VGG or VSS2 corresponding to the data. G001 to G256 Driver output O The output signals change in synchronization with the rising edge of shift clock input, CPV. The amplitude of the driver output is VGG - VSS2. VSS2 Driver negative power supply I The input is internally connected to the logic ground, VSS1. The input operates as the TFT panel gate OFF voltage. VLO Logic input low voltage I Logic input range: VDD - VLO VGG Driver positive power supply I 6 to 35 V The TFT gate ON voltage is VGG - VSS2. VDD Logic positive power supply I 2.7 to 5.5 V VSS1 Logic negative power supply I The logic negative power supply, VSS1, is internally connected to the driver negative power supply, VSS2. 7 S6C0649 256 CH. TFT-LCD GATE DRIVER ABSOLUTE MAXIMUM RATINGS (VSS1 = VSS2 = 0 V) Table 1. Absolute Maximum Ratings Parameter Symbol Ratings Unit Logic positive power supply VDD - 0.3 to 21.0 V Driver positive power supply VGG - 0.3 to 45.0 V Logic input low voltage VLO - 0.3 to VDD + 0.3 V Input voltage VIN - 0.3 to VDD + 0.3 V Operation temperature Top - 20 to 75 °C Storage temperature Tstg - 55 to 150 °C CAUTIONS If the absolute maximum rating is exceeded momentarily, the quality of this product may be degraded. It is desirable to use this product within the range of the absolute maximum ratings. The power supplying order is as follows. ON: VLO → VDD → VSS1, VSS2 → Control Input → VGG OFF: VGG → Control Input → VSS1, VSS2 → VDD → VLO RECOMMENDED OPERATION RATINGS (VLO = 0 V) Table 2. Recommended Operation Ratings 8 Parameter Symbol Min. Typ. Max. Unit Logic positive power supply VDD 2.7 - 5.5 V Driver positive power supply VGG 6 - 35 V Logic negative power supply VSS1 - 15 - -5 V Driver negative power supply VSS2 - 15 - -5 V Power supply voltage VGG - VSS2 21 - 40 V Operation frequency fCPV - 100 200 kHz Output load CL - - 500 pF 256 CH. TFT-LCD GATE DRIVER S6C0649 DC CHARACTERISTICS (VLO = 0V) Table 3. DC Characteristics (Ta = - 20 to 75 °C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 5 V, VDD VLO = 2.7 to 5.5 V, fCPV=100KHz) Parameter Symbol High input voltage VIH Condition VX = VDD - VLO Min. Max. Unit VLO + 0.9VX VDD V VSS1 VLO + 0.1VX V Pin used (1) Low input voltage VIL High output voltage VOH IOH = - 40 µA VDD - 0.4 VDD V Low output voltage VOL IOL = 40 µA VSS1 VSS1 + 0.4 V ROH VOUT = VGG - 0.5 V, VGG = 40 V, VSS2 = 0 V - 500 Ω G001 to G256 ROL VOUT = 0.5 V, VGG = 40 V, VSS2 = 0 V - 500 Ω G001 to G256 High output current IGG Without output load - 400 µA VGG IDD VDD - VSS1 = 3.3 V - 400 µA (1) Low output current VDD - VSS1 = 19 V - 1000 µA (3) Input leak current ILK - -5 5 µA (1) LCD driver output ON resistance (2) NOTES: 1. DI/O, DO/I, CPV, OE1, OE2, OE3, U/D used. 2. When U/D = H, DO/I used, and when U/D = L, DI/O used. 3. Input swing voltage = VDD to VDD - 2.7 V 9 S6C0649 256 CH. TFT-LCD GATE DRIVER AC CHARACTERISTICS (VLO = 0 V) Table 4. AC Characteristics (Ta = - 20 to 75 °C, VGG - VSS2 = 21 to 40 V, VLO - VSS1 = 15 to 5 V, VDD VLO = 2.7 to 5.5 V, fCPV=100KHz) Parameter Symbol Condition Operation frequency fCPV - Clock pulse width tCPVH, tCPVL Duty = 50 % 2 - Output enable input width twOE - 1 - Data setup time tsDI - 800 - Data hold time thDI - 800 - Output delay time (1) tpdDO CL = 30 pF - 800 Output delay time (2) tpdG - 800 Output delay time (3) tpdOE - 800 10 CL = 300 pF Min. Max. Unit 200 kHz µs ns 256 CH. TFT-LCD GATE DRIVER S6C0649 AC TIMING DIAGRAM tpdDO 50% 50% tCPV 50% 50% tpdDO 50% twOE 50% 50% tpdOE 50% 50% tpdOE thDI 50% 50% tsDI 50% 50% tCPVL tpdG 50% DO/I (U/D=H) DI/O (U/D=L) G256 (U/D=H) G1 (U/D=L) G2 to G255 OE1~3 G1 (U/D=H) G256 (U/D=L) DI/O (U/D=H) DO/I (U/D=L) CPV tCPVH Figure 3. AC Timing Diagram 11 S6C0649 256 CH. TFT-LCD GATE DRIVER OPERATION DESCRIPTION OPERATION METHOD The start pulse input, DI/O (when U/D is “H”) or DO/I (when U/D = “L”), is synchronized with the rising edge of CPV and stored in the first shift register. While stored pulse is transferred to the next register at the next rising edge of CPV, a new pulse is stored simultaneously. Output pin (G1 to G256) supplies VGG voltage or VSS2 voltage to the TFT-LCD panel depending on the pulse of the shift register. The start pulse output, DO/I (when U/D is “H”) or DI/O (when U/D = “L”), is synchronized with the falling edge of CPV and the pulse of the last register (G1 or G256) is transferred to the next IC. The voltage level of the start pulse output is VDD with “H” data, VSS1 with “L” data The relationship between U/D and shift data inout pin is as follows: Table 5. The relationship between U/D and the start pulse input / output Start pulse input / output U/D Pin Data shift direction Input Output “H” (VDD) DI/O DO/I G1 → G2 → G3 → G4 → G5 →……→ G256 “L” (VSS1 - VLO) DO/I DI/O G256 → G255 → G254 → G253 →……→ G1 OUTPUT PIN (G1 TO G256) If the data of the shift register to an output drive pin is “H”, the voltage level of the output is VGG and if the data is “L”, the level of the output is VSS2. But, when OE is “H”, the voltage level of the output is VSS2 irrespective of the data of the shift register. Table 6. The voltage level of the output Condition Pin Control pin to LCD panel State G2, G5, G8, …… , G251, G254 G3, G6, G9, …… , G252, G255 OE1 G1, G4, G7, …… , G250, G253, G256 OE3 12 “H” OE3 OE2 Output level G1, G4, G7, …… , G250, G253, G256 OE1 OE2 Controlled output pin by OE signal “L” G2, G5, G8, …… , G251, G254 G3, G6, G9, …… , G252, G255 VSS2 Normal output (VGG or VSS2) 256 CH. TFT-LCD GATE DRIVER S6C0649 VOLTAGE BIASING The driver negative power supply, VSS2, can be any value between VLO - 5V and VLO - 15V. And VSS2 is internally connected to the logic negative power supply, VSS1. G1 to G256 VGG (33V) Input signal Logic Source Logic Output VDD (3V) VLO (0V) VSS1 = VSS2 (- 7V) Figure 4. Example of Voltage Biasing 13 S6C0649 256 CH. TFT-LCD GATE DRIVER RECOMMENDED TIMING When U/D = "H" Input DI/O CPV OE1 OE2 OE3 G1 G2 G3 G4 VGG G256 VSS2 VDD Output DO/I VSS1 When U/D = "L" Input DO/I CPV OE1 OE3 OE2 G256 G255 G254 G253 VGG G1 VDD Output DI/O Figure 5. Recommended Timing 14 VSS2 VSS1