MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 D D D D Gate Driver LSI for Active-Matrix LCD Liquid-Crystal Control Outputs: 256 Enables High-Voltage Operation: Liquid-Crystal Control Signal VL + 35 V (max) D D D Liquid-Crystal Control Signal’s Negative-Voltage Output Is Enabled by a Level-Shift Circuit On-Chip Bidirectional Shift Registers TCP (Tape Carrier Package) CMOS-LSI Structure description The MPT57605 is a gate driver LSI that drives an active-matrix LCD panel and implements a multi-pin configuration, low power consumption, and high voltage. Furthermore, the level-shift circuit enables positive and negative power supplies. Also, it is compatible with various SVGA/XGA panels. OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT251 OUT252 OUT253 OUT254 OUT255 OUT256 MPT57605 STV2 CPV OE1, OE2, OE3 VSS L/R VL VDD VCOM VEE STV1 NOTE A: This figure shows the copper foil side and does not describe the TAB outline or show the NC pins. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 block diagram L/R OE3 OE2 OE1 STV1 STV2 CPV VCOM VL VDD VSS VEE Level Shift 2 Shift Register Level Shift Circuits Output Circuits OUT1 Shift Register Level Shift Circuits Output Circuits OUT2 Shift Register Level Shift Circuits Output Circuits OUT3 Shift Register Level Shift Circuits Output Circuits OUT4 Shift Register Level Shift Circuits Output Circuits OUT5 Shift Register Level Shift Circuits Output Circuits OUT6 Shift Register Level Shift Circuits Output Circuits OUT254 Shift Register Level Shift Circuits Output Circuits OUT255 Shift Register Level Shift Circuits Output Circuits OUT256 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 Terminal Functions TERMINAL NAME I/O DESCRIPTION CPV I Vertical shift clock input The shift register’s shift clock. Data are shifted in sync with the rising edge of this pin. OE1 OE2 OE3 I Output enable pins The liquid-crystal control output is held low by setting pins OE1, 2, and 3 High. However, the shift registers are not cleared. OE is async with CPV. Enable control target pin: OE1: OUT1, OUT4, OUT7...OUT253, OUT256 OE2: OUT2, OUT5, OUT8...OUT254 OE3: OUT3, OUT6, OUT9...OUT255 These combinations are generally as above, regardless of the L/R polarity. L/R I Shift direction switching pin This pin is used to switch the data’s shift direction. L/R = L: STV1 ← OUT1 ← OUT2...OUT255 ← OUT256 ← STV2 L/R = H: STV1 → OUT1 → OUT2...OUT255 → OUT256 → STV2 STV1 STV2 I/O Shift data I/O pins These pins are used to input/output data to/from a shift register. During input, data are captured in sync with the leading edge of CPV. During output, data are output in sync with its trailing edge. L/R = L: STV1 is the next-stage data output pin, and STV2 is the shift data input pin. L/R = H: STV1 is the shift data input pin, and STV2 is the next-stage data output pin. OUT1 thru OUT256 O Output terminals VCOM VDD Power supply for high-withstand-voltage logic VSS VEE GND for logic input VL Negative power supply for liquid-crystal control Power supply for logic input GND POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 detailed description liquid-crystal control output voltage The MPT57605 enables negative-voltage output for the liquid-crystal control output. VCOM – VL = 35 V max VL – VEE = 0-6 V. VCOM – VSS = 10-25 V. Out V(COM) Logic Input VDD VSS VEE = VL Figure 1. Liquid-Crystal Control Output Voltage For the input signals (CPV, OE1-3, L/R, STV1 and STV2), input the amplitude of VDD from VSS. The next-stage data output pins (STV1, STV2) output the next level: H level = VDD L level = VSS details of operation The liquid-crystal control outputs (OUT1-256) output either a selective signal (H) or a nonselective signal (L), depending on the input signals (STV1 and STV2, CPV, OE1, OE2, OE3). A right data shift (OUT1 → OUT256) or a left data shift (OUT256 → OUT1) can be selected by means of the shift direction switching pin (L/R). When the L/R pin is H, the vertical shift data (STV1) are captured at the leading edge of the shift clock (CPV), after which they are output to the liquid-crystal control output OUT1. Furthermore, the OUT1 output data are shifted to OUT2 at the leading edge of the next CPV, and the data newly fetched from STV1 are output to OUT1. In this manner, they are shifted successively in sync with the leading edge of CPV, and the OUT256 data are output to STV2 in sync with the trailing edge of CPV. When the L/R pin is L, the vertical shift data (STV2) are captured at the leading edge of the shift clock (CPV), after which they are output to the liquid-crystal control output OUT256. Furthermore, the OUT256 output data are shifted to OUT255 at the leading edge of the next CPV, and the data newly fetched from STV2 are output to OUT256. In this manner, they are shifted successively in sync with the leading edge of CPV, and the OUT1 data are output to STV1 in sync with the trailing edge of CPV. Also, while OE1, OE2, and OE3 are H, the corresponding liquid-crystal control outputs (OE1: OUT1, 4, 7,...; OE2: OUT2, 5, 8,...; OE3: OUT 3, 6, 9,...) all become nonselective signals (L). In order to hold the internal data, however, the previous state is restored by again setting to L. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 detailed description (continued) 1 2 3 4 5 6 7 256 257 258 CPV STV1 OE1 OE2 OE3 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT256 STV2 Figure 2. Recommended Operation Timing (L/R = H) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 absolute maximum ratings (referenced to VSS = 0 V)† Supply voltage‡§, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to 7 V VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 20 to 0.3 V VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VEE – 0.3 to VEE + 7 V VCOM – VEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to 40 V Input voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 to VDD + 0.3 V Storage temperature, TSTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ‡ Unless otherwise indicated, all voltages are with reference to VSS. § Power up in the following order: VDD → VEE → input signal → VCOM. Power down by reversing the sequence. recommended operating conditions (referenced to VSS = 0 V) MIN TYP MAX Supply voltage, VDD 3.0 3.3 3.6 V Supply voltage, VCOM 10 25 V – 15 –5 V Supply voltage, VEE Supply voltage, VL – VEE Supply voltage, VCOM – VEE Low-level input voltage, VIL High-level input voltage, VIH 0 6 V 17 35 V VSS 0.9 × VDD 0.1 × VDD V Clock frequency, fCPV Operating free-air temperature, TA UNIT – 55 VDD 100 kHz V 125 °C electrical characteristics over full range of recommended operating conditions, VSS = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 40 µA IOH = – 40 µA VOL VOH Low-level output voltage (STV1, STV2) ROL Low-level output resistance (OUT1–OUT256) ROH High-level output resistance (OUT1–OUT256) VOUT = VL + 0.2 V VOUT = VCOM – 0.2 V II IDD Input current All input terminals High-level output voltage (STV1, STV2) Continuous current dissipation MIN VSS VDD – 0.4 –5 TYP MAX UNIT VSS + 0.4 VDD V 1000 Ω 1000 Ω 5 µA 500 V See Notes 1 and 2 µA ICOM Continuous current dissipation 100 NOTES: 1. Current consumption by a 1/768-duty liquid-crystal display. 2. Condition: The outputs are no load. The inputs are VIH = VDD, VIL = VSS, fCPV = 50 kHz, fSTV = 104.2 Hz, and OE1-3 = VIL. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 timing requirements over full range of recommended operating conditions, VSS = 0 V (unless otherwise noted) PARAMETER MIN MAX UNIT 100 KHz fCP tCPVH, tCPVL Operating frequency CPV clock pulse width 4 µs tWCL tsu Clear enable time 1 µs Data setup time 700 ns th Data hold time 700 ns switching characteristics over full range of recommended operating conditions, VSS = 0 V (unless otherwise noted) PARAMETER tpd1 tpd2 MAX UNIT Propagation delay time, CPV to outputs CL = 300 pF 1500 ns Propagation delay time, CPV to STV1, STV2 CL = 30 pF 800 ns CL = 300 pF 800 ns tpd3 Propagation delay time, output enables to outputs NOTE: The ac timing is 50% of the I/O amplitude, for each signal. POST OFFICE BOX 655303 TEST CONDITIONS • DALLAS, TEXAS 75265 MIN 7 MPT57605 256-OUTPUT TFT GATE DRIVER SGLS116A – JANUARY 2001 – REVISED MAY 2001 timing diagram of ac characteristics (when L/R = H) tCPVH tCPVL CPV 50% tsu th 50% STV1 tpd1 tpd1 50% OUT1 tpd1 tpd1 OUT2– OUT256 50% CPV 50% OUT256 50% tpd2 STV2 tpd2 50% tWCL OE1 OE2 OE3 50% tpd3 tpd3 OUT1– OUT256 8 50% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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