AD120 Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver Document Title 3-Level / 258 Outputs TFT LCD Gate Driver Revision History Rev. No. 0.0 History Issue Date Remark Initial issue August 10, 2001 Preliminary Important Notice: AMIC reserves the right to make changes to its products or to discontinue any integrated circuit product or service without notice. AMIC integrated circuit products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. Use of AMIC products in such applications is understood to be fully at the risk of the customer. PRELIMINARY (August, 2001, Version 0.0) AMIC Technology, Inc. AD120 Preliminary 3-Level / 258 Outputs TFT LCD Gate Driver Features n n n n n n Bi-directional data shift control n Output waveform control n TCP available TFT LCD gate driver 3-level / 258 outputs 40V max. for each output -15V min. for each output 2.7V~3.6V logic input/output level AD120 is a gate driver for TFT LCD panel. There are 258 outputs in the chip. Three-level output allows voltage correction for better switching noise rejection. It can be used for XGA / SXGA panels. Block Diagram ST1 ST1X ST2 ST2X Shift Register R/L CP ......... XOFF XON OGW Decoder ......... VH VOFF VL Output ......... VDD VSS OUT0 OUT1 OUT2 PRELIMINARY (August, 2001, Version 0.0) ......... 1 OUT255 OUT256 OUT257 AMIC Technology, Inc AD120 PRELIMINARY 17 16 VH 15 ST1 14 ST2 13 VSS 12 CP 11 VDD 10 XOFF 9 XON 8 R/L 7 OGW 6 ST2X 5 ST1X 4 VH 3 VOFF 2 VL 1 (August, 2001, Version 0.0) AD120 2 OUT0 19 OUT1 20 OUT2 21 OUT3 22 OUT4 ....................................................................... VL VOFF 18 ...................................................................... TCP Pinout 271 OUT253 272 OUT254 273 OUT255 274 OUT256 275 OUT257 AMIC Technology, Inc AD120 Input/Output Pin Function Pin No. Symbol I/O 11 CP I R /L I 7 Description Clock pulse Right / left direction control for shift register When R /L is LOW, data are shifted to the right, or ST1 / ST2 .… output257. output0 When R /L is HIGH, data are shifted to the left, or ST1X / ST2X output256 .... output0. 8 XON I XON to force all the outputs to VH voltage. It is not synchronous to CP. 9 XOFF I XOFF to force all the outputs to VOFF voltage. output1 output257 It is not synchronous to CP. 6 OGW I 4,5, 13,14 ST1, ST2, I/O ST1X, ST2X When R /L is LOW, ST1 / ST2 are defined as inputs while ST1X / ST2X are defined as outputs . The synchronized ST1 / ST2 signals are placed at ST1X / ST2X after 256 CP pulses. When R /L is HIGH, ST1X / ST2X are defined as inputs, while ST1/ST2 are defined as outputs. The synchronized ST1X / ST2X signals are placed at ST1 / ST2 after 256 CP pulses. Output drivers These outputs are synchronized to CP pulses. The output format and voltage level are controlled by OGW, XON , XOFF , ST1 / ST2, ST1X / ST2X and R /L correspondingly as shown in the diagram. Output Gate pulse Width to select output_waveform format. 18 - 275 OUT0~ OUT257 O 12 VSS PWR Reference voltage 10 VDD PWR 3, 15 VH PWR Supply voltage for logic operation VDD and VSS are voltage levels of input / output logic signals High voltage for output drivers 1, 17 VL PWR Low voltage for output drivers 2, 16 VOFF PWR OFF voltage for output drivers PRELIMINARY (August, 2001, Version 0.0) 3 AMIC Technology, Inc AD120 Description Operation Output signals OUT0~OUT257 are used for control of the TFT gates of the LCD panel. A bi-directional shift register is implemented to sequentially output signals OUT0~OUT257. A clock pulse CP is applied to the bi-directional shift register and the direction of the register is controlled by R /L signal. When R /L is LOW and either starting signal ST1 or ST2 goes to HIGH, the shift register starts shifting from OUT0 to OUT257. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1X / ST2X switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. When R /L is HIGH and either starting signal ST1X or ST2X goes to HIGH, the shift register starts shifting from OUT257 to OUT0. The voltages of the corresponding outputs switch to VH, VL or VOFF depending on the starting signals as shown in the diagram. The outputs of the starting signals ST1/ST2 switch accordingly after 256 CP pulses following start of the shift register which allows expansion of the outputs by cascading more devices. 3-Level Output VH - VL = 40V(max.) VOFF - VL = 0~10V VH - VSS = 17~28V OUT VH Level VDD VSS VOFF VL PRELIMINARY (August, 2001, Version 0.0) 4 AMIC Technology, Inc AD120 Operation Diagram 1 ( R /L = L, OGW = L) 2 3 256 257 ~ ~ 1 CP ST1 ~ ~ VDD V SS ST2 V SS OUT0 VOFF ~ ~ VDD ~ ~ VH VL OUT1 ~ ~ VH VOFF VL OUT2 ~ ~ VH VOFF VL VH OUT3 VOFF VL VH VOFF VL ~ ~ OUT256 VH VOFF VL ~ ~ OUT257 VDD V SS ~ ~ ST1X VDD V SS PRELIMINARY ~ ~ ST2X (August, 2001, Version 0.0) 5 AMIC Technology, Inc AD120 Operation Diagram 2 ( R /L = L, OGW = H) 1 2 3 CP ST1 ST2 XOFF VDD VSS XON VDD VSS VH OUT0 VOFF VL VH OUT1 VOFF VL OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 PRELIMINARY (August, 2001, Version 0.0) 6 AMIC Technology, Inc AD120 Table 1. Function of XON and XOFF XON XOFF OUT0~OUT257 L X VH H L VOFF H H Table2 * The outputs are asynchronous to CP. Table 2. Control of OUT1~OUT256 ( XON = H, XOFF = H) ( R /L = L) ST1 ST2 ( R /L = H) ST1X ST2X L OGW OUT1~OUT256 L X VOFF L H X VL H L X VL L VH H H H VH (CP = “L”) VL (CP = “H”) * The outputs are synchronous to CP. Table 3. Control of OUT0 and OUT257 ( XON = H, XOFF = H) ( R /L = L) ST1 ST2 OUT0 ( R /L = H) ST1X ST2X OUT257 L L VOFF L H VL H L VL H H VL * The outputs are synchronous to CP. PRELIMINARY (August, 2001, Version 0.0) 7 AMIC Technology, Inc AD120 Absolute Maximum Ratings Over Operating Free-air Temperature Range Parameter Symbol Ratings Unit Supply Voltage VDD -0.3 ~ +7.0 V Supply Voltage VH -0.3 ~ 42.0 V Supply Voltage VL -20.0 ~ +0.3 V Supply Voltage VOFF VL-0.3 ~ VL+11.0 V Supply Voltage VH - VL -0.3 ~ 42.0 V Input Voltage VIN -0.3 ~ VDD+0.3 V Storage Temperature Tstg -55 ~ 125 °C Power_on Sequence and Voltage Levels VH VDD Out0~Out257 VSS VOFF VL VDD Logic Signal VSS Operating Voltage Range Parameter Symbol Min. Typ. Max. Unit Supply Voltage VDD 2.7 3.3 3.6 V Supply Voltage VH 17 - 28 V Supply Voltage VL -15 - -5 V Supply Voltage VOFF - VL 0 - 10.0 V Supply Voltage VH - VL 22 - 40 V Clock Frequency fCP - - 100 KHz Operating Free-air Temperature Ta -20 - +75 °C PRELIMINARY (August, 2001, Version 0.0) 8 AMIC Technology, Inc AD120 DC Charactertics (VDD = 2.7~3.6V, Ta = -20~75°C) Parameter Symbol Condition Min. Max. Unit Applicable Pin Low Level Input Voltage VIL VSS 0.2 X VDD V All input pins High Level Input Voltage VIH 0.8 X VDD VDD V All input pins Note Low Level Output Voltage VOL IOL = 40µA VSS VSS + 0.4 V High Level Output Voltage VOH IOH = 40µA VDD -0.4 VDD V ST1, ST2, ST1X, ST2X Output Resistance (1) RL VOUT = VL + 0.5 1000 Ù OUT0~OUT257 1 Output Resistance (2) ROFF VOUT = VOFF + 0.5 1000 Ù OUT0~OUT257 1 Output Resistance (3) RH VOUT = VH - 0.5 1000 Ù OUT0~OUT257 1 II VI = VDD / VSS +5.0 µA All input pins Input Current -5.0 Operating Current (1) IDD 1500 µA VDD 1, 2 Operating Current (2) IH 100 µA VH 1, 2 Notes: 1. VH = 25V, VOFF = 0V, VL = -10V 2. CP = 50KHz AC Charactertics (VDD = 2.7~3.6V, Ta = -20~75°C) Parameter Symbol Condition Min. Max. Unit Clock Frequency fCP 100 KHz CP High Pulse Width tCPH 1 µs CP Low Pulse Width tCPL 4 µs Input Rise Time tr 10% ~ 90% 50 ns Input Fall Time tf 90% ~ 10% 50 ns Gate Off Time tWOFF 1 µs Data Setup Time tSU 700 ns Data Hold Time thd 700 ns Delay Time 1 tpd1 CL = 20pF 800 ns Delay Time 2 tpd2 CL = 300pF 1000 ns Delay Time 3 tpd3 CL = 300pF 1000 ns Delay Time 4 tpd4 CL = 300pF 1000 ns Delay Time 5 tpd5 CL = 300pF 1000 ns PRELIMINARY (August, 2001, Version 0.0) 9 AMIC Technology, Inc AD120 Timing Waveform 1 CP 2 0.5 x V DD 0.5 x V DD tSU ST1, ST2 0.5 x V DD 257 0.5 x V DD 0.5 x V DD thd 0.5 x V DD Input 256 0.5 x V DD ~ ~ 0.5 x V DD tCPL ~ ~ tCPH tpd1 Output ~ ~ STX1, STX2 OUT0~OUT257 50% 50% tpd2 ~ ~ tpd2 tpd1 80% 20% -----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = H) 0.5 x V DD 0.5 x V DD 0.5 x V DD 0.5 x V DD 0.5 x V DD 0.5 x V DD CP tpd2 tpd2 tpd2 tpd2 tpd2 80% 80% OUT0~257 VH VOFF 80% 20% 20% tpd2 20% VL -----------------------------------------------------------------------------------------------------------------------------------------------------------------------(OGW = L) 0.5 x VDD 0.5 x VDD 0.5 x VDD tpd2 tpd2 0.5 x VDD 0.5 x VDD CP tpd2 tpd2 VH OUT0~OUT257 20% 80% 80% tpd2 VOFF 20% 20% VL PRELIMINARY (August, 2001, Version 0.0) 10 AMIC Technology, Inc AD120 Timing Waveform (continued) XOFF 0.5 x V DD 0.5 x V DD twOFF tpd3 tpd3 80% OUT0~OUT257 20% 80% VOFF 20% VH VL ------------------------------------------------------------------------------------------------------------------------------------------------------------------------ XON 0.5 x V DD 0.5 x V DD tpd4 tpd4 OUT0~OUT257 PRELIMINARY (August, 2001, Version 0.0) 20% 11 80% VH AMIC Technology, Inc AD120 Ordering Information Part No. Package AD120T TCP PRELIMINARY (August, 2001, Version 0.0) 12 AMIC Technology, Inc