KT8554B/7B 1 CHIP CODECS INTRODUCTION 16-CERDIP The KT8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system. These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk. These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information. 16-DIP300A FEATURES • Complete CODEC and filtering system • Meets or exceeds AT&T D3/D4 and CCITT specifications µ-Law : KT8554B, A-Law : KT8557B • On-chip auto zero, sample and hold, and precision voltage references • Low power dissipation : 60mW (operating) 3mW (standby) • ± 5V operation • TTL or CMOS compatible • Automatic power down 16-SOP-BD300 -SG ORDERING INFORMATION Device PIN CONFIGURATION BCLK - 25 ~ 125°C KT8557BN KT8554BN 16-DIP-300A - 25 ~ 70°C KT8554BD KT8557BD 16-SOP-BD300 -SG - 25 ~ 70°C 16 VF X I + 2 15 VF X I - VF RO 3 14 GS X V CC 4 13 TS X FS R 5 12 FS X S DR 6 11 DX 7 10 BCLK X 8 9 MCLK X GNDA R/CLKSEL MCLK R/PDN KT8554B/7B Fig. 1 Operating Temperature 16-CERDIP 1 V BB Package KT8554BJ KT8557BJ KT8554B/7B 1 CHIP CODECS PIN DESCRIPTION Pin No Symbol Description VBB = - 5V ±5%. 1 VBB 2 GNDA Analog ground. 3 VFRO Analog output of the receive power Amp. 4 VCC VCC = +5V ± 5%. 5 FSR Receive frame sync pulse. 8KHz pulse train. 6 DR PCM data input. 7 BCLKR / CLKSEL Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock in normal operation and BCLKX is used for both TX and RX directions. Alternately direct clock input available, very from 64KHz to 2.048MHz. 8 MCLKR / PDN When MCLKR is connected continuously high, the device is powered down. Normally connected continusously low, MCLKX is selected for all DAC timing. Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available. 9 MCLKX 10 BCLKX Must be1.536MHz/1.544MHz or 2.048MHz. May be vary from 64KHz to 2.048MHz but BCLKX is externally tied with MCLKX in normal operation. 11 DX PCM data output. 12 FSX TX frame sync pulse. 8KHz pulse train. 13 TSX Changed from high to low during the encoder timeslot. Open drain output. 14 GSX Analog output of the TX input amplifier. Used to set gain through external resistor. 15 VFXI - 16 + VFXI Inverting input stage of the TX analog signal. Non-inverting input stage of the TX analog signal. ABSOLUTE MAXIMUM RATINGS (Ta = 25oC) Characteristic Symbol Value Unit Positive Supply Voltage VCC 7 V Negative Supply Voltage VBB -7 V Voltage at Any Analog Input or Output VI (A) VCC + 0.3 to VBB - 0.3 V Voltage at Any Digital Input or Output Vl (D) VCC + 0.3 to GNDA - 0.3 Operating Temperature Range Ta - 25 to + 125 o Storage Temperature Range T STG - 65 to + 150 o Lead Temperature (Soldering, 10 secs) T LEAD 300 o V C C C KT8554B/7B 1 CHIP CODECS ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 5.0V ±5%, VBB = - 5.0V ±5%, GNDA = 0V, Ta = 0 oC to 70 oC ; typical characteristics specified at VCC = 5.0V, VBB = - 5.0V, Ta = 25 oC ; all signals referenced to GNDA). Characteristic Power Symbol Test Conditions Min Typ Max Unit Dissipation Power-Down Current ICC (DOWN) No Load 0.5 1.5 mA Power-Down Current IBB (DOWN) No Load 0.05 0.3 mA Active Current ICC (A) No Load 6.0 9.0 mA Active Current IBB (A) No Load 6.0 9.0 mA 0.6 V 10 µA 10 µA 0.4 0.4 0.4 V V V Digital Interface Input Low Voltage VIL Input High Voltage VIH Input Low Current IIL Input High Current IIH 2.2 GNDA ≤ VIN≤VIL, all digital inputs -10 VIH ≤ VIN ≤ VCC -10 Output Low Voltage VOL DX,IL = 3.2mA SIGR, IL = 1.0mA TSX, IL = 3.2mA,open drain Output High Voltage VOH DX, IH = -3.2mA SIGR, IH = -1.0 mA 2.4 2.4 Output Current in High Impedance State (TRI-STATE) IO (HZ) DX, GNDA ≤ VO ≤ VCC -10 V V V 10 µA 3 Ω 500 pF -200 200 mV 200 Analog Interface with Receive Filter Output Resistance RO Pin VFRO Load Resistance RL VFRO = ±2.5V Load Capacitance CL Output DC Offset Voltage VOO (RX) 1 Ω 600 Analog Interface with Transmit input Amplifier Input Leakage Current ILKG -2.5V≤V≤+2.5V, VFXI + or VFXI - -200 Input Resistance RI -2.5V≤V≤+2.5V, VFXI + or VFXI - 10 Output Resistance RO Closed loop, unity gain Load Resistance RL GSX CL GSX Load Capacitance Output Dynamic Range Voltage Gain Unity Gain Bandwidth VOD (TX) GV nA MΩ 1 3 10 Ω KΩ 50 pF GSX, RL≤10KW ±2.8 V VFXI + to GSX 5,000 V/V BW 1 Offset Voltage VIO (TX) -20 2 20 MHz Common-Mode Voltage VCM (TX) CMRRXA > 60dB -2.5 2.5 Common-Mode Rejection Ratio CMRR DC Test 60 dB Power Supply Rejection Ratio PSRR DC Test 60 dB mV V KT8554B/7B 1 CHIP CODECS TIMING CHARACTERISTICS (Unless otherwise noted, VCC = 5.0 ±5%, VBB = -5.0V ±5%, GNDA = 0V, Ta = 0oC to 70 oC; typical characteristics specified at VCC = 5.0V, VBB = -5.0V, Ta = 25 oC; all signals referenced to GNDA.) Characteristic Frequency of Master Clocks Symbol fMCK Test Conditions Min Depends on the device used and the BCLKR /CLKSEL Pin. MCLKX and MCLKR Typ Max 1.536 1.544 2.048 Unit MHz MHz MHz Rise Time of Bit Clock tR (BCK) tPB = 488ns 50 ns Fall Time of Bit Clock tF (BCK) tPB = 488ns 50 ns Holding Time from Bit Clock Low to Frame Sync tH (LFS) Long frame only 0 ns Holding Time from Bit Clock High to Frame Sync tH (HFS) Short frame only 0 ns tSU (FBCL) Long frame only 80 ns 0 Set-Up Time from Frame Sync to Bit Clock Low Delay Time from BCLKX High to Data Valid tD (HDV) Load = 150pF plus 2 LSTTL loads Delay Time to TSX Low tD (TSXL) Load = 150pF plus 2 LSTTL loads Delay Time from BCLKX Low to Data Output Disabled tD (LDD) Delay Time to Valid Data from FSX or BCLKX, Whichever Comes Later tD (VD) CL = 0pF to 150pF 180 ns 140 ns 50 165 ns 20 165 ns Set-Up Time from DR Valid to BCLKR/X Low tSU (DR BL) 50 ns Hold Time from BCLKR/X Low to D R Invalid tH (BL DR) 50 ns Set-Up Time from FSX/R to BCLKX/R Low tSU (FBLS) Short frame sync pulse (1 or 2 bit clock periods long) (Note1) 50 ns Width of Master Clock High tW (MCKH) MCLKX and MCLKR 160 ns Width of Master Clock Low tW (MCKL) MCLKX and MCLKR 160 ns Rise Time of Master Clock tR (MCK) MCLKX and MCLKR 50 ns Fall Time of Master Clock tF( MCK) MCLKX and MCLKR 50 ns 15,72 5 ns Set-Up Time from BCLKX High (and FSX In Long Frame Sync Mode) to MCLKX Falling Edge Period of Bit Clock tSU (BHMF) First bit clock after the leading edge of FSX tCK 485 488 Width of Bit Clock High tW (BCKH) VIH = 2.2V 160 ns Width of Bit Clock Low tW (BCKL) VIL = 0.6V 160 ns KT8554B/7B 1 CHIP CODECS TIMING CHARACTERISTICS (Continued) Characteristic Symbol Test Conditions Min Typ Max Unit tH (BLFL) Short frame sync pulse (1 or 2 bit clock periods long) (Note 1) 100 ns Hold Time from 3rd Period of Bit Clock Low to Frame Sync (FSX or FSR) tH (3rd ) Long frame sync pulse (from 3 to 8 bit clock periods long) 100 ns Minimum Width of the Frame Sync Pulse (Low Level) tWFL 64K bit/s operating mode 160 ns Hold Time from BCLKX/R Low to FSX/R Low Note 1 : For short frame sync timing, FSX and FSR must go high while their respective bit clocks are high. TIMING DIAGRAM tD (LDD) tD (TS X L) tF (MCK) tR (MCK) tW (MCKH) tH (HFS) tSU (FBLS) tW (MCKL) tCK tSU (BHMF) tH (BLFL) tD (HDV) tH (HFS) tSU (FBCL) tD (LDD) tH (BLFL) tSU (DR BL) Fig. 2. Short Frame Sync Timing tH (BLDR) tH (BLDR) KT8554B/7B TIMING DIAGRAM 1 CHIP CODECS (Continued) tR (MCK) tW (MCKL) tCK tW (BCKH) tW (BCKL) tSU (BHMF) tRB tH (HFS) tD (HDV) tD (VD) tD (LDD) tD (VD) tH (HFS) tSU(FBCK) tH (3rd) tSU (DR BL) tH (BL DR) Fig. 3 Long Frame Sync Timing tH (BL DR) KT8554B/7B 1 CHIP CODECS TRANSMISSION CHARACTERISTICS (Unless otherwise specified : Ta = 0oC to 70 oC, VCC = 5V ±5%, VBB = -5V ±5%, GNDA = 0V, f = 1.02KHz, VIN = 0dBm0, transmit input amplifier connected for unity-gain non-inverting.) Characteristic Symbol Test Conditions Min Typ Max Unit -0.15 0.15 dB -0.15 -0.35 -0.7 0.15 0.05 0 -14 dB dB dB dB Ta = 0 oC to 70 oC ±0.1 dB VCC = 5V ±5%, VBB = -5V ±5% ±0.05 dB 0.2 0.4 1.2 2.5 dB dB dB V Amplitude Respons Receive Gain, Absolute GV (ARX) Receive Gain, Relative to GV (ARX) GV (RRX) Absolute Receive Gain Variation with Temperature ∆GV (ARX) /∆T ∆GV (ARX) /∆V Absolute Receive Gain Variation with Supply Voltage Receive Gain Variations with Level Receive Output Drive Level Absolute Levels ∆GV (RXL) VO (RX) VAL Max Overload Level VOL (MAX) Transmit Gain, Absolute GV (ATX) Transmit Gain, Relative to GV (ATX) GV (RTX) Absolute Transmit Gain Variation with Temperature Absolute Transmit Gain Variation with Supply Voltage ∆GV(ATX) /∆T ∆GV (ATX) /∆V Transmit Gain Variations with Level ∆GV (TXL) Ta = 25 oC, VCC = 5V, VBB = -5V Input = Digital code sequence for 0dBm0 signal at 1020Hz f = 0Hz to 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz Sinusoidal test method ; reference input PCM code corresponds to an Ideally encoded -10dBm0 signal PCM level = -40dBm0 to +3dBm0 PCM level = -50dBm0 to -40dBm0 PCM level = -55dBm0 to -50dBm0 RL = 600Ω Nominal 0dBm0 level is 4dBm (600Ω) 0dBm0 Max overload level (3.17dBm0): KT8554B Max overload level (3.14dBm0): KT8557B Ta = 25 oC, VCC = 5V, VBB = -5V Input at GSX = 0dBm0 at 1020Hz f = 16Hz f = 50Hz f = 60Hz f = 200Hz f = 300Hz - 3000Hz f = 3300Hz f = 3400Hz f = 4000Hz f = 4600Hz and up, measure response from 0Hz to 4000Hz Ta = 0 oC to 70 oC -0.2 -0.4 -1.2 -2.5 -0.15 -1.8 -0.15 -0.35 -0.7 VCC = 5V ±5%, VBB = -5V ±5% Sinusoldal test method Reference level = - 10dBm0 VFXI + = - 40dBm0 to + 3dBm0 VFXI + = - 50dBm0 to - 40dBm0 VFXI + = - 55dBm0 to - 50dBm0 - 0.2 - 0.4 - 1.2 1.2276 Vrms 2.501 VPK 0.15 dB -40 -30 -26 -0.1 0.15 0.05 0 -14 -32 dB dB dB dB dB dB dB dB dB ±0.1 dB ±0.05 dB 0.2 0.4 1.2 dB dB dB KT8554B/7B 1 CHIP CODECS TRANSMISSION CHARACTERISTICS (Continued) Characteristic Symbol Envelope Delay Distortion with Frequency Receive Delay, Absolute tD (ARX) Receive Delay, Relative to tD (ARX) tD (RRX) Transmit Delay, Absolute tD (ATX) Transmit Delay, Relative to tD (ATX) Noise Receive Noise, C Message Weighted Receive Noise, P Message Weighted Transmit Noise, C Message Weighted Transmit Noise, P Message Weighted Noise, Single Frequency tD (RTX) NRXC NRXP Test Conditions Min f = 1600Hz f = 500Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz f = 1600Hz -40 -30 f = 500Hz - 600Hz f = 600Hz - 800Hz f = 800Hz - 1000Hz f = 1000Hz - 1600Hz f = 1600Hz - 2600Hz f = 2600Hz - 2800Hz f = 2800Hz - 3000Hz PCM code equals alternating positive and negative zero, KT8554B PCM code equals, positive zero, KT8557B Typ Max 180 200 Unit µs µs µs µs µs µs -25 -20 70 100 145 290 90 125 175 315 195 120 50 20 55 80 130 220 145 75 40 75 105 155 µs µs µs µs µs µs µs 8 11 dBrnc0 -82 -79 dBm0p µs NTXC KT8554B 12 15 dBrnc0 NTXP KT8557B 74 -67 dBm0p NSF f = 0KHz to 100KHz, loop around measurement, VFXI + = 0Vrms VFXI + = 0Vrms, VCC = 5.0VDC + 100mVrms f = 0KHz - 50KHz VFXI + = 0Vrms, VBB = -5.0VDC + 100mVrms f = 0KHz - 50KHz PCM code equals positive zero VCC = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz f = 25KHz - 50KHz PCM code equals positive zero VBB = 5.0VDC + 100mVrms f = 0Hz - 4000Hz f = 4KHz - 25KHz f = 25KHz - 50KHz -53 dBm0 Positive Power Supply Rejection, Transmit PSRR Negative Power Supply Rejection, Transmit PSRR Positive Power Supply Rejection, Receive PSRR Negative Power Supply Rejection, Receive PSRR (PTX) (NTX) (PRX) (NRX) 40 dBC 40 dBC 40 40 36 dBC dB dB 40 40 36 dBC dB dB KT8554B/7B CMOS INTEGRATED CIRCUIT TRANSMISSION CHARACTERISTICS (Continued) Characteristic Spurious Out-of-Band Signals at the Channel Output Symbol Test Conditions SOS Loop around measurement, 0dBm0, 300Hz - 3400Hz input PCM applied to DR, Measure individual image signals at VFRO 4600Hz - 760Hz 7600Hz - 8400Hz 8400Hz - 100,000Hz Min typ Max Unit -32 -40 -32 dB dB dB Distortion Signal to Total Distortion Transmit or Receive Half-Channel THDTX THDRX Sinusoidal test method Level = 3.0dBm0 = 0dBm0 to 30dBm0 = -40dBm0 XMT RCV = -55dBm0 XMT RCV 33 26 29 30 14 15 dBC dBC dBC dBC dBC dBC Single Frequency Distortion, Transmit THD SF (TX) -46 dB Single Frequency Distortion, Receive THDSF (RX) -46 dB -41 dB -90 -75 dB -90 -70 (Note1) dB Intermodulation Distortion THDIMD Loop around measurement, VFXI + = -4dBm0 to -21dBm0, two frequencies in the range 300Hz - 3400Hz Crosstalk Transmit to Receive Crosstalk, 0dBm0 Transmit Level CT(TX-RX) f = 300Hz - 3400Hz DR = Steady PCM code Receive to Transmit Crosstalk, 0dBm0 Receive Level CT (RX-TX) f = 300Hz - 3400Hz, VFXI = 0V Note 1. CT(RX-TX) is measured with a - 40dBm0 activating signal applied at VFXI + ENCODING FORMAT AT Dx OUTPUT VIN (at GSX) = + Full Scale VIN (at GSX) = 0V VIN (at GSX) = - Full Scale µ-Law KT8554B A-Law KT8557B 10000000 10101010 11111111 11010101 01111111 01010101 00000000 00101010 KT8554B/7B CMOS INTEGRATED CIRCUIT APPLICATION CIRCUIT +5V -5V 0.1µF 4 VCC R2 FROMSLIC R1 TOSLIC R4 R3 0.1µF 2 GND 14 GSX DX DR 6 MCLKX 9 DR KT8554B/7B 15 VFXI- CLOCK BCLKX 10 3 VFRO BCLKR/CLKSEL 7 16 VFXI+ PDN 1 VBB DX11 FSXS 12 8 MCLKR/PDN R6 u-lowonly FSX/R FSR 5 Fig. 4 NOTE 1 : Supposing Desired Line Termination Impedance RL = 600ohm It is 0dBm = 0.77459Vrms NOTE 2 : TX Gain 20 log (R2/R1), R1 + R2 < 100Kohm, or The Correspondence of 1-CHIP CODEC 0dBm 0 = 4dBm. SELECTION OF MASTER CLOCK FREQUENCY BCLKR/CLKSEL KT 8554 KT 8557 Clocked 1.536 / 1.544 MHz 2.048MHz 0 2.048 MHz 1.536 / 1.544 MHz 1 (or open) 1.536 / 1.544 MHz 2.048MHz