TIME SLOT ASSIGNMENT CIRCUIT S5T8555 INTRODUCTION 20-CERDIP The S5T8555 is a per channel Time Slot Assignment Circuit (TSAC) that produces 8-bit receive and transmit time slots for four 1 CHIP CODEC. Each frame synchronization pulse may be independently assigned to a time slot in a frame of up to 64 time slots FEATURES • Single, 5V operation • Low power consumption: 5mW • Controls four 1 CHIP CODEC • Independent transmit and receive frame syncs • channel unidirectional mode • Up to 64 time slots per frame • Compatible with S5T8554B/7B CODECs • TTL and CMOS compatible ORDERING INFORMATION Device Package Operating Temperature S5T8555X01-L0B0 20−CERDIP −20°C to 125°C 1 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT PIN CONFIGURATION 2 FSX1 1 20 VCC FSR1 2 19 FSR2 FSX0 3 18 FSX2 FSR0 4 TSX 5 DC 6 15 CH0 CLKC 7 14 CH1 CS 8 13 RSYC /CH2 MODE 9 12 XSYC GND 10 11 BCLK KT8555 S5T8555 17 FSR3 16 FSX3 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 PIN DISCRIPTION Pin No Symbol Description 3 1 18 16 FSX0 FSX1 FSX2 FSX3 A Transmit frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid transmit time slot assignment is made. 4 2 19 17 FSR0 FSR1 FSR2 FSR3 A Receive frame sync output which is normally low, and goes active-high for 8 cycles of BCLK when a valid receive time slot assignment is made. 5 TSX This pin pulls low during any active transmit time slot. (N-channel open drain) 6 DC The input for an 8 bit serial control word. X is the first bit clocked in. 7 CLKC The clock input for the control interface. 8 CS The active-low chip select for the control interface. 9 MODE Mode 1 = Open or VCC Mode 2 = Gnd 10 GND Ground 11 BCLK The bit clock input (2.048 MHz) 12 XSYC The transmit Time Slot Output sync pulse input. Must be synchronous with BCLK. 13 RSYC /CH2 The receive time slot sync pulse input. Must be synchronous with BCLK. In mode 1 this input is the receive time slot 0 sync pulse, RSY C, which must be synchronous with BCLK. In mode 2 this is the CH2 input for the MSB of the channel select word. 14 CH1 The input for the NSB (next significant bit) of the channel select word. 15 CH0 The input for the LSB (last significant bit) of the channel select word, which defines the frame sync output affected by the following control word. 20 VCC Power supply pin. 5V ± 5% 3 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT ABSOLUTE MAXIMUM RATING (Ta = 25°C) Characteristic Symbol Value Unit VCC 70. V Input Voltage VI VCC + 0.3 ~ −0.3 V Output Voltage VO VCC + 0.3 ~ −0.3 V Operating Temperature Range TOPR − 25 ~ 125 °C Storage Temperature Range TSTG − 65 ~ 150 °C Lead Temperature (Soldering, 10 secs) TLEAD 300 °C Positive Supply Voltage 4 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 ELECTRICAL CHARACTERISTICS (Unless otherwise noted; VCC = 5.0V ± 5%, Ta = 0°C to 70°C) Characteristic Symbol Test Conditions Min. Typ. Max. Unit Operating Current ICC BCLK = 2.048MHz, all output open − 1 1.5 mA Input Voltage High VIH − 2.0 − − V Input Voltage Low VIL − − − 0.7 V Input Current 1 II1 All Inputs Except Mode, VIL≤VIN≤VIH −1 − 1 µA Input Current 2 II2 Mode, VIN = 0V −100 − − µA FSX and FSR Outputs, IOH = 3mA 2.4 − − V FSX and FSR Outputs, IOH = 3mA − − 0.4 V TSX output, IOL=3mA − − 0.4 V BCLK, CLKC − − 50 nS Output Voltage High VOH Output Voltage Low Rise and Fall Time of Clock tR (CK) tF (CK) Delay to TS X Low tD (TSXL) CL=50pF − − 140 nS Delay to TS X High tD (TSXH) RL=1kΩ 30 − 100 nS Hold Time BCLK to Frame Sync tH (BFS) − 50 − − nS Set-Up Time from Frame Sync BCLK tH (FSB) − 30 − − nS Delay Time from BLCK Low to FSX/R0-3 High or Low tD − − 50 nS Hold Time from Channel Select to CLK tH (CSC) − 50 − − nS Set-Up Time from Channel Select to CLK tSU (CSC) − 30 − − nS CL = 50pF tCK BCLK, CLKC 240 − − nS Width of Clock High tW (CKH) BCLK, CLK 50 − − nS Width of Clock Low tW (CKL) BCLK, CLK 50 − − nS Set-Up Time from DC to CLK tSU (DCC) − 30 − − nS Hold Time from CLK to DC tH (CDC) − 50 − − nS Set-Up Time from CS to CLK tSU (CC) − 30 − − nS Hold Time from CLK to CS tH (CC) − 100 − − nS Period of Clock 5 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT TIMING DIAGRAM tHCD tW(CKH) CONTROL INTERFACE tW(CKL) tH(CC) CLKC t R(CK) tH(CC) tSU(CC) tF(CK) CS t SU(CC) tSU(CSC) CH0, CH1 AND CH2 tH(CSC) tSU(DcC) 1 DC 2 3 4 5 tWCH 6 7 8 OUTPUT tDT(SxL) tSU(FSB) 1 BCLK 2 t H(BFS) t RS t FS 3 4 5 6 7 8 t W(CKL) tF(CK) tD t R(CK) XSYC OR RSYC tD FSX OR FSR tD(TSxH) MIN tD(TSxH) MAX TSX Figure 1. APPLICATION INFORMATION OPERATING CONTROL MODE 1 The S5T8555 is a control interface which requires an 8 bit serial control word. Either one of the frame sync output group, FSX0 to FXX3 or FSR0 to FSR3, affected by the control word is defined by the two bits, X and R. Time slot selected from 0 to 63 is specified. A frame sync output is highly active for one time slot which is equivalent to 8 cycles of BCLK. Up to 64 time slots are allowed to form a frame. There are two operational mode. In mode 1, each channel of transmit and receive direction has different time slot assigned. This mode can be selected by either leaving pin 9 (MODE) opened or connecting it with VCC. In such a case, pin 13 is RSYC input defining the start of each receive frame while four out-put, FSR0 to FSR3, are assigned with respect to RSYC. On the other hand, start of each transmit frame is defined by XSYC input by which output FS X0 to FSX3, are assigned. XSYC and RSYC can be phase related. Channels from 0-3 are selected by the input CH0 and CH1 (refer to the table 1). X R T5 T4 T3 X is the first bit clocked into DC input 6 T2 T1 T0 CH1 CH0 0 0 1 1 0 1 0 1 Channel Selected Assign to FSX0 and/or FSR0 Assign to FSX1 and/or FSR1 Assign to FSX2 and/or FSR2 Assign to FSX3 and/or FSR3 TIME SLOT ASSIGNMENT CIRCUIT S5T8555 Control Data Format Table 1. OPERATING CONTROL MODE 1 T5 T4 T3 T2 T1 T1 Time Slot X R Action 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 2 0 0 1 1 0 1 0 1 Assign time slot to both selected FSX and FSR Assign time slot to selected FSX only Assign time slot to selected FSR only Assign time slot to selected FSX and FSR . . . 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 30 31 32 33 . . . 1 1 1 1 1 1 63 OPERATING CONTROL MODE 2 In mode 2, all 8 frame sync outputs can be assigned with respect to XSYC input. The mode 2, selected by connecting pin 9 (MODE) to GND, enables the S5T8555 TSAC suitable for an 8-channel unidirectional controller and for a system where both transmit and receive direction of each channel have same time slot assigned. For instance, FSX and FSR input of 1 CHIP CODEC are hard wired together. The channel assigned has its channel selected by CH0, CH1 and CH2 (refer to table 2). CH2 CH1 CH0 Channel Selected X R 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Assign to FSX0 Assign to FSX1 Assign to FSX2 Assign to FSX3 Assign to FSR0 Assign to FSR1 Assign to FSR2 Assign to FSR3 0 0 1 1 0 1 0 1 Action Assign time slot to selected output Assign time slot to selected output Assign time slot to selected output Disable both selected output 7 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION CIRCUIT The S5T8555 TSAC combined with any kind of 1 CHIP CODEC from S5T8554B/7B series can obtain data timing as illustrated in Fig. 3. Even though FSX output goes high before BCLK gets high, the DX output of the 1 CHIP CODEC remains in the TRI-STATE mode until both outputs are high. The eight bit period is shortened to avoid PCM data clash at PCM pre-highway. Alternatively, full 8 bits can be obtained by inverting the BCLK to the 1 CHIP CODEC devices, thereby rising edges of BCLK and FSX/R are aligned. Fig. 4 is typical timing of the control data interface. Fig. 5 is the typical application circuit at operating control mode 2. 1 BCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 XSYC FSX1 FSX2 DX 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 TS X Figure 2. Transmit Data Timing CLKC CH0, CH1 CS DC X R T5 T4 T3 T2 T1 T0 Figure 3. Control Data Timing 8 X R T5 T4 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT APPLICATION CIRCUIT +5V 20 0.1µF VCC 10 9 GND MODE 3 1 13 TS X 7 CLKSEL FSR FS X DR 9 MCLK X 10 BCLK X 6 5 12 KT8554/57 1 CHIP CODEC # 0 1 CHIP CODEC #3 1 CHIP CODEC #2 1 CHIP CODEC #1 FS X2 1 CHIP CODEC #4 18 FS X3 16 FS X0 KT8555 1 CHIP CODEC #5 FSR3 17 5 FS R 12 FS X 6 DR 9 MCLK X 7 CLKSEL 10 BCLK X 13 TS X 63 62 . . . . 2 1 0 Time Slot 1 1 . . . . 0 0 0 T4 1 1 . . . . 0 0 0 T3 1 1 . . . . 0 0 0 T2 1 1 . . . . 1 0 0 T1 1 0 . . . . 0 1 0 T0 VFXI+ 16 14 VFXI- 15 DX GSX 8 8 3 11 VFRO PDN PDN DX 14 11 VFRO 3 GSX VF XI- 15 VF XI+ 16 1 CHIP CODEC #7 NOTE 4 : Time slot assign status KT8554/57 4 15 CH0 Action Timesolt assign FSR0 CH0 Time slot assign 1 CHIP CODEC #6 FS X1 R 0 Time slot assign 2 14 CH1 8 CS 0 Time slot assign disable Action FSR1 13 CH2 CS 7 CLKC 11 BCLK CLKC BCLK X 0 1 LSB T1 T0 12 XSYC T3 6 DC T4 XSYC T5 DC R 0 1 T5 Normal operation S5T8554B/7B S5T8554B/7B FSR2 19 CH1 T2 CH2 NOTE 1 : Dc Format MSB X 1 NOTE 2 : X, R action status 1 0 Time slot assign disable NOTE 3 : T5 action status 1 S5T8555 Figure 4. Digital Interface on a Typical Subscriber Linecard NOTES: Different time slot assign for RX and TX respectively 9 S5T8555 TIME SLOT ASSIGNMENT CIRCUIT NOTES 10