SERIAL PRESENCE DETECT PC100 Unbuffered DIMM PC100 Unbuffered DIMM(168pin) SPD Specification(64Mb D-die base) Rev. 0.1 Jan. 2000 Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT PC100 Unbuffered DIMM M366S0424DTS-C80/C1H/C1L • Organization : 4Mx64 • Composition : 4Mx16 *4 • Used component part # : K4S641632D-TC80/ TC1H/ TC1L • # of rows in module : 1 row • # of banks in component : 4 banks • Feature : 1,000mil height & single sided component • Refresh : 4K/64ms • Contents ; Byte # Function Supported Function Described -80 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 -1H Hex value -1L -80 -1H 128bytes 80h 256bytes (2K-bit) 08h Note -1L SDRAM 04h # of row address on this assembly 12 0Ch 1 4 # of column address on this assembly 8 08h 1 5 # of module rows on this assembly 1 row 01h 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly - 00h LVTTL 01h 9 SDRAM cycle time @CAS latency of 3 8ns 10ns 10ns 80h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 6ns 60h 60h 60h 2 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 2&3 06h 19 SDRAM device attributes : CS latency 0 CLK 01h 20 SDRAM device attributes : Write latency 0 CLK 01h 21 SDRAM module attributes Non-buffered, non-registered & redundant addressing 00h 22 SDRAM device attributes : General C0h 2 2 Non parity 00h 15.625us, support self refresh 80h x16 10h None 00h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 10ns 10ns 12ns A0h A0h 24 SDRAM access time from clock @CAS latency of 2 6ns 6ns 7ns 60h 60h 70h 25 SDRAM cycle time @CAS latency of 1 - - - 00h 00h 00h 26 SDRAM access time from clock @CAS latency of 1 - - - 00h 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns 50ns 50ns 30h 32h 32h 31 Module row density 32 Command and address signal input setup time 2ns 1 row of 32MB 2ns 2ns 20h 20h 20h 33 Command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h 34 Data signal input setup time 2ns 2ns 2ns 20h 20h 20h 08h Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 Function Supported Function Described Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code Hex value -80 -1H -1L -80 1ns 1ns 1ns 10h Superset information (maybe used in future) 64 65~71 PC100 Unbuffered DIMM -1L 10h 10h - 00h PC100 SPD Spec.Ver.1.2A 12h - DEh Samsung ...... Manufacturer JEDEC ID code 04h Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM configuration) 3 33h Blank 20h 6 36h Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 ...... Manufacturer part # (Data bits) 77 ...... Manufacturer part # (Data bits) 6 36h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 2 32h 82 Manufacturer part # (Composition component) 4 34h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) 34h CEh 72 86 Note -1H S 53h "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 8 1 1 38h 31h 31h 89 Manufacturer part # (Minimum cycle time) 0 H L 30h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 94 C 43h Blank 20h S 53h D-die (5th Gen.) 44h Manufacturing date (Week) - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 100MHz 64h 126 127 128+ System frequency for 100MHz PC100 specification details Unused storage locations Detailed 100MHz Information Undefined ADh AFh - ADh 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT PC100 Unbuffered DIMM M366S0823DTS-C80/C1H/C1L • Organization : 8Mx64 • Composition : 8Mx8 *8 • Used component part # : K4S640832D-TC80/C1H/C1L • # of rows in module : 1 row • # of banks in component : 4 banks • Feature : 1,375mil height & single sided component • Refresh : 4K/64ms • Contents ; Byte # Function Supported Function Described -80 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 -1H Hex value -1L -80 -1H 128bytes 80h 256bytes (2K-bit) 08h Note -1L SDRAM 04h # of row address on this assembly 12 0Ch 1 4 # of column address on this assembly 9 09h 1 5 # of module rows on this assembly 1 row 01h 6 Data width of this assembly 64 bits 40h 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly - 00h LVTTL 01h 9 SDRAM cycle time @CAS latency of 3 8ns 10ns 10ns 80h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 6ns 60h 60h 60h 2 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width C0h 2 2 Non parity 00h 15.625us, support self refresh 80h x8 08h 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address None 00h tCCD = 1CLK 01h 16 SDRAM device attributes : Burst lengths supported 17 SDRAM device attributes : # of banks on SDRAM device 1, 2, 4, 8 & full page 8Fh 4 banks 18 SDRAM device attributes : CAS latency 2&3 04h 06h 19 SDRAM device attributes : CS latency 0 CLK 01h 20 SDRAM device attributes : Write latency 0 CLK 01h 21 SDRAM module attributes Non-buffered, non-registered & redundant addressing 00h 22 SDRAM device attributes : General +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 10ns 10ns 12ns A0h A0h 24 SDRAM access time from clock @CAS latency of 2 6ns 6ns 7ns 60h 60h 70h 25 SDRAM cycle time @CAS latency of 1 - - - 00h 00h 00h 26 SDRAM access time from clock @CAS latency of 1 - - - 00h 00h 00h 27 Minimum row precharge time (=tRP) 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns 50ns 50ns 30h 32h 32h 31 Module row density 32 Command and address signal input setup time 2ns 1 row of 64MB 2ns 2ns 20h 20h 20h 33 Command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h 34 Data signal input setup time 2ns 2ns 2ns 20h 20h 20h 10h Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 Function Supported Function Described Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code Hex value -80 -1H -1L -80 1ns 1ns 1ns 10h Superset information (maybe used in future) 64 65~71 PC100 Unbuffered DIMM -1L 10h 10h - 00h PC100 SPD Spec. Ver. 1.2A 12h - DFh Samsung ...... Manufacturer JEDEC ID code 05h Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM configuration) 3 33h Blank 20h 6 36h Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 ...... Manufacturer part # (Data bits) 77 ...... Manufacturer part # (Data bits) 6 36h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 8 38h 81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 2 32h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) 35h CEh 72 86 Note -1H S 53h "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 8 1 1 38h 31h 31h 89 Manufacturer part # (Minimum cycle time) 0 H L 30h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 94 C 43h Blank 20h S 53h D-die (5th Gen.) 44h Manufacturing date (Week) - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 100MHz 64h 126 127 128+ System frequency for 100MHz PC100 specification details Unused storage locations Detailed 100MHz Information Undefined ADh AFh - ADh 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT PC100 Unbuffered DIMM M374S0823DTS-C80/C1H/C1L • Organization : 8Mx72 • Composition : 8Mx8 *9 • Used component part # : K4S640832D-TC80/C1H/C1L • # of rows in module : 1 row • # of banks in component : 4 banks • Feature : 1,375mil height & single sided component • Refresh : 4K/64ms • Contents ; Byte # Function Supported Function Described -80 0 # of bytes written into serial memory at module manufacturer 1 Total # of bytes of SPD memory device 2 Fundamental memory type 3 4 -1H Hex value -1L -80 -1H 128bytes 80h 256bytes (2K-bit) 08h Note -1L SDRAM 04h # of row address on this assembly 12 0Ch 1 # of column address on this assembly 9 09h 1 5 # of module rows on this assembly 1 row 01h 6 Data width of this assembly 72 bits 48h 7 ...... Data width of this assembly 8 Voltage interface standard of this assembly - 00h LVTTL 01h 9 SDRAM cycle time @CAS latency of 3 8ns 10ns 10ns 80h A0h A0h 2 10 SDRAM access time from clock @CAS latency of 3 6ns 6ns 6ns 60h 60h 60h 2 11 DIMM configuration type 12 Refresh rate & type 13 Primary SDRAM width 14 Error checking SDRAM width 15 Minimum clock delay for back-to-back random column address 16 SDRAM device attributes : Burst lengths supported C0h 2 2 ECC 02h 15.625us, support self refresh 80h x8 08h x8 08h tCCD = 1CLK 01h 1, 2, 4, 8 & full page 8Fh 4 banks 04h 17 SDRAM device attributes : # of banks on SDRAM device 18 SDRAM device attributes : CAS latency 2&3 06h 19 SDRAM device attributes : CS latency 0 CLK 01h 20 SDRAM device attributes : Write latency 0 CLK 01h Non-buffered, non-registered & redundant addressing 00h 21 SDRAM module attributes 22 SDRAM device attributes : General +/- 10% voltage tolerance, Burst Read Single bit Write 0Eh precharge all, auto precharge 23 SDRAM cycle time @CAS latency of 2 10ns 10ns 12ns 24 SDRAM access time from clock @CAS latency of 2 6ns 6ns 7ns 60h 60h 70h 25 SDRAM cycle time @CAS latency of 1 - - - 00h 00h 00h 26 SDRAM access time from clock @CAS latency of 1 27 Minimum row precharge time (=tRP) A0h A0h - - - 00h 00h 00h 20ns 20ns 20ns 14h 14h 14h 28 Minimum row active to row active delay (tRRD) 16ns 20ns 20ns 10h 14h 14h 29 Minimum RAS to CAS delay (=tRCD) 20ns 20ns 20ns 14h 14h 14h 30 Minimum activate precharge time (=tRAS) 48ns 50ns 50ns 30h 32h 32h 31 Module row density 10h 1 row of 64MB 32 Command and address signal input setup time 2ns 2ns 2ns 20h 20h 20h 33 Command and address signal input hold time 1ns 1ns 1ns 10h 10h 10h 34 Data signal input setup time 2ns 2ns 2ns 20h 20h 20h Rev 0.1 Jan. 2000 SERIAL PRESENCE DETECT Byte # 35 36~61 62 Function Supported Function Described Data signal input hold time SPD data revision code 63 Checksum for bytes 0 ~ 62 Manufacturer JEDEC ID code Hex value -80 -1H -1L -80 1ns 1ns 1ns 10h Superset information (maybe used in future) 64 65~71 PC100 Unbuffered DIMM -1L 10h 10h - 00h PC100 SPD Spec. Ver. 1.2A 12h - F1h Samsung ...... Manufacturer JEDEC ID code 17h Samsung 00h Onyang Korea 01h Manufacturer part # (Memory module) M 4Dh Manufacturer part # (DIMM configuration) 3 33h Blank 20h 7 37h Manufacturing location 73 74 75 Manufacturer part # (Data bits) 76 ...... Manufacturer part # (Data bits) 77 ...... Manufacturer part # (Data bits) 4 34h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 0 30h 80 ...... Manufacturer part # (Module depth) 8 38h 81 Manufacturer part # (Refresh, # of banks in Comp. & interface) 2 32h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) D 44h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) Manufacturer part # (Hyphen) 47h CEh 72 86 Note -1H S 53h "-" 2Dh 87 Manufacturer part # (Power) 88 Manufacturer part # (Minimum cycle time) 8 1 1 38h 31h 31h 89 Manufacturer part # (Minimum cycle time) 0 H L 30h 48h 4Ch 90 Manufacturer part # (TBD) 91 Manufacturer revision code (For PCB) 92 ...... Manufacturer revision code (For component) 93 94 C 43h Blank 20h S 53h D-die (5th Gen.) 44h Manufacturing date (Week) - - 3 Manufacturing date (Year) - - 3 95~98 Assembly serial # - - 4 99~125 Manufacturer specific data (may be used in future) Undefined - 5 100MHz 64h 126 127 128+ System frequency for 100MHz PC100 specification details Unused storage locations Detailed 100MHz Information Undefined ADh AFh - ADh 5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. Rev 0.1 Jan. 2000