SMMS702B − JANUARY 1998 − REVISED APRIL 1998
D Organization:
D
D
D
D
D
D
D
D
D JEDEC 168-Pin Dual-In-Line Memory
− TM2TR64EPH . . . 2 097 152 x 64 Bits
− TM4TR64EPH . . . 4 194 304 x 64 Bits
− TM2TR72EPH . . . 2 097 152 x 72 Bits
− TM4TR72EPH . . . 4 194 304 x 72 Bits
Single 3.3-V Power Supply
(±10% Tolerance)
Designed for 100-MHz 4-Clock Systems
TM2TR64EPH — Uses Eight 16M-Bit
Synchronous Dynamic RAMs (SDRAMs)
(2M × 8-Bit) in Plastic Thin Small-Outline
Packages (TSOPs)
TM4TR64EPH — Uses Sixteen 16M-Bit
SDRAMs (2M × 8-Bit) in Plastic TSOPs
TM2TR72EPH — Uses Nine 16M-Bit
SDRAMs (2M × 8-Bit) in Plastic TSOPs
TM4TR72EPH — Uses Eighteen 16M-Bit
SDRAMs (2M × 8-Bit) in Plastic TSOPs
Byte-Read/Write Capability
Performance Ranges:
SYNCHRONOUS
CLOCK CYCLE
TIME
tCK3
tCK2
(CL = 3)† (CL = 2)
ACCESS TIME
CLOCK TO
OUTPUT
tAC3
tAC2
(CL = 3) (CL = 2)
D
D
D
D
D
D
D
D
D
Module (DIMM) Without Buffer for Use With
Socket
High-Speed, Low-Noise, Low-Voltage TTL
(LVTTL) Interface
Read Latencies 2 and 3 Supported
Support Burst-Interleave and
Burst-Interrupt Operations
Burst Length Programmable to 1, 2, 4,
and 8
Two Banks for On-Chip Interleaving
(Gapless Access)
Ambient Temperature Range
0°C to 70°C
Gold-Plated Contacts
Pipeline Architecture
Serial Presence Detect (SPD) Using
EEPROM
REFRESH
INTERVAL
’xTRxxEPH-8
8 ns
10 ns
6 ns
6 ns
64 ms
’xTRxxEPH-8A
8 ns
15 ns
6 ns
7.5 ns
64 ms
† CL = CAS latency
description
The TM2TR64EPH is a 16M-byte, 168-pin DIMM. The DIMM is composed of eight TMS626812BDGE 2097 152
x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling capacitors.
See the TMS626812B data sheet (literature number SMOS693).
The TM4TR64EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of sixteen TMS626812BDGE
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors.
The TM2TR72EPH is an 16M-byte, 168-pin DIMM. The DIMM is composed of nine TMS626812BDGE
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors.
The TM4TR72EPH is a 32M-byte, 168-pin DIMM. The DIMM is composed of eighteen TMS626812BDGE
2 097 152 x 8-bit SDRAMs, each in a 400-mil, 44-pin plastic TSOP mounted on a substrate with decoupling
capacitors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
!" #!$% &"'
&! #" #" (" " ") !"
&& *+' &! #", &" ""%+ %!&"
", %% #""'
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1
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
operation
The TM2TR64EPH operates as eight TMS626812BDGE devices that are connected as shown in the
TM2TR64EPH functional block diagram. The TM4TR64EPH operates as sixteen TMS626812BDGE devices
connected as shown in the TM4TR64EPH functional block diagram.
The TM2TR72EPH operates as nine TMS626812BDGE devices that are connected as shown in the
TM2TR72EPH functional block diagram. The TM4TR72EPH operates as eighteen TMS626812BDGE devices
connected as shown in the TM4TR72EPH functional block diagram.
2
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SMMS702B − JANUARY 1998 − REVISED APRIL 1998
DUAL-IN-LINE MEMORY MODULE
( TOP VIEW )
TM2TR64EPH TM4TR64EPH
( SIDE VIEW ) ( SIDE VIEW )
PIN NOMENCLATURE
A[0:10]
A[0:8]
A11/BA0
CAS
CB[0:7]
CKE[0:1]
CK[0:3]
DQ[0:63]
DQMB[0:7]
1
10
NC
RAS
S[0:3]
SA[0:2]
11
SCL
SDA
VDD
VSS
WE
WP
Row-Address Inputs
Column-Address Inputs
Bank-Select Zero
Column-Address Strobe
Check Bit In/Check Bit Out
Clock Enable
System Clock
Data-In / Data-Out
Data-In/Data-Out
Mask Enable
No Connect
Row-Address Strobe
Chip-Select
Serial Presence Detect (SPD)
Device Address Input
SPD Clock
SPD Address / Data
3.3-V Supply
Ground
Write Enable
SPD Write-Protect
40
41
84
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3
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
Pin Assignments
PIN
NO.
NAME
NO.
1
43
2
VSS
DQ0
3
DQ1
4
NO.
85
44
VSS
NC
45
S2
DQ2
46
5
DQ3
6
7
VDD
DQ4
8
DQ5
9
PIN
NAME
NO.
PIN
NAME
127
86
VSS
DQ32
87
DQ33
129
S3
DQMB2
88
DQ34
130
DQMB6
47
DQMB3
89
DQ35
131
DQMB7
48
NC
90
132
NC
49
91
133
50
VDD
NC
VDD
DQ36
92
DQ37
134
VDD
NC
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
DQ9
54
97
VSS
DQ41
138
55
VSS
DQ16
96
13
139
VSS
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
101
DQ45
143
18
60
102
144
61
NC
103
VDD
DQ46
VDD
DQ52
19
VDD
DQ14
VDD
DQ20
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
CKE1
105
CB4
147
NC
22
CB1
64
106
CB5
148
23
VSS
NC
65
VSS
DQ21
107
149
66
DQ22
108
VSS
NC
VSS
DQ53
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
68
111
VDD
CAS
152
69
VSS
DQ24
110
27
VDD
WE
153
VSS
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0
72
DQ27
114
S1
156
DQ59
31
NC
73
115
RAS
157
32
74
116
VDD
DQ60
75
DQ29
117
VSS
A1
158
33
VSS
A0
VDD
DQ28
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
A7
162
A8
79
VSS
CK2
120
37
121
A9
163
VSS
CK3
38
A10
80
NC
122
A11/BA0
164
NC
39
NC
81
WP
123
NC
165
SA0
40
82
SDA
124
SA1
83
SCL
125
VDD
CK1
166
41
VDD
VDD
167
SA2
42
CK0
84
VDD
126
NC
168
VDD
24
4
PIN
NAME
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128
VSS
CKE0
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
dual-in-line memory module and components
The dual-in-line memory module and components include:
D PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage
D Bypass capacitors: Multilayer ceramic
D Contact area: Nickel plate and gold plate over copper
TM2TR64EPH functional block diagram
S0
RC
CS
CK: U0, U4
CS
CK0†
RC
CK: U1, U5
U0
DQMB0
DQM
R
DQ[0:7]
8
U4
DQMB4
DQ[32:39]
8
CK: U2, U6
CK2†
DQM
R
DQ[0:7]
RC
RC
CK: U3, U7
DQ[0:7]
RC
CK1
CS
C
CS
RC
CK3
U1
DQMB1
DQM
R
DQ[8:15]
8
U5
DQMB5
R
DQ[0:7]
C
DQM
DQ[40:47]
8
DQ[0:7]
R = 10 Ω
RC = 10 Ω
C = 10 pF
S2
DQMB2
DQM
R
8
Two 0.1 µF per
SDRAM device
CS
U2
DQ[16:23]
U[0:7]
VDD
CS
DQMB6
U[0:7]
DQM
R
DQ[0:7]
VSS
U6
DQ[48:55]
8
DQ[0:7]
SPD EEPROM
CS
CS
U3
DQMB3
DQ[24:31]
RAS
CAS
WE
CKE0
A[0:11]
DQM
R
8
U7
DQMB7
47 kΩ
DQM
R
DQ[0:7]
DQ[56:63]
RAS: SDRAM U[0:7]
CAS: SDRAM U[0:7]
WE: SDRAM U[0:7]
CKE: SDRAM U[0:7]
A[0:11]: SDRAM U[0:7]
8
SDA
SCL
WP
A0
A1
A2
SA0
SA1
SA2
DQ[0:7]
LEGEND: CS =
SPD =
Chip select
Serial Presence Detect
† Additional 3.3 pF capacity is used to balance loads among clocks.
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SMMS702B − JANUARY 1998 − REVISED APRIL 1998
TM4TR64EPH functional block diagram
S1
VDD
S0
CS
CS
CS
U[0:7], UB[0:7]
Two 0.1 µF per
SDRAM device
CS
VSS
U0
DQMB0
DQM
R
DQ[0:7]
8
R
DQ[8:15]
8
DQM
U4
DQMB4
R
DQ[0:7]
DQ[0:7]
CS
CS
U1
DQMB1
UB0
8
DQ[32:39]
UB1
DQM
DQM
DQ[0:7]
DQ[0:7]
DQM
DQM
DQ[0:7]
DQ[0:7]
CS
CS
U5
DQMB5
R
8
DQ[40:47]
U[0:7], UB[0:7]
UB4
UB5
DQM
DQM
DQ[0:7]
DQ[0:7]
VDD
10 kΩ
CKE1
CKE: UB[0:7]
CKE0
CKE: U[0:7]
RAS
RAS: U[0:7], UB[0:7]
CAS
CAS: U[0:7], UB[0:7]
WE
WE: U[0:7], UB[0:7]
A[0:11]
A[0:11]: U[0:7], UB[0:7]
R = 10 Ω
RC = 10 Ω
S3
RC
S2
CK0†
CS
U2
DQMB2
R
DQ[16:23]
8
CS
CS
UB2
DQM
DQM
DQ[0:7]
DQ[0:7]
CS
CS
U6
DQMB6
R
8
DQ[48:55]
CK: U1, U5
CS
UB6
DQM
DQM
DQ[0:7]
DQ[0:7]
CS
CS
CK: U0, U4
RC
RC
CK1†
CK: UB0, UB4
RC
CK: UB1, UB5
RC
CK2†
CK: U2, U6
RC
CK: U3, U7
RC
CK3†
CK: UB2, UB6
RC
CK: UB3, UB7
U3
DQMB3
DQM
R
DQ[24:31]
LEGEND: CS =
SPD =
8
DQ[0:7]
U7
UB3
DQM
DQ[0:7]
DQMB7
R
8
DQ[56:63]
UB7
DQM
DQM
DQ[0:7]
DQ[0:7]
Chip select
Serial Presence Detect
SCL
WP
47 kΩ
† Additional 3.3 pF capacity is used to balance loads among clocks.
6
SPD EEPROM
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SDA
A0
A1
A2
SA0 SA1 SA2
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
TM2TR72EPH functional block diagram
S0
RB
CS
DQMB0
U0
DQM
R
DQ[0:7]
8
U0, U4
CS
DQMB4
DQ[32:39]
8
CS
U1, U5, U8
U4
DQM
R
DQ[0:7]
RB
CK0
RC
U2, U6
DQ[0:7]
RC
CK2†
U3, U7
RC
CS
CK1
DQMB1
U1
DQM
R
DQ[8:15]
8
DQMB5
R
DQ[0:7]
U5
DQM
DQ[40:47]
8
C
DQ[0:7]
RC
CK3
CS
DQMB1
U8
DQM
R
CB[0:7]
8
DQ[0:7]
S2
VDD
CS
DQMB2
DQ[16:23]
8
U2
DQMB6
DQ[0:7]
DQ[48:55]
8
8
U3
DQMB7
DQ[0:7]
DQ[56:63]
RAS: SDRAM U[0:8]
CAS
CAS: SDRAM U[0:8]
WE
WE: SDRAM U[0:8]
A[0:11]
U[0:8]
CKE: SDRAM U[0:8]
A[0:11]: SDRAM U[0:8]
U7
DQM
R
RAS
CKE0
VSS
DQ[0:7]
CS
DQM
R
U6
DQM
R
CS
DQMB3
U[0:8]
Two 0.1 µF per
SDRAM device
CS
DQM
R
DQ[24:31]
C
R = 10 Ω
RB = 5 Ω
RC = 10 Ω
C = 10 pF
8
DQ[0:7]
SPD EEPROM
SCL
WP
47 kΩ
LEGEND: CS = Chip Select
SPD = Serial Presence Detect
SDA
A0
A1
A2
SA0
SA1
SA2
† Additional 3.3 pF capacity is used to balance loads among clocks.
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7
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
TM4TR72EPH functional block diagram
S1
VDD
S0
CS
CS
CS
U[0:8], UB[0:8]
Two 0.1 µF per
SDRAM device
CS
VSS
U0
DQMB0
DQM
R
DQ[0:7]
8
DQ[0:7]
U1
R
DQ[8:15]
8
U4
DQMB4
DQM
R
CS
DQMB1
UB0
DQ[0:7]
DQ[32:39]
8
CS
DQM
DQM
DQ[0:7]
DQ[0:7]
CS
UB1
DQM
DQM
DQ[0:7]
DQ[0:7]
U5
DQMB5
R
DQ[40:47]
8
U[0:8], UB[0:8]
UB4
R = 10 Ω
RC = 10 Ω
RB = 5 Ω
CS
RB
UB5
DQM
DQM
DQ[0:7]
DQ[0:7]
CK: U0, U4
RB
CK0
CK: U1, U5, U8
RB
CK: UB0, UB4
RB
CK1
CS
CK: UB1, UB5, UB8
CS
RC
U8
DQMB1
UB8
DQM
R
CB[0:7]
8
CK2†
DQM
DQ[0:7]
CK: U2, U6
RC
CK: U3, U7
RC
DQ[0:7]
CK3†
CK: UB2, UB6
RC
CK: UB3, UB7
S3
VDD
S2
CS
U2
DQMB2
R
DQ[16:23]
8
CS
CS
UB2
DQM
DQM
DQ[0:7]
DQ[0:7]
U6
DQMB6
R
CS
DQ[48:55]
8
UB6
DQM
DQM
DQ[0:7]
DQ[0:7]
CS
CS
10 kΩ
CS
CKE1
CKE: UB[0:8]
CKE0
CKE: U[0:8]
RAS
RAS: U[0:8], UB[0:8]
CAS
CAS: U[0:8], UB[0:8]
WE
WE: U[0:8], UB[0:8]
CS
A[0:11]
U3
DQMB3
DQM
R
DQ[24:31]
LEGEND: CS =
SPD =
8
DQ[0:7]
U7
UB3
DQMB7
DQM
R
DQ[0:7]
DQ[56:63]
8
DQM
DQM
DQ[0:7]
DQ[0:7]
47 kΩ
† Additional 3.3 pF capacity is used to balance loads among clocks.
8
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SPD EEPROM
SCL
WP
Chip select
Serial Presence Detect
• HOUSTON, TEXAS 77251−1443
A[0:11]: U[0:8], UB[0:8]
UB7
SDA
A0
A1
A2
SA0 SA1 SA2
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
absolute maximum ratings over operating ambient temperature range (unless otherwise noted)†
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.5 V to 4.6 V
Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Power dissipation: TM2TR64EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W
TM4TR64EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W
TM2TR72EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 W
TM4TR72EPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 W
Operating ambient temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions‡
VDD
VSS
Supply voltage
VIH
VIH-SPD
High-level input voltage
MIN
NOM
MAX
UNIT
3
3.3
3.6
V
Supply voltage
0
2
High-level input voltage for the SPD device
0.7*VDD
−0.3
VIL
Low-level input voltage
TA
Operating ambient temperature
‡ The overshoot and undershoot voltage duration is less than or equal to 3 ns with no input clamp diode.
V
VDD + 0.3
VDD + 0.5
0
V
V
0.8
V
70
°C
capacitance over recommended ranges of supply voltage and ambient temperature,
f = 1 MHz (see Note 2)§
TMxTRxxEPH
PARAMETER
MIN
MAX
UNIT
Ci(CK)
Input capacitance, CK input
2.5
4
pF
Ci(AC)
Input capacitance, address and control inputs: A0 −A11, RAS, CAS, WE
2.5
5
pF
Ci(CKE)
Input capacitance, CKE input
5
pF
Co
Output capacitance
4
6.5
pF
Ci(DQMBx)
Input capacitance, DQMBx input
2.5
5
pF
Ci(Sx)
Input capacitance, Sx input
2.5
5
pF
Ci/o(SDA)
Input/output capacitance, SDA input
9
pF
7
pF
Ci(SPD)
Input capacitance, SA0, SA1, SA2, SCL inputs
§ Specifications in this table represent a single SDRAM device.
NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.
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9
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
electrical characteristics over recommended ranges of supply voltage and operating ambient
temperature (unless otherwise noted) (see Note 3)†
’xTRxxEPH-8
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
IOH = − 4 mA
IOL = 4 mA
"10
µA
"10
"10
µA
95
95
100
100
CKE ≤ VIL MAX, tCK = 15 ns (see Note 6)
1
1
CKE and CK ≤ VIL MAX, tCK = ∞ (see Note 7)
1
1
CKE ≥ VIH MIN, tCK = 15 ns (see Note 6)
30
30
CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞
(see Note 7)
2
2
CKE ≤ VIL MAX, tCK = 15 ns (see Notes 3 and 6)
3
3
CKE and CK ≤ VIL MAX, tCK = ∞
(see Notes 3 and 7)
3
3
CKE ≥ VIH MIN, tCK = 15 ns (see Notes 3 and 6)
40
40
CKE ≥ VIH MIN, CK ≤ VIL MAX, tCK = ∞
(see Notes 3 and 7)
10
10
Page burst, IOH/IOL = 0 mA CAS latency = 2
All banks activated,
nCCD = one cycle
CAS latency = 3
(see Notes 8 and 9)
140
140
150
150
CAS latency = 2
90
90
CAS latency = 3
95
95
0.4
0.4
0 V ≤ VO ≤ VDD, Output disabled
Operating current
Burst length = 1,
CAS latency = 2
tRC ≥ tRC MIN
IOH/IOL = 0 mA, one bank
activated
CAS latency = 3
(see Notes 3, 4, and 5)
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
ICC5
Active standby current in
power-down mode
Active standby current in
non-power-down mode
Burst current
Auto-refresh current
tRC ≤ tRC MIN (see Note 7)
ICC6
Self-refresh current
CKE ≤ VIL MAX
† Specifications in this table represent a single SDRAM device.
NOTES: 3. Only one bank is activated.
4. tRC = MIN
5. Control, DQ, and address inputs change state only twice during tRC.
6. Control, DQ, and address inputs change state only once every 30 ns.
7. Control, DQ, and address inputs do not change state (stable).
8. Control, DQ, and address inputs change state only once every cycle.
9. Continuous burst access, nCCD = 1 cycle.
10
V
"10
Output current (leakage)
Precharge standby current in
non-power-down mode
2.4
UNIT
V
IO
ICC2N
MAX
0.4
Input current (leakage)
Precharge standby current in
power-down mode
MIN
0.4
II
ICC2P
ICC2PS
’xTRxxEPH-8A
MAX
2.4
0 V ≤ VI ≤ VDD + 0.3 V,
All other pins = 0 V to VDD
ICC1
MIN
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
mA
mA
mA
mA
mA
mA
mA
mA
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
ac timing requirements† ‡§
’xTRxxEPH-8
MIN
’xTRxxEPH-8A
MAX
MIN
MAX
UNIT
tCK2
tCK3
Cycle time, CLK, CAS latency = 2
10
15
ns
Cycle time, CLK, CAS latency = 3
8
8
ns
tCH
tCL
Pulse duration, CLK high
3
3
ns
Pulse duration, CLK low
3
tAC2
tAC3
Access time, CLK high to data out, CAS latency = 2 (see Note 10)
6
7.5
ns
Access time, CLK high to data out, CAS latency = 3 (see Note 10)
6
6
ns
tOH
tOHN
Hold time, CLK high to data out with 50-pF load
3
3
ns
Hold time, CLK high to data out with 0-pF load
2
2
ns
tLZ
tHZ
Delay time, CLK high to DQ in low-impedance state (see Note 11)
1
tIS
tIH
Setup time, address, control, and data input
2
2
ns
Hold time, address, control, and data input
1
1
ns
tCESP
tRAS
Power-down/self-refresh exit time
8
8
Delay time, ACTV command to DEAC or DCAB command
48
tRC
Delay time, ACTV, REFR, or SLFR exit to ACTV, MRS, REFR, or SLFR command
68
68
ns
tRCD
Delay time, ACTV command to READ, READ-P, WRT, or WRT-P command
(see Note 13)
20
20
ns
tRP
tRRD
Delay time, DEAC or DCAB command to ACTV, MRS, REFR, or SLFR command
20
20
ns
Delay time, ACTV command in one bank to ACTV command in the other bank
16
16
ns
tRSA
tAPR
Delay time, MRS command to ACTV, MRS, REFR, or SLFR command
16
16
ns
tAPW
Final data in of WRT-P operation to ACTV, MRS, SLFR, or REFR command
tT
tREF
Transition time (see Note 14)
nCCD
nCDD
Delay time, READ or WRT command to an interrupting command
1
Delay time, CS low or high to input enabled or disabled
0
0
0
0
cycle
nCLE
nCWL
Delay time, CKE high or low to CLK enabled or disabled
1
1
1
1
cycle
Delay time, final data in of WRT operation to READ, READ-P, WRT, WRT-P
1
nDID
nDOD
Delay time, ENBL or MASK command to enabled or masked data in
0
0
0
0
cycle
Delay time, ENBL or MASK command to enabled or masked data out
2
2
2
2
cycle
Delay time, CLK high to DQ in high-impedance state (see Note 12)
3
1
8
Final data out of READ-P operation to ACTV, MRS, SLFR, or REFR command
1
Refresh interval
ns
100 000
ns
8
48
ns
ns
100 000
ns
tRP − (CL −1) * tCK
ns
tRP + 1 tCK
ns
5
1
64
5
64
1
ns
ms
cycle
1
cycle
nHZP2
Delay time, DEAC or DCAB command to DQ in high-impedance state,
CAS latency = 2
2
2
cycle
nHZP3
Delay time, DEAC or DCAB command to DQ in high-impedance state,
CAS latency = 3
3
3
cycle
nWCD
Delay time, WRT command to first data in
0
cycle
0
0
0
nWR
Delay time, final data in of WRT operation to DEAC or DCAB command
1
1
cycle
† See Parameter Measurement Information for load circuits in the TMS626812B data sheet (literature number SMOS693).
‡ All references are made to the rising transition of CLK, unless otherwise noted.
§ Specifications in this table represent a single SDRAM device.
NOTES: 10. tAC is referenced from the rising transition of CLK that precedes the data-out cycle. For example, the first data-out tAC is referenced
from the rising transition of CLK0 that is CAS latency minus one cycle after the READ command. Access time is measured at output
reference level 1.4 V.
11. tLZ is measured from the rising transition of CLK that is CAS latency minus one cycle after the READ command.
12. tHZ MAX defines the time at which the outputs are no longer driven and is not referenced to output voltage levels.
13. For read or write operations with automatic deactivate, tRCD must be set to satisfy minimum tRAS.
14. Transition time, tT, is measured between VIH and VIL.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
11
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect
The serial presence detect (SPD) is contained in a 256-byte serial EEPROM located on the module. The SPD
nonvolatile EEPROM contains various data such as module configuration, SDRAM organization, and timing
parameters (see Table 1 − Table 4). Only the first 128 bytes are programmed by Texas Instruments, while the
remaining 128 bytes are available for customer use. Programming is done through an IIC bus using the clock
(SCL) and data (SDA) signals. All Texas Instruments modules comply with the current JEDEC SPD Standard.
See the Texas Instruments Serial Presence Detect Technical Reference (literature number SMMU001) for
further details.
SPD contents of each TMxTRxxEPH device are listed in the following tables:
Table 1 − TM2TR64EPH
Table 3 − TM2TR72EPH
Table 2 − TM4TR64EPH
Table 4 − TM4TR72EPH
Table 1. Serial Presence Detect Data for the TM2TR64EPH
TM2TR64EPH-8
BYTE
NO.
TM2TR64EPH-8A
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into serial memory
during module manufacturing
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
SDRAM
04h
3
Number of row addresses on this assembly
11
0Bh
11
0Bh
4
Number of column addresses on this assembly
9
09h
9
09h
5
Number of module rows on this assembly
1 bank
01h
1 bank
01h
6
Data width of this assembly
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this assembly
LVTTL
01h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
tCK = 8 ns
80h
tCK = 8 ns
80h
10
SDRAM access from clock at CL = X
tAC = 6 ns
60h
tAC = 6 ns
60h
11
DIMM configuration type (non-parity, parity, error
correcting code [ECC])
Non-Parity
00h
Non-Parity
00h
12
Refresh rate / type
15.6 µs/
self-refresh
80h
15.6 µs/
self-refresh
80h
13
SDRAM width, primary DRAM
x8
08h
x8
08h
14
Error-checking SDRAM data width
N/A
00h
N/A
00h
15
Minimum clock delay, back-to-back random column
addresses
1 CK cycle
01h
1 CK cycle
01h
16
Burst lengths supported
1, 2, 4, 8
0Fh
1, 2, 4, 8
0Fh
17
Number of banks on each SDRAM device
2 banks
02h
2 banks
02h
18
CAS latencies supported
2, 3
06h
2, 3
06h
19
CS latency
0
01h
0
01h
20
Write latency
0
01h
0
01h
00h
Non-buffered/
Non-registered
00h
VDD tolerance =
(+10%)
precharge all,
auto precharge
0Eh
VDD tolerance =
(+10%),
Burst read / write,
precharge all,
auto precharge
0Eh
tCK = 10 ns
A0h
tCK = 15 ns
F0h
21
12
DESCRIPTION OF FUNCTION
00h
Non-buffered/
Non-registered
SDRAM module attributes
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
00h
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 1. Serial Presence Detect Data for the TM2TR64EPH (Continued)
TM2TR64EPH-8
BYTE
NO.
DESCRIPTION OF FUNCTION
24
Maximum data-access time from clock at CL = X − 1
25
Minimum clock cycle time at CL = X − 2
26
Maximum data-access time from clock at CL = X − 2
27
Minimum row-precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
31
Density of each bank on module
32
Command and address signal input setup time
33
Command and address signal input hold time
34
35
36−61
TM2TR64EPH-8A
ITEM
DATA
ITEM
DATA
tAC = 6 ns
N/A
60h
75h
00h
tAC = 7.5 ns
N/A
N/A
00h
N/A
00h
tRP = 20 ns
tRRD = 16 ns
tRCD = 20 ns
14h
tRP = 20 ns
tRRD = 16 ns
tRCD = 20 ns
14h
tRAS = 48 ns
16M Bytes
30h
tRAS = 48 ns
16M Bytes
30h
20h
20h
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
20h
Data signal input setup time
tIS = 2 ns
tIH = 1 ns
tIS = 2 ns
Data signal input hold time
tIH = 1 ns
10h
tIH = 1 ns
10h
Rev. 1.2
12h
Rev. 1.2
12h
10h
14h
04h
10h
00h
10h
14h
04h
10h
20h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
80
50h
181
B5h
97h
9700...00h
97h
9700...00h
72
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
73
Manufacturer’s part number
T
54h
T
54h
74
Manufacturer’s part number
M
4Dh
M
4Dh
75
Manufacturer’s part number
2
32h
2
32h
76
Manufacturer’s part number
T
54h
T
54h
77
Manufacturer’s part number
R
52h
R
52h
78
Manufacturer’s part number
6
36h
6
36h
79
Manufacturer’s part number
4
34h
4
34h
80
Manufacturer’s part number
E
45h
E
45h
81
Manufacturer’s part number
P
50h
P
50h
82
Manufacturer’s part number
H
4Eh
H
4Eh
83
Manufacturer’s part number
−
2Dh
−
2Dh
84
Manufacturer’s part number
8
38h
8
38h
85
Manufacturer’s part number
SPACE
20h
A
41h
86−90
Manufacturer’s part number
Die revision code†
SPACE
20h
SPACE
20h
64 −71
91
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
99−125
Manufacturer-specific data†
TBD
92
126
Clock frequency
127
SDRAM component and clock interconnection details
System-integrator-specific data‡
128−166
TBD
100 MHz
64h
199
C7h
TBD
100 MHz
64h
199
C7h
TBD
167−255 Open
† TBD indicates values that are determined at manufacturing time and are module-dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
13
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM4TR64EPH
TM4TR64EPH-8
BYTE
NO.
TM4TR64EPH-8A
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into serial memory during
module manufacturing
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
SDRAM
04h
3
Number of row addresses on this assembly
11
0Bh
11
0Bh
4
Number of column addresses on this assembly
9
09h
9
09h
5
Number of module rows on this assembly
2 banks
02h
2 banks
02h
6
Data width of this assembly
64 bits
40h
64 bits
40h
7
Data width continuation
8
Voltage interface standard of this assembly
LVTTL
01h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
tCK = 8 ns
80h
tCK = 8 ns
80h
10
SDRAM access from clock at CL = X
tAC = 6 ns
60h
tAC = 6 ns
60h
11
DIMM configuration type (non-parity, parity, error correcting
code [ECC])
Non-Parity
00h
Non-Parity
00h
12
Refresh rate / type
15.6 µs/
self-refresh
80h
15.6 µs/
self-refresh
80h
13
SDRAM width, primary DRAM
14
Error-checking SDRAM data width
15
Minimum clock delay, back-to-back random column
addresses
16
00h
00h
x8
08h
x8
08h
N/A
00h
N/A
00h
1 CK cycle
01h
1 CK cycle
01h
Burst lengths supported
1, 2, 4, 8
0Fh
1, 2, 4, 8
0Fh
17
Number of banks on each SDRAM device
2 banks
02h
2 banks
02h
18
CAS latencies supported
2, 3
06h
2, 3
06h
19
CS latency
0
01h
0
01h
20
Write latency
0
01h
0
01h
00h
Non-buffered/
Non-registered
00h
0Eh
VDD tolerance =
(+10%),
Burst read / write,
precharge all,
auto precharge
0Eh
21
14
DESCRIPTION OF FUNCTION
Non-buffered/
Non-registered
SDRAM module attributes
VDD tolerance =
(+10%)
Burst read / write,
precharge all,
auto precharge
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
24
Maximum data-access time from clock at CL = X − 1
25
26
tCK = 10 ns
tAC = 6 ns
A0h
Minimum clock cycle time at CL = X − 2
N/A
Maximum data-access time from clock at CL = X − 2
N/A
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
F0h
00h
tCK = 15 ns
tAC = 7.5 ns
N/A
00h
N/A
00h
60h
75h
00h
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 2. Serial Presence Detect Data for the TM4TR64EPH (Continued)
BYTE
NO.
TM4TR64EPH-8
DESCRIPTION OF FUNCTION
TM4TR64EPH-8A
ITEM
DATA
ITEM
DATA
tRP = 20 ns
tRRD = 16 ns
14h
tRP = 20 ns
tRRD = 16 ns
14h
tRCD = 20 ns
tRAS = 48 ns
14h
14h
27
Minimum row-precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
30h
tRCD = 20 ns
tRAS = 48 ns
31
Density of each bank on module
16M Bytes
04h
16M Bytes
04h
32
Command and address signal input setup time
20h
Command and address signal input hold time
tIS = 2 ns
tIH = 1 ns
20h
33
tIS = 2 ns
tIH = 1 ns
34
Data signal input setup time
20h
Data signal input hold time
10h
tIS = 2 ns
tIH = 1 ns
20h
35
tIS = 2 ns
tIH = 1 ns
Rev. 1.2
12h
Rev. 1.2
12h
36−61
10h
10h
10h
30h
10h
10h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
81
51h
182
B6h
97h
9700...00h
97h
9700...00h
72
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
73
Manufacturer’s part number
T
54h
T
54h
74
Manufacturer’s part number
M
4Dh
M
4Dh
75
Manufacturer’s part number
4
34h
4
34h
76
Manufacturer’s part number
T
54h
T
54h
77
Manufacturer’s part number
R
52h
R
52h
78
Manufacturer’s part number
6
36h
6
36h
79
Manufacturer’s part number
4
34h
4
34h
80
Manufacturer’s part number
E
45h
E
45h
81
Manufacturer’s part number
P
50h
P
50h
82
Manufacturer’s part number
H
4Eh
H
4Eh
83
Manufacturer’s part number
−
2Dh
−
2Dh
84
Manufacturer’s part number
8
38h
8
38h
85
Manufacturer’s part number
SPACE
20h
A
41h
86−90
Manufacturer’s part number
Die revision code†
SPACE
20h
SPACE
20h
64 −71
91
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
99−125
Manufacturer-specific data†
92
TBD
126
Clock frequency
127
SDRAM component and clock interconnection details
System-integrator-specific data‡
128−166
TBD
100 MHz
64h
247
F7h
TBD
100 MHz
64h
247
F7h
TBD
167−255 Open
† TBD indicates values that are determined at manufacturing time and are module-dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
15
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 3. Serial Presence Detect Data for the TM2TR72EPH
TM2TR72EPH-8
BYTE
NO.
TM2TR72EPH-8A
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into serial memory during
module manufacturing
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
SDRAM
04h
3
Number of row addresses on this assembly
11
0Bh
11
0Bh
4
Number of column addresses on this assembly
9
09h
9
09h
5
Number of module rows on this assembly
1 bank
01h
1 bank
01h
6
Data width of this assembly
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this assembly
LVTTL
01h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
tCK = 8 ns
80h
tCK = 8 ns
80h
10
SDRAM access from clock at CL = X
tAC = 6 ns
60h
tAC = 6 ns
60h
11
DIMM configuration type (non-parity, parity, error correcting
code [ECC])
ECC
02h
ECC
02h
12
Refresh rate / type
15.6 µs/
self-refresh
80h
15.6 µs/
self-refresh
80h
13
SDRAM width, primary DRAM
x8
08h
x8
08h
14
Error-checking SDRAM data width
x8
08h
x8
08h
15
Minimum clock delay, back-to-back random column
addresses
1 CK cycle
01h
1 CK cycle
01h
16
Burst lengths supported
1, 2, 4, 8
0Fh
1, 2, 4, 8
0Fh
17
Number of banks on each SDRAM device
2 banks
02h
2 banks
02h
18
CAS latencies supported
2, 3
06h
2, 3
06h
19
CS latency
0
01h
0
01h
20
Write latency
0
01h
0
01h
00h
Non-buffered/
Non-registered
00h
0Eh
VDD tolerance =
(+10%) ,
Burst read / write,
precharge all,
auto precharge
0Eh
21
16
DESCRIPTION OF FUNCTION
00h
Non-buffered/
Non-registered
SDRAM module attributes
VDD tolerance =
(+10%)
Burst read / write,
precharge all,
auto precharge
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
24
Maximum data-access time from clock at CL = X − 1
POST OFFICE BOX 1443
tCK = 10 ns
tAC = 6.0 ns
• HOUSTON, TEXAS 77251−1443
A0h
60h
00h
tCK = 15 ns
tAC = 7.5 ns
F0h
75h
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 3. Serial Presence Detect Data for the TM2TR72EPH (Continued)
BYTE
NO.
TM2TR72EPH-8
DESCRIPTION OF FUNCTION
25
Minimum clock cycle time at CL = X − 2
26
Maximum data-access time from clock at CL = X − 2
27
Minimum row-precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
31
Density of each bank on module
32
Command and address signal input setup time
33
Command and address signal input hold time
34
Data signal input setup time
35
Data signal input hold time
36−61
TM2TR72EPH-8A
ITEM
DATA
ITEM
DATA
N/A
00h
N/A
00h
N/A
00h
N/A
00h
tRP = 20 ns
14h
tRP = 20 ns
14h
tRRD = 16 ns
tRCD = 20 ns
10h
tRRD = 16 ns
tRCD = 20 ns
10h
tRAS = 48 ns
16M Bytes
30h
tRAS = 48 ns
16M Bytes
30h
tIS = 2 ns
tIH = 1 ns
20h
tIS = 2 ns
tIH = 1 ns
20h
tIS = 2 ns
tIH = 1 ns
20h
20h
10h
tIS = 2 ns
tIH = 1 ns
Rev. 1.2
12h
Rev. 1.2
12h
14h
04h
10h
14h
04h
10h
10h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
98
62h
199
C7h
97h
9700...00h
97h
9700...00h
72
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
73
Manufacturer’s part number
T
54h
T
54h
74
Manufacturer’s part number
M
4Dh
M
4Dh
75
Manufacturer’s part number
2
32h
2
32h
76
Manufacturer’s part number
T
54h
T
54h
77
Manufacturer’s part number
R
52h
R
52h
78
Manufacturer’s part number
7
37h
7
37h
79
Manufacturer’s part number
2
32h
2
32h
80
Manufacturer’s part number
E
45h
E
45h
81
Manufacturer’s part number
P
50h
P
50h
82
Manufacturer’s part number
H
4Eh
H
4Eh
83
Manufacturer’s part number
−
2Dh
−
2Dh
84
Manufacturer’s part number
8
38h
8
38h
85
Manufacturer’s part number
SPACE
20h
A
41h
86−90
Manufacturer’s part number
Die revision code†
SPACE
20h
SPACE
20h
64 −71
91
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
99−125
Manufacturer-specific data†
TBD
92
126
Clock frequency
127
SDRAM component and clock interconnection details
System-integrator-specific data ‡
128−166
TBD
100 MHz
64h
199
C7h
TBD
100 MHz
64h
199
C7h
TBD
167−255 Open
† TBD indicates values that are determined at manufacturing time and are module-dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
17
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 4. Serial Presence Detect Data for the TM4TR72EPH
TM4TR72EPH-8
BYTE
NO.
TM4TR72EPH-8A
ITEM
DATA
ITEM
DATA
0
Defines number of bytes written into serial memory during
module manufacturing
128 bytes
80h
128 bytes
80h
1
Total number of bytes of SPD memory device
256 bytes
08h
256 bytes
08h
2
Fundamental memory type (FPM, EDO, SDRAM, . . .)
SDRAM
04h
SDRAM
04h
3
Number of row addresses on this assembly
11
0Bh
11
0Bh
4
Number of column addresses on this assembly
9
09h
9
09h
5
Number of module rows on this assembly
2 banks
02h
2 banks
02h
6
Data width of this assembly
72 bits
48h
72 bits
48h
7
Data width continuation
8
Voltage interface standard of this assembly
LVTTL
01h
LVTTL
01h
9
SDRAM cycle time at maximum supported CAS latency
(CL), CL = X
tCK = 8 ns
80h
tCK = 8 ns
80h
10
SDRAM access from clock at CL = X
tAC = 6 ns
60h
tAC = 6 ns
60h
11
DIMM configuration type (non-parity, parity, error correcting
code [ECC])
ECC
02h
ECC
02h
12
Refresh rate / type
15.6 µs/
self-refresh
80h
15.6 µs/
self-refresh
80h
13
SDRAM width, primary DRAM
x8
08h
x8
08h
14
Error-checking SDRAM data width
x8
08h
x8
08h
15
Minimum clock delay, back-to-back random column
addresses
1 CK cycle
01h
1 CK cycle
01h
16
Burst lengths supported
1, 2, 4, 8
0Fh
1, 2, 4, 8
0Fh
17
Number of banks on each SDRAM device
2 banks
02h
2 banks
02h
18
CAS latencies supported
2, 3
06h
2, 3
06h
19
CS latency
0
01h
0
01h
20
Write latency
0
01h
0
01h
00h
Non-buffered/
Non-registered
00h
0Eh
VDD tolerance =
(+10%) ,
Burst read / write,
precharge all,
auto precharge
0Eh
21
18
DESCRIPTION OF FUNCTION
00h
Non-buffered/
Non-registered
SDRAM module attributes
VDD tolerance =
(+10%)
Burst read / write,
precharge all,
auto precharge
22
SDRAM device attributes: general
23
Minimum clock cycle time at CL = X − 1
24
Maximum data-access time from clock at CL = X − 1
25
Minimum clock cycle time at CL = X − 2
26
Maximum data-access time from clock at CL = X − 2
27
Minimum row-precharge time
28
Minimum row-active to row-active delay
29
Minimum RAS-to-CAS delay
30
Minimum RAS pulse width
31
Density of each bank on module
POST OFFICE BOX 1443
tCK = 10 ns
tAC = 6.0 ns
N/A
A0h
N/A
00h
F0h
00h
tCK = 15 ns
tAC = 7.5 ns
N/A
00h
N/A
00h
tRP = 20 ns
tRRD = 16 ns
14h
tRP = 20 ns
tRRD = 16 ns
14h
tRCD = 20 ns
tRAS = 48 ns
14h
14h
30h
tRCD = 20 ns
tRAS = 48 ns
16M Bytes
04h
16M Bytes
04h
• HOUSTON, TEXAS 77251−1443
60h
10h
75h
00h
10h
30h
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
serial presence detect (continued)
Table 4. Serial Presence Detect Data for the TM4TR72EPH (Continued)
BYTE
NO.
TM4TR72EPH-8
DESCRIPTION OF FUNCTION
32
Command and address signal input setup time
33
Command and address signal input hold time
34
Data signal input setup time
35
Data signal input hold time
36 −61
TM4TR72EPH-8A
ITEM
DATA
ITEM
DATA
tIS = 2 ns
tIH = 1 ns
20h
tIS = 2 ns
tIH = 1 ns
20h
tIS = 2 ns
tIH = 1 ns
20h
20h
10h
tIS = 2 ns
tIH = 1 ns
Rev. 1.2
12h
Rev. 1.2
12h
10h
10h
10h
Superset features (may be used in the future)
62
SPD revision
63
Checksum for byte 0 −62
99
63h
200
C8h
97h
9700...00h
97h
9700...00h
72
Manufacturer’s JEDEC ID code per JEP −106E
Manufacturing location†
73
Manufacturer’s part number
T
54h
T
54h
74
Manufacturer’s part number
M
4Dh
M
4Dh
75
Manufacturer’s part number
4
34h
4
34h
76
Manufacturer’s part number
T
54h
T
54h
77
Manufacturer’s part number
R
52h
R
52h
78
Manufacturer’s part number
7
37h
7
37h
79
Manufacturer’s part number
2
32h
2
32h
80
Manufacturer’s part number
E
45h
E
45h
81
Manufacturer’s part number
P
50h
P
50h
82
Manufacturer’s part number
H
4Eh
H
4Eh
83
Manufacturer’s part number
−
2Dh
−
2Dh
84
Manufacturer’s part number
8
38h
8
38h
85
Manufacturer’s part number
SPACE
20h
A
41h
86−90
Manufacturer’s part number
Die revision code†
SPACE
20h
SPACE
20h
64 −71
91
TBD
TBD
TBD
TBD
TBD
TBD
93−94
PCB revision code†
Manufacturing date†
TBD
TBD
95−98
Assembly serial number†
TBD
TBD
99−125
Manufacturer-specific data†
TBD
92
126
Clock frequency
127
SDRAM component and clock interconnection details
System-integrator-specific data‡
128−166
TBD
100 MHz
64h
247
F7h
TBD
100 MHz
64h
247
F7h
TBD
167−255 Open
† TBD indicates values that are determined at manufacturing time and are module-dependent.
‡ These TBD values are determined and programmed by the customer (optional).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
19
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
device symbolization (TM2TR64EPH illustrated)
TM2TR64EPH
-SS
Unbuffered Key Position
3.3-V Voltage Key Position
YY
MM
T
-SS
=
=
=
=
Year Code
Month Code
Assembly Site Code
Speed Code
NOTE A: Location of symbolization may vary.
20
YYMMT
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
SMMS702B − JANUARY 1998 − REVISED APRIL 1998
MECHANICAL DATA
BUV (R-PDIM-N168)
DUAL-IN-LINE MEMORY MODULE
5.255 (133,48)
5.245 (133,22)
(Note D)
Notch 0.250 (6,35) x 0.089 (2,26) Deep
2 Places
0.054 (1,37)
0.046 (1,17)
Notch 0.079 (2,00) x 0.122 (3,10) Deep
2 Places
Notch 0.157 (4,00) x 0.122 (3,10) Deep
2 Places
2 Places
0.050 (1,27)
0.039 (1,00) TYP
0.125 (3,18)
0.014 (0,35) MAX
0.118 (3,00) TYP
0.125 (3,18)
0.700 (17,78) TYP
0.118 (3,00) DIA (2 Places)
1.255 (31,88)
1.245 (31,62)
0.875 (22,23) 2 Places
0.106 (2,70) MAX
0.157 (4,00) MAX
(For Double Sided DIMM Only)
4088192/A 01/98
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Falls within JEDEC MO-161
Dimension includes depanelization variations; applies between notch and tab edge.
Outline may vary above notches to allow router/panelization irregularities.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
21
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