INTERGER RF/IF DUAL PLL
S1M8821/22/23
INTRODUCTION
20-TSSOP-BD44
The S1M8821/22/23 is a high performance dual frequency
synthesizer with integrated prescalers designed for RF operation up
to 1.2GHz/2.0GHz/2.5GHz and IF operation up to 520MHz.
The S1M8821/22/23 contains dual-modulus prescalers. The RF
synthesizer adopts a 64/65 or a 128/129 prescaler(32/33 or 64/65 for
the S1M8823) and the IF synthesizer adopts an 8/9 or a 16/17
prescaler.
Using a proprietary digital phase-locked-loop technique, the
S1M8821/22/23 has linear phase detector characteristic and can be
used for very stable, low noise local oscillator signal. Supply voltage
can range from 2.7V to 4.0V. The S1M8821/22/23 is now available in
a 20-TSSOP/24-QFN package.
24-QFN-3.5×4.5
FEATURES
•
High operating frequency dual synthesizer
— S1M8821 : 0.1 to 1.2GHz (RF)/ 45 to 520MHz (IF)
— S1M8822 : 0.2 to 2.0GHz (RF)/ 45 to 520MHz (IF)
— S1M8823 : 0.5 to 2.5GHz (RF)/ 45 to 520MHz (IF)
•
Very low current consumption(8821:3.5mA, 22:4.5mA, 23:5.5mA)
•
Operating voltage range : 2.7 to 4.0V
•
Selectable power saving mode(Icc=1uA typical @3V)
•
Dual modulus prescaler :
S1M8821/22
S1M8823
S1M8821/22/23
(RF) 64/65 or 128/129
(RF) 32/33 or 64/65
(IF) 8/9 or 16/17
•
Programmability via serial bus interface
•
No dead-zone PFD
•
Variable charge pump output current
•
High speed lock mode
APPLICATIONS
•
Cellular telephone systems : S1M8821
•
Portable wireless communications : S1M8822 (PCS/PCN, cordless)
•
Wireless Local Area Networks (W-LANs) : S1M8823
•
Other wireless communication systems
1
S1M8821/22/23
INTERGER RF/IF DUAL PLL
ORDERING INFORMATION
2
Device
Package
Operating Temperature
S1M8821X01-R0T0
S1M8822X01-R0T0
S1M8823X01-R0T0
20-TSSOP-BD44
-40 to +85°C
S1M8821X01-R0T0
S1M8822X01-R0T0
S1M8823X01-R0T0
24-QFN-3.5×4.5
-40 to +85°C
INTERGER RF/IF DUAL PLL
S1M8821/22/23
BLOCK DIAGRAM
VDD1 1
RF
LD
VP1 2
RF
Charge
Pump
RF
Phase
Detector
foLD
Data Out
Multiplexer
IF
LD
20 VDD2
IF
Phase
Detector
19 VP2
IF
Charge
Pump
18 CPoIF
CPoRF 3
RF Prescaler
IF Prescaler
GND 4
17 GND
+
finRF 5
–
Prescaler
Control
RF
Programmable
Counter
IF
Programmable
Counter
Prescaler
Control
–
+
16 finIF
15 finIF
finRF 6
RF N-Latch
GND 7
IF N-Latch
20-bit Shift Register
OSCin 8
RF R-Latch
IF R-Latch
GND 9
RF Reference
Counter
IF Reference
Counter
foLD 10
2-bit
Control
14 GND
13 LE
12 DATA
11 CLOCK
NOTE: The pin numbers above are for 20-TSSOP package.
3
S1M8821/22/23
INTERGER RF/IF DUAL PLL
PIN CONFIGURATION
VDD1 1
20 VDD2
Vp1 2
19 Vp2
CPoRF 3
18 CPoIF
GND 4
(Digital)
17 GND
(Digital)
S1M8821
finRF 5
finRF 6
16 finIF
S1M8822
15 finIF
S1M8823
GND 7
(Analog)
14 GND
(Analog)
OSCin 8
13 LE
GND 9
(Digital)
12 DATA
foLD 10
11 CLOCK
20-TSSOP
20-Lead(0.173 Wide) Thin Shrink Small
Outline Package(20-TSSOP)
NOTES:
1. pin #9 = pin #17(internally connected).
2. Do not tie up Vp and VDD
: Vp is the source of digital noises. The power for analog part is supplied by VDD.
If Vp and VDD are tied together, noisy Vp corrupts the power source for the analog part.
4
INTERGER RF/IF DUAL PLL
S1M8821/22/23
PIN CONFIGURATION(24-QFN, NOT TO SCALE)
VDD1 VDD2 Vp2
N/C
1
Vp1
23
21
N/C
2
20
CPoIF
CPoRF
3
19
GND
(Digital)
GND
(Digital)
4
18
finIF
finRF
5
17
finIF
finRF
6
16
GND 7
(Analog)
15
LE
OSCin
8
14
DATA
N/C
9
13
N/C
24
22
S1M8821
S1M8822
S1M8823
10
11
12
GND
(Analog)
* N/C pins must be connected
to GND(to Analog GND if
possible).
GND foLD CLOCK
(Digital)
24-QFN
24 PIN Quad Flat Non-leaded
(24-QFN) Package
NOTES:
1 pin #10 = pin #19(internally connected).
2. Do not tie up Vp and VDD
: Vp is the source of digital noises. The power for analog part is supplied by VDD. If Vp and VDD are tied together,
noisy Vp corrupts the power source for the analog part.
5
S1M8821/22/23
INTERGER RF/IF DUAL PLL
PIN DESCRIPTION
Pin No
(20TSSOP)
Pin No
(24QFN)
Symbol
I/O
Description
1
24
VDD1
-
Power supply voltage input for the RF PLL part. VDD1 must
equal VDD2. In order to reject supply noise, bypass capacitors
must be placed as close as possible to this pin and be
connected directly to the ground plane.
-
1
-
N/C
2
2
Vp1
-
Power supply voltage input for RF charge pump( ≥ VDD1).
3
3
CPoRF
O
Internal RF charge pump output for connection to an external
loop filter whose filtered output drives an external VCO.
4
4
GND
-
Ground for RF digital blocks.
5
5
finRF
I
RF prescaler input. The signal comes from the external VCO.
6
6
finRF
I
The complementary input of the RF prescaler. A bypass
capacitor must be placed as close as possible to this pin and
be connected directly to the ground plane. The bypass
capacitor is optional with some loss of sensitivity.
7
7
GND
-
Ground for RF analog blocks.
8
8
OSCin
I
Reference counter input. TCXO is connected via a coupling
capacitor.
-
9
-
N/C
9
10
GND
-
Ground for IF digital blocks.
10
11
foLD
O
Multiplexed output of the RF/IF programmable counters, the
reference counters, the lock detect signals and the shift
registers. The output level is CMOS level. (see fout
Programmable Truth Table)
11
12
CLOCK
I
CMOS clock input. Serial data for the various counters is
transferred into the 22-bit shift register on the rising edge of
the clock signal.
-
13
-
N/C
12
14
DATA
I
Binary serial data input. The MSB of CMOS input data is
entered first. The control bits are on the last two bits. CMOS
input.
13
15
LE
I
Load enable CMOS input. When LE becomes high, the data
in the shift register is loaded into one of the four latches (by
the control bits).
14
16
GND
-
Ground for IF analog blocks.
6
No connection.
No connection.
No connection.
INTERGER RF/IF DUAL PLL
S1M8821/22/23
PIN DESCRIPTION (Continued)
Pin No
(20TSSOP)
Pin No
(24QFN)
Symbol
I/O
Description
15
17
finIF
I
The complementary input of the IF prescaler. A bypass
capacitor must be placed as close as possible to this pin and
be connected directly to the ground plane. The bypass
capacitor is optional with some loss of sensitivity.
16
18
finIF
I
IF prescaler input. The signal comes from the external VCO.
17
19
GND
-
Ground for IF digital blocks.
18
20
CPoIF
O
Internal IF charge pump output for connection to an external
loop filter whose filtered output drives an external VCO.
-
21
-
N/C
19
22
Vp2
-
Power supply voltage input for IF charge pump( ≥ VDD2)
20
23
VDD2
-
Power supply voltage input for the IF PLL part. VDD1 must
equal VDD2. In order to reject supply noise, bypass capacitors
must be placed as close as possible to this pin and be
connected directly to the ground plane.
No connection.
7
S1M8821/22/23
INTERGER RF/IF DUAL PLL
EQUIVALENT CIRCUIT DIAGRAM
CLOCK, DATA, LE
foLD
OSCin
CPoRF, CPoIF
finRF, finRF, finIF, finIF
finRF,
finIF
finRF,
finIF
Vbias
8
INTERGER RF/IF DUAL PLL
S1M8821/22/23
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
Power Supply Voltage
VDD
0 to 4.0
V
Power Dissipation
PD
600
mW
Operating Temperature
Ta
-40 to +85oC
°C
TSTG
-65 to +150oC
°C
Pin No.
ESD level
Unit
Human Body Model
All
< ± 2000
V
Machine Model
All
< ± 300
V
Charged Device Model
All
< ± 800
V
Storage Temperature
ELECTROSTATIC CHARACTERISTICS
Characteristic
These devices are ESD sensitive. These devices must be handled in the ESD protected environment.
9
S1M8821/22/23
INTERGER RF/IF DUAL PLL
ELECTRICAL CHARACTERISTICS
(VDD=3.0V, VP=3.0V, Ta = 25°C, Unless otherwise specified)
Characteristic
Symbol
Power Supply Voltage
Power
Supply
Current
Test Conditions
Min.
Typ.
Max.
VDD
2.7
3.0
4.0
VP
VDD
3.0
4.0
V
S1M8823 RF + IF
5.5
S1M8823 RF Only
4.0
S1M8822 RF + IF
4.5
S1M8822 RF Only
IDD
VDD=2.7V to 4.0V
3.0
S1M8821 RF + IF
3.5
S1M8821 RF Only
2.0
S1M882x IF Only
1.5
Power down Current
IPWDN
Unit
VDD=3.0V
1.0
mA
10
µA
Digital inputs : CLOCK, DATA and LE
High-Level Input Voltage
VIH
VDD=2.7V to 4.0V
Low-Level Input Voltage
VIL
VDD=2.7V to 4.0V
High-Level Input Current
IIH
VIH= VDD=4.0V
Low-Level Input Current
IIL
VIL=0V, VDD=4.0V
0.7VDD
V
0.3VDD
V
-1.0
+1.0
µA
-1.0
+1.0
µA
+100
µA
Reference Oscillator Input : OSCin
IIHR
VIH= VDD=4.0V
IILR
VIL=0V, VDD=4.0V
High Level Output Voltage
VOH
Iout = -500µA
Low Level Output Voltage
VOL
Iout = +500µA
Input Current
-100
µA
VDD-0.4
V
Digital Output : foLD
10
0.4
V
INTERGER RF/IF DUAL PLL
S1M8821/22/23
ELECTRICAL CHARACTERISTICS (Continued)
(VDD=3.0V, VP=3.0V, Ta = 25°C, Unless otherwise specified)
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Charge Pump Outputs : CPoRF, CPoIF
ICP-SRC
VCP=VP/2, ICPo=Low
-1.0
ICP-SINK
VCP=VP/2, ICPo=Low
+1.0
ICP-SRC
VCP=VP/2, ICPo=High
-4.0
ICP-SINK
VCP=VP/2, ICPo=High
+4.0
Charge Pump Leakage
Current
ICPL
0.5V ≤ VCP ≤ VP-0.5V
Output Current Sink vs.
Source Mismatch*
ICP-SINK
vs ICP-SRC
VCP=VP/2
3
Output Current Magnitude
Variation vs. Temperature**
ICP vs T
VCP=VP/2
10
Output Current Magnitude
Variation vs. Voltage***
ICP vs VCP
0.5V ≤ VCP ≤ VP-0.5V
10
Charge Pump Output
Current
mA
-2.5
+2.5
nA
10
%
%
15
%
Programmable Divider
S1M8823
Operating
Frequency
S1M8822
finRF
0.5
2.5
0.2
2.0
0.1
1.2
VDD=3.0V
45
520
VDD=3.0V
-15
0
VDD=4.0V
-10
0
VDD=2.7V to 4.0V
-10
0
dBm
10
MHz
40
MHz
VDD=2.7V to 4.0V
S1M8821
Operating Frequency
RF Input Sensitivity
IF Input Sensitivity
Phase Detector Frequency
finIF
PfinRF
PfinIF
GHz
MHz
dBm
fPD
Reference Divider
Operating Frequency
OSCin
5
Input Sensitivity
VOSCin
0.5
VPP
11
S1M8821/22/23
INTERGER RF/IF DUAL PLL
ELECTRICAL CHARACTERISTICS (Continued)
(VDD=3.0V, VP=3.0V, Ta = 25°C, Unless otherwise specified )
Characteristic
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
10
MHz
Serial Data Control
CLOCK Frequency
fCLOCK
CLOCK Pulse Width High
tCWH
50
ns
CLOCK Pulse Width Low
tCWL
50
ns
DATA Set Up Time to CLOCK
Risng Edge
tDS
50
ns
DATA Hold Time after CLOCK
Rising Edge
tDH
10
ns
LE Pulse Width
tLEW
50
ns
CLOCK Rising Edge to LE Rising
Edge
tCLE
50
ns
<For Charge Pump items>
Ia=Charge pump sink current at Vcp=Vp-∆V,
Ib=Charge pump sink current at Vcp=Vp/2,
Ic=Charge pump sink current at Vcp=∆V
Id=Charge pump source current at Vcp=Vp-∆V, Ie=Charge pump source current at Vcp=Vp/2,
If=Charge pump source current at Vcp=∆V
∆V=Voltage offset from positive(for sink current) and negative(for source current) points from which the charge pump currents
become flat.
* Output Current Sink vs. Source Mismatch = [| Ib|-|Ie|] / [0.5 * {| Ib|+|Ie|}] * 100 (%)
** Output Current Magnitude Variation vs. Temperature =
[| Ib @any temp.| - |Ib @ 25οC|] / | Ib @ 25οC| * 100 (%)
and [|Ie @any temp.| - |Ie @ 25οC|] / |Ie @ 25οC| * 100 (%)
*** Output Current Magnitude Variation vs. Voltage =
[0.5 * {|Ia|-|Ic|}] / [0.5 * {|Ia|+|Ic|}] * 100 (%) and [0.5 * {|Id|-|If|}] / [0.5 * {|Id|+|If|}] * 100 (%)
12
INTERGER RF/IF DUAL PLL
S1M8821/22/23
FUNCTIONAL DESCRIPTION
The Samsung S1M8821/22/23 are dual PLL frequency synthesizer ICs. S1M8821/22/23 combined with external
LPFs and external VCOs form PLL frequency synthesizers. They include serial data control, R counter, N counter,
prescaler, phase detector, charge pump, and etc.
Serial data is moved into 20-bit shift register on the rising edge of the clock. These data enters MSB first. When LE
becomes HIGH, data in the shift register is moved into one of the 4 latches(by the 2-bit control). The divide ratios of
the prescaler and the counters are determined by the data stored in the latches. The external VCO output signal is
divided by the prescaler and the N counter. External reference signal is divided by the R counter. These two signals
are the two input signals to the phase detector. The phase detector drives the charge pump by comparing
frequencies and phases of the above two signals. The charge pump and the external LPF make the control voltage
for the external VCO and finally the VCO generates the appropriate frequency signal.
Serial Data Input Timing
MSB
DATA N20(R20)
LSB
N19(R19)
N10(R10)
N9(R9)
C2
C1
CLOCK
tCWL
tDS
tLEW
tCWH
LE
tDH
tCLE
13
S1M8821/22/23
INTERGER RF/IF DUAL PLL
PROGRAMMING DESCRIPTION
Control Bits
Control Bits
DATA Location
C1
C2
0
0
IF R Counter
0
1
RF R Counter
1
0
IF N Counter
1
1
RF N Counter
Programmable Reference Counter(IF / RF R Counter)
If the Control Bits are 00(IF) or 01(RF), data is moved from the 20-bit shift register into the R-latch which sets the
reference counter. Serial data format is shown in the table below.
LSB
C1
MSB
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C2
Division Ratio of the R Counter, R
Control Bits
•
Program Modes
15-Bit Programmable Reference Counter Ratio
Division
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Ratio
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
²
²
²
²
²
²
²
²
²
²
²
²
²
²
²
²
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Division ratio : 3 to 32767
Data are shifted in MSB first
14
INTERGER RF/IF DUAL PLL
S1M8821/22/23
Programmable Counter(N Counter)
If the Control Bits are 10(IF) or 11(RF), data is transferred from the 20-bit shift register into the N-latch. N Counter
consists of 7-bit swallow counter(A counter) and 11-bit main counter(B counter). Serial data format is shown below.
LSB
C1
MSB
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
C2
Division Ratio of the N Counter, N
Control Bits
•
Program Modes
7-Bit Swallow Counter Division Ratio(A Counter)
RF
IF
Division
N
N
N
N
N
N
N
Division
N
N
N
N
N
N
N
Ratio(A)
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Ratio(A)
0
7
X
6
X
5
X
4
0
3
0
2
0
1
0
1
0
0
0
0
0
0
1
1
X
X
X
0
0
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
15
X
X
X
1
1
1
1
Division ratio : 0 to 127
B > A
•
Division ratio : 0 to 15
B > A
X = DON’T CARE condition
11-Bit Main Counter Division Ratio(B Counter)
Division
N
N
N
N
N
N
N
N
N
N
N
Ratio
18
17
16
15
14
13
12
11
10
9
8
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Division ratio : 3 to 2047
15
S1M8821/22/23
INTERGER RF/IF DUAL PLL
Pulse Swallow Function
fVCO=[ ( P X B ) + A ] x fOSCin / R
fVCO : External VCO output frequency
P : Preset modulus of dual modulus prescaler
(for S1M8821/22 RF:P=64 or 128,
for S1M8823 RF:P=32 or 64,
for IF: P=8 or 16)
B : 11-bit main counter division ratio (3 ≤ B ≤ 2047)
A : 7-bit swallow counter division ratio
(for RF: 0 ≤ A ≤ 127,
for IF: 0 ≤ A ≤ 15, A ≤ B)
fOSCin : External reference frequency(from external oscillator)
R : 15-bit reference counter division ratio (3 ≤ R ≤ 32767)
Program Mode
C1
C2
R16
R17
R18
R19
R20
0
0
IF Phase
Detector Polarity
IF ICPo
IF CPoIF
High Impedance
IF
LD
IF
Fo
0
1
RF Phase
Detector Polarity
RF ICPo
RF CPoIF
High Impedance
RF
LD
RF
Fo
•
C1
C2
N19
N20
1
0
IF Prescaler
Pwdn IF
1
1
RF Prescaler
Pwdn RF
Mode Select Truth Table
Phase Detector Polarity
CPoIF High Impedance
ICPo
IF Prescaler
RF Prescaler
S1M8821/22
(S1M8823)
Pwdn
0
Negative
Normal Operation
Low
8/9
64/65 (32/33)
Pwr Up
1
Positive
High Impedance
High
16/17
128/129 (64/65)
Pwr Dn
* The charge pump output current of ICPo LOW = 1/4 × ICPo HIGH.
16
INTERGER RF/IF DUAL PLL
•
S1M8821/22/23
Phase Detector Polarity
Depending on VCO characteristics, R16 bit should be set as follows :
VCO Output Frequency
VCO Characteristics
VCO characteristics are positive like (1) : R16 HIGH
VCO characteristics are negative like (2) : R16 LOW
(1)
(2)
VCO Input Voltage
•
foLD (Pin10) Output Truth Table
RF R19
(RF LD)
IF R19
(IF LD)
RF R20
(RF fo)
IF R20
(IF fo)
0
0
0
0
Disabled (default LOW)
0
1
0
0
IF Lock Detect
1
0
0
0
RF Lock Detect
1
1
0
0
RF and IF Lock Detect
0
0
0
1
IF Reference Divider Output
0
0
1
0
RF Reference Divider Output
0
1
0
1
IF Programmable Divider Output
0
1
1
0
RF Programmable Divider Output
0
0
1
1
High Speed Lock mode
0
1
1
1
IF Counter Reset
1
0
1
1
RF Counter Reset
1
1
1
1
RF and IF Counter Reset
foLD Output State
— When the PLL is locked and a lock detect mode is selected, the foLD output is HIGH, with narrow pulses
LOW.
— Counter Reset mode resets R & N counters.
— The high speed lock mode sets the foLD output pin to be connected to ground with a low impedance
(≤ 110Ω).
17
S1M8821/22/23
INTERGER RF/IF DUAL PLL
FUNCTIONAL DESCRIPTION (Continued)
•
Powerdown mode operation
There are synchronous and asynchronous powerdown modes for S1M8821/22/23.
Synchronous powerdown mode occurs if R18 bit is LOW, N20 bit is HIGH and charge pump output is in high
impedance state. In the synchronous power down mode, the powerdown function is activated by the charge pump
to diminish unwanted frequency jumps. Asynchronous powerdown mode occurs if R18 bit is HIGH and N20 bit is
HIGH.
When the PLL goes to either synchronous or asynchronous powerdown mode, preamp becomes debiased, R & N
counters keeps their load conditions and the charge pump becomes high impedance state. The oscillator circuitry
function becomes disabled only when both IF and RF powerdown bits are activated, i.e. N20 HIGH.
The PLL returns to an active powerup mode when N20 bit becomes LOW(either in synchronous or asynchronous
modes).
R18
N20
Powerdown mode status
0
0
PLL active
1
0
PLL active, only charge pump high impedance
0
1
Synchronous powerdown
1
1
Asynchronous powerdown
Phase Detector and Charge pump Characteristics
Phase difference detection range : -2π to +2π
When R16 = HIGH
fr
fp
LD
CPo
fr>fp
18
fr=fp
fr<fp
fr<fp
fr<fp
INTERGER RF/IF DUAL PLL
S1M8821/22/23
RF SENSITIVITY MEASUREMENT CIRCUIT
2.7V to 4.0V
RF
Signal
Generator
50Ω
Microstrip
100pF
VDD
fin
10dB ATTN
100pF
51Ω
VP
fin
100pF 2.2µF
100pF
2.2µF
OSCin
LE
foLD
Frequency
Counter
12kΩ
DATA
CLOCK
PC
Parallel
Port
39kΩ
** N=10,000 R=50 P=64
** Sensitivity limit is determined when the error of the divided RF output( foLD) becomes
≥ 1 Hz.
19
S1M8821/22/23
INTERGER RF/IF DUAL PLL
TYPICAL APPLICATION CIRCUIT
VP
VCO
1000pF
Reference
Input
0.01µF
100pF
R1
RF out
10pF
51Ω
100pF
VDD
C2
0.01µF
C1
100pF
foLD
Rin
100pF
18Ω
0.01µF
10
9
8
7
6
5
4
3
2
1
foLD
GND
OSCin
GND
finRF
finRF
GND
CPoRF
VP1
VDD1
S1M8821/22/23
CLOCK DATA
11
12
LE
GND
finIF
finIF
GND
CPoIF
VP2
VDD2
13
14
15
16
17
18
19
20
From
Controller
IF out
10pF
0.01µF
Rin
100pF
18Ω
VDD
100pF
VCO
<RF VCO Module: ALPS Part No>
. CDMA : UCVA4X103A
. K-PCS : UCVW4X102A
. US-PCS : UCVA3X120A
100pF
Vp
R2
C4
C3
100pF
** The role of Rin : Rin makes VCO output power go to the load rather than the PLL.
The value of Rin depends on the VCO power level.
20
0.01µF
0.01µF
INTERGER RF/IF DUAL PLL
S1M8821/22/23
PACKAGE DIMENSIONS
#11
4.40 ¡¾ 0.20
0.173 ¡¾ 0.008
0.15 x +0.10
-0.05
0.006 x +0.004
-0.002
5.72
0.225
0 ~ 8o
6.40 ± 0.30
0.252 ± 0.012
#20
0.50 ¡¾ 0.20
0.020 ¡¾ 0.008
#10
0.90 ± 0.20
0.059 ± 0.008
6.90
0.272 MAX
6.40 ¡¾ 0.20
0.252 ¡¾ 0.008
1.10
MAX
0.073
#1
0.30
0.012
0.65
0.026
0.05
0.002 MIN
0.10MAX
0.004MAX
0.22 ¡¾ 0.10
0.009 ¡¾ 0.004
20-Lead TSSOP Package
(Samsung 20-TSSOP-BD44)
21
S1M8821/22/23
INTERGER RF/IF DUAL PLL
PACKAGE DIMENSIONS (24-QFN)
1.00MAX
0.27 + 0.05
0.70 + 0.05
4.50 + 0.10
#1 INDEX AREA
B
3.50 + 0.10
C
A
(0.05)
(0.05)
0.08
4X0.50 + 0.10
#24
#1
2X4.00
#1 ID MARK
2X
0.10
20X0.50
24X0.30 + 0.05
2X1.00
2X
0.10
22
C
C
0.10 M
C B
C S
C