INTERSIL ISL55112IRTZ

ISL55112
Features
The ISL55112 is a high-speed CCD array driver
comprising 2 Horizontal drivers with high current output
drive and 2 ancillary signal drivers with lower current
output drive.
• 2 Horizontal Row Drivers (High Current)
The devices can be used in pairs to drive and control two
halves of a high pixel count CCD array as used in high
end Digital Cameras or Camcorders. The device has a
largely symmetric pinout about a center axis to facilitate
the placement of the devices on either side of a large
CCD array with minimal signal routing disruption.
• 2 Ancillary Drivers (Lower Current)
• Up to 8V Signal Swing
• Unipolar and Bipolar Supply Capability
• Adjustable Output Impedance for EMI Control
• 3V Logic Interface
• Low Propagation Delays
• Low Skew: ±500ps
• High Clock Rates: 30MHz+
The ISL55112 can accommodate split asymmetric
voltage supplies up to 8V total for each of the 4 drivers
and has significant flexibility in the selection of these
supply voltages within this range. All 4 drivers have their
own High and Low level supply lines to minimize
interference between drivers caused by shared current
paths.
• Stand-by and Power-Down Modes
Special circuitry for the high current drivers is included to
ensure the highest degree of stability of the driver output
resistance over varying supply voltage, temperature and
semiconductor process variations, resulting in highly
consistent, predictable waveform crossover points.
• Medical Imaging
• Digital Still Cameras
• High Definition Digital Camcorders
• Industrial Vision Systems
• Semiconductor Wafer and Mask Inspection
Equipment
• High Definition Security Systems
• Home Security Systems
Pin Configuration
1. Add “-T” suffix for tape and reel. Please refer to TB347 for
details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die
attach materials and 100% matte tin plate plus anneal (e3
termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering
operations). Intersil Pb-free products are MSL classified at
Pb-free peak reflow temperatures that meet or exceed the
Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device
information page for ISL55112. For more information on
MSL please see techbrief TB363.
September 23, 2009
FN6649.0
1
VDD
GND
22
21
20
RGIN
1
19 H1_VN
H1IN
2
18 H1_OUT
PD
3
17 H1_VP
ROIC
4
16 DNC
EN
5
15 H2_VP
H2IN
6
14 H2_OUT
HLIN
7
13 H2_VN
8
9
10
11
12
VSUB
55112 IRTZ -40 to +85 24 Ld TQFN L24.4x5C
23
VPLUS
PACKAGE
PKG.
(Pb-Free) DWG. #
24
HL_VN
ISL55112IRTZ
TEMP.
RANGE
(°C)
HL_OUT
PART
NUMBER
PART
(Notes 1, 2, 3) MARKING
RG_VN
Ordering Information
RG_OUT
The ISL55112 is available in 24 Ld exposed pad TQFN
package and is specified for operation over the full -40°C
to +85°C temperature range.
RG_VP
ISL55112
(24 LD TQFN)
TOP VIEW
HL_VP
The ISL55112 can drive high capacitance loads at pixel
clock rates exceeding 30MHz with low propagation
delays, and skews between channels of better than
±500ps.
Applications*(see page 19)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2009. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
ISL55112
High-Speed Dual Precision CCD Driver
ISL55112
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
RGIN
Logic input for the Reset Gate (low capacitance) driver.
2
H1IN
Logic input for the H1(high capacitance) driver.
3
PD
4
ROIC
5
EN
6
H2IN
Logic input for the H2 (high capacitance) driver.
7
HLIN
Logic input for the HL Driver (low capacitance) driver.
8
HL_VP
9
HL_OUT
10
HL_VN
Low current driver (HL) lower supply voltage connection.
11
VPLUS
Bias connection. Tie to most positive supply line on device.
12
VSUB
Bias connection. Tie to most negative supply line on device. Note: This potential is also on the
exposed pad of the device.
13
H2_VN
High current driver (H2) lower supply voltage connection. (Connect to same voltage as H1_VN).
14
H2_OUT
15
H2_VP
16
DNC
17
H1_VP
18
H1_OUT
19
H1_VN
20
GND
Device ground connection.
21
VDD
Logic supply voltage connection.
22
RG_VN
23
RG_OUT
24
RG_VP
Logic input for placing device in Power-Down State.This is a static input and should never be
toggled above 1Hz.
A resistor to VSUB, sets the output impedance of the High Current Drivers.
Logic input for placing device in the enabled state.
Low current driver (HL) upper supply voltage connection.
Low current driver (HL) output connection.
High current driver (H2) output connection.
High current driver (H2) upper supply voltage connection.
Do not connect, leave open.
High current driver (H1) upper supply voltage connection.
High current driver (H1) output connection.
High current driver (H1) lower supply voltage connection (Connect to same voltage as H2_VN).
Low current driver (RG) lower supply voltage connection.
Low current driver (RG) output connection.
Low current driver (RG) upper supply voltage connection.
2
FN6649.0
September 23, 2009
ISL55112
Functional Diagram
RG_VP
RG_OUT
RGIN
RG_VN
H1_VP
H1_OUT
H1IN
OIC ADJUST
H1_VN
.
ROIC
H2_VP
H2IN
H2_OUT
OIC ADJUST
H2_VN
HL_VP
HLIN
HL_OUT
HL_VN
EN
PD
DEVICE POWER-DOWN
3
FN6649.0
September 23, 2009
ISL55112
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VPLUS and VSUB) . . . . . . . . . . . . . . . 9.0V
Supply
Voltage
(H1_VP/H2_VP/RG_VP/HL_VP - H1_VN/
H2_VN/RG_VN/HL_VN) . . . . . . . . . . . . . . . . . . . . . 9.0V
Supply Voltage (VDD VLOGIC) . . . . . . . . . . . . -0.3V to 6.0V
Maximum Output Current H1-H2 . . . . . . . . . . . . . . 200mA
Maximum Output Current RG/HL . . . . . . . . . . . . . . . 20mA
Input Voltages
H1/H2/RG/HL/EN/PD . . . . . (GND -0.5V) to (VLogic +0.5V)
Output Voltages
H1/H2//RG/HL . . . . . . . . . . . . . (VN -0.5V) to (VP +0.5V)
LATCH-UP . . . . . . . . . . . . . . . . . Class II, Level A AT +85°C
ESD Ratings
Human Body Model (HBM) . . . . . . . . . . . . . . . . . . . . 3kV
Machine Model (MM) . . . . . . . . . . . . . . . . . . . . . . . 300V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
24 Ld QFN Package (Notes 4, 5) . .
37
1.5
Maximum Junction Temperature (Plastic Package). . . +150°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature. . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features and is based on 6 Thermal Vias. See Tech Brief TB379 for details. Adding additional vias can improve thermal
performance. See Tech Brief TB389.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Recommended Operating Specifications Boldface limits apply over the operating temperature range,
-40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Driver Positive Supply
VPn
H1, H2, RG, HL
Full
-2.5
8.0
V
Driver Negative Supply
VNn
H1, H2, RG, HL
Full
-8.0
2.5
V
Driver Differential Supply Range
VPn-VNn
H1, H2, RG, HL
Full
5.5
8.0
V
Logic Positive Supply Voltage
VDD
Full
2.7
5.5
V
NOTE: VPLUS must be connected to most positive Driver Voltage Rail, VSUB must be connected to the most negative voltage rail.
VSUB should be connected to ground where Driver Negative Supplies are above ground. H1_VN and H2_VN should be connected
to each other and operated at the same voltage.
Electrical Specifications
SYMBOL
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V,
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C.
PARAMETER
TEST CONDITIONS
(Note 8)
TEMP
(°C)
MIN
(Note 6)
25
2.0
V
Full
2.0
V
TYP
MAX
(Note 6)
UNITS
LOGIC INPUT CHARACTERISTICS H1/H2/RG/HL DRIVER INPUTS
VIH
VIL
IIH
IIL
Input High Threshold Voltage H1, H2, RG,
HL (Note 10)
VDD = 3.3V
Input Low Threshold Voltage H1, H2, RG,
HL (Note 10)
VDD = 3.3V
Logic “1” Input Current
H1, H2, RG,
HL
VINPUT = 5.5V,
VDD = 5.5V
Full
H1, H2, RG,
HL
VINPUT = 0.0V,
VDD = 5.5V
Full
Logic “0” Input Current
25
1.2
V
Full
1.2
V
63
µA
65
µA
25
25
56
45
30
175
nA
200
nA
CIN
Input Capacitance (Gnd)
H1, H2, RG, HL
25
3.5
pF
RIN
Input Resistance (Gnd)
H1, H2, RG, HL
25
100k
Ω
4
FN6649.0
September 23, 2009
ISL55112
Electrical Specifications
SYMBOL
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V,
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
(Note 8)
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
LOGIC INPUT CHARACTERISTICS EN (Enable) and PD (Power-Down) DRIVER INPUT
VIH
VIL
IIH
IIL
Input High Threshold Voltage EN, PD
(Note 11)
VDD = 3.3V
Input Low Threshold Voltage EN, PD
(Note 11)
VDD = 3.3V
Logic “1” Input Current
VINPUT = 5.5V,
VDD = 5.5V
Full
VINPUT = 0.0V,
VDD = 5.5V
25
45
nA
Full
50
nA
Logic “0” Input Current
EN, PD
EN, PD
25
2.0
V
Full
2.0
V
25
1.2
V
Full
1.2
V
5
µA
5.5
µA
25
3
CIN
Input Capacitance (Gnd)
EN, PD
25
3.5
pF
RIN
Input Resistance (Gnd)
EN, PD
25
2M
Ω
DRIVER SIGNAL OUTPUT CHARACTERISTICS H1 and H2 (Note 12)
VOH
Driver Output High Voltage
H1, H2: IOUT = -10mA
25
3.9
3.93
3.95
V
VOL
Driver Output Low Voltage
H1, H2 IOUT = 10mA
25
-3.95
-3.93
-3.90
V
ROH
Driver Source Output
Resistance
H1, H2: IOUT = -100mA (Note
12)
25
2.8
9
Ω
ROL
Driver Sink Ouput
Resistance
H1, H2: IOUT = -100mA
(Note 12)
25
2.0
8
Ω
IPK+
Peak Sourcing Current
ROIC = 40k
H1, H2:
CL = 0.022µf,
= 68k
R
(Notes 12,13) OIC
ROIC = 80k
25
2.66
Α
25
2.04
Α
25
1.96
Α
ROIC = 120k
IPK-
Peak Sinking Current
ROIC = 40k
H1, H2:
CL = 0.022µf,
= 68k
R
(Notes 12,13) OIC
ROIC = 80k
ROIC = 120k
tR
tF
tPD+
tPDtSKEW+
Driver Rise Time
H1, H2: CL = 300pF: VP = +6V,
VN = -1V
25
1.66
Α
25
2.18
Α
25
1.72
Α
25
1.64
Α
25
1.52
25
2.8
H1, H2: CL = 300pF: VP = +6V,
VN = -1V
Propagation Delay Rising
Edge
H1, H2: CL = 300pF: VP= +6V,
VN = -1V
Propagation Delay Falling
Edge
H1, H2: CL = 300pF: VP= +6V,
VN = -1V
Full
Driver Skew, H1 to H2 Rising
Edge
H1, H2: CL = 300pF
25
25
Driver Skew, H1 to H2 Falling H1, H2: CL = 300pF
Edge
tSKEW±
Skew: H1 Rising H2 Falling
H1, H2: CL = 300pF
25
ns
2.8
4.2
ns
4.3
ns
7.7
10.1
ns
10.5
ns
10.1
ns
Full
25
7.7
10.5
0
-0.50
25
Full
0.50
-0.50
ns
ns
0.50
0
-0.50
ns
ns
0
25
Full
5
4.3
Full
Full
tSKEW-
ns
Full
Driver Fall Time
Α
4.2
ns
ns
0.50
ns
FN6649.0
September 23, 2009
ISL55112
Electrical Specifications
SYMBOL
tSKEW±
FMAX
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V,
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
PARAMETER
Skew: H2 Rising H1 Falling
Max Operating Frequency
TEST CONDITIONS
(Note 8)
H1, H2: CL = 300pF
H1, H2: CL = 300pF: VP= +6V,
VN = -1V
H1, H2:
CL = 300pF
CHINT
Calculated Empirical Internal H1, H2:
H Driver capacitance
CL = 0
TEMP
(°C)
MIN
(Note 6)
25
TYP
MAX
(Note 6)
0
Full
-0.50
25
40
UNITS
ns
0.50
ns
MHz
ROIC = 40k
25
70
MHz
ROIC = 120k
25
55
MHz
40MHz,
ROIC = 68k
25
60
pF
2.5
ns
tMIN
Min Pulse Width
CL = 0pF
25
tMIN
Min Pulse Width
CL = 300pF VP = 6, VN = -1V
25
4
5.5
8
ns
DRIVER SIGNAL OUTPUT CHARACTERISTICS RG and HL
VOH
Driver Output High Voltage
RG, HL: IOUT = -1mA
25
3.96
3.97
3.99
V
VOL
Driver Output Low Voltage
RG, HL; IOUT = 1mA
25
-3.99
-3.97
-3.96
V
ROH
Driver Source Output
Resistance
RG, HL: IOUT = -10mA
Driver Sink Ouput
Resistance
RG, HL: IOUT = -10mA
Driver Rise Time
RG, HL: CL = 22pF
ROL
tR
25
25
Driver Fall Time
25
RG, HL: CL = 22pF
tPDtSKEW+
tSKEWFMAX
Propagation Delay Rising
Edge
RG, HL: CL = 22pF (Note 14)
Propagation Delay Falling
Edge
RG, HL: CL = 22pF (Note 14)
Driver Skew, RG to HL Rising
Edge
RG, HL: CL = 22pF,
Driver Skew, RG to HL Falling RG, HL: CL = 22pF,
Edge
Max Operating Frequency
55
Ω
56
Ω
ns
3.7
ns
8.2
ns
ns
8.5
7.9
ns
9.0
ns
0.50
ns
0
-0.5
25
ns
0
Full
-0.5
RG. HL: CL = 90pF: VP = +6V,
VN = -1V
25
40
RG, HL: CL = 22pF
Full
60
ns
ns
7.6
7
25
Full
Ω
3.5
3.1
25
Full
Ω
3.4
25
Full
55
56
3
2.5
25
Full
tPD+
17
Full
Full
tF
22
Full
ns
0.50
ns
MHz
MHz
tMIN
Min Pulse Width
CL = 0pF
25
3.6
ns
tMIN
Min Pulse Width
CL = 22pF
25
6.5
ns
Power Down and Driver Enable timing (Note 8)
tPD ON
Active Mode to Power Down
Time
Time VDD Current Drops to <
100µA (Note 8)
25
25
50
µs
tPD OFF
Power Down to Active Mode
Time
Time H-Drivers tPD/tR/tF Takes to
Stabilize (Note 8)
25
25
50
µs
6
FN6649.0
September 23, 2009
ISL55112
Electrical Specifications
SYMBOL
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V,
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
(Note 8)
PARAMETER
tEN ON
Driver Enable to Disable
Mode Time
tEN OFF
Drivers Disable to Enable
Mode Time
CLK Running at 30MHz
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
25
33
ns
25
33
ns
25
2.5
Standby Supply Current: EN = 1:PD = 0
ISB
Current on each pin type,
Input= = 0Hz
H1_VP,
H2_VP
+4.0V
H1_VN,
H2_VN
-4.0V
RG_VP,
HL_VP
+4.0V
RG_VN,
HL_VN
-4.0V
VDD
3.3V
Full
25
-5
Full
-5.5
25
Full
-1.7
25
+4.0V
1.0
Full
VSUB
-4.0V
25
-2.2
Full
-2.5
1.5
mA
1.7
mA
mA
mA
.75
25
mA
-0.25
Full
VPLUS
mA
mA
0.25
-1.5
mA
5
-2.5
Full
25
4.75
1.2
mA
1.3
mA
1.8
mA
2.0
mA
-1.4
mA
mA
Power-Down Supply Current: EN = X, PD =1
IPD
Current on each pin type
H1_VP,
H2_VP
+4.0V
H1_VN,
H2_VN
-4.0V
RG_VP,
HL_VP
+4.0V
RG_VN,
HL_VN
-4.0V
VDD
3.3V
VPLUS
+4.0V
25
70
Full
25
-450
Full
-500
25
Full
-250
25
70
Full
7
-4.0V
25
-400
Full
-450
µA
200
µA
250
µA
µA
µA
Full
VSUB
µA
-10
30
25
500
µA
Full
-200
µA
-70
10
25
450
-70
300
µA
320
µA
400
µA
450
µA
µA
µA
FN6649.0
September 23, 2009
ISL55112
Electrical Specifications
SYMBOL
Test Conditions: XX_VP = 4V, XX_VN = -4V, VDD = 3.3V, VPLUS = 4V, VSUB = -4V,
ROIC = 68kΩ; Unless Otherwise specified. Full (-40°C to +85°C) limits are established by
characterization and are not production tested. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
TEST CONDITIONS
(Note 8)
PARAMETER
TEMP
(°C)
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Active Supply Current: EN=1, PD=0
IACT
Current on each pin type; 40
MHz input: Note 15
H1_VP,
H2_VP
+4.0V
25
118
mA
H1_VN,
H2_VN
-4.0V
25
-118
mA
RG_VP,
HL_VP
+4.0V
25
15
mA
RG_VN,
HL_VN
-4.0V
25
-15
mA
VDD
3.3V, All driver
inputs running
25
3.8
mA
VPLUS
+4.0V
25
0.9
mA
VSUB
-4.0V
25
-0.9
mA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Full Temperature limits
established by characterization and are not production tested.
7. The algebraic convention, where by the most negative value is the minimum and the most positive a maximum, is used in the
data sheet.
8. All load capacitances are with respect to Gnd.
9. PD (Power-Down) is a static control. Do not allow toggle frequency above 1 Hz. PD should be used in combination with EN pin
during Active and Inactive state changes. (See Power Mode Sequencing).
10. H1, H2, EN, RG, HL VIH and VIL Thresholds established while toggling @10MHz.
11. PD VIH and VIL Thresholds established while toggling @ 1Hz.
12. ATE test conditions limit rON measurement capability. Refer to Characterization tables for typical rON Values. The Output
Impedance Control active circuitry adjusts rON characteristics dynamically.
13. Peak current as measured with evaluation board with 1Ω resistor in series with 0.022µF capacitor. Measurements as
characterized with ISL55112 Evaluation board.
14. Dynamic FULL/MIN/MAX data recorded with ISL55112 Evaluation board. Series inductance of decoupling, loads and
interconnect will greatly influence this measurement. See section on “Power Supply Bypassing and Printed Circuit Board
Layout” on page 11.
15. As measured using evaluation board with H1_OUT, H2_OUT = 300pF load on each output and RG_OUT, HL_OUT = 22pF load
on each output.
Test Circuits and Waveforms
3V
IN
VDD
50%
50%
tPD+
tPD-
0V
EN
OUT
IN
CL
VP
50%
OUT
50%
VN
SIGNAL
GENERATOR
90%
OUT
10%
tR
FIGURE 1A. TEST CIRCUIT
VP
90%
10%
VN
tF
FIGURE 1B. MEASUREMENT POINTS
FIGURE 1. DRIVER PROPAGATION DELAY AND RISE AND FALL TIMES
8
FN6649.0
September 23, 2009
ISL55112
Test Circuits and Waveforms (Continued)
EN
3V
OUT
IN
EN
CL
50%
50%
0V
SIGNAL
GENERATOR
tEN ON
SIGNAL
GENERATOR
tEN OFF
VP
50%
OUT
50%
VN
VP
50%
OUT
50%
VN
FIGURE 2B. MEASUREMENT POINTS
FIGURE 2A. TEST CIRCUIT
FIGURE 2. DRIVER ENABLE AND DISABLE TIMES
1000pF AND 0.1µF
VDD = 3.3V
XX_VP = 4V
XX_VN = -4V
GND = 0V
22pF
1000pF AND 0.1µF
24
PD
68kΩ ROIC
EN
H2IN
HLIN
VDD
GND
20
H1_VN
1
19
2
18
3
17
4
16 NC
5
15
6
14
7
13
9
HLOUT
HL_VP
8
10
11
12
H1OUT
300pF
H1_VP
H2_VP
H2OUT
300pF
H2_VN
ALL CAPACITORS ABOVE ARE 0.1µF AND
BULK DECOUPLING CAPACITORS
(NOT SHOWN) ON EACH SUPPLY
VSUB
PD should not be
operated above 1Hz
21
VPLUS
H1IN
22
HL_VN
RGIN
23
RG_VN
RG_VP
RGOUT
0.1µF AND 4.7µF
0.1µF
1000pF AND 0.1µF
22pF
0.1µF
1000pF AND 0.1µF
0.1µF
FIGURE 3. STANDARD TEST CONFIGURATION
9
FN6649.0
September 23, 2009
ISL55112
RG_VN
3.3V
24
23
22
21
20
RGOUT
13
14
15
H1OUT
7
6
5
4
3
2
1
HXVP
H2OUT
RG_VP
17
18
19
RGIN
H1IN
PIN 12 (VSUB)
H2IN
HLIN
20
21
22
23
24
19
18 H1OUT
17
HXVP
15
14 H2OUT
13
RGOUT
8
9
10
11
12
PIN 12 (VSUB)
RGIN 1
H1IN 2
3
4
5
H2IN 6
HLIN 7
RG_VN
CCD Array
with Dual
Video Outputs
12
11
10
9
8
RG_VP
HLOUT
HLOUT
3.3V
HL_VP
HL_VN
HL_VN
HL_VP
FIGURE 4. SYMMETRY ACCOMMODATES DUAL DEVICE UTILIZATION WITH A DUAL VIDEO CCD DEVICE
Application Information
The ISL55112 2+2 CCD device provides four drivers for
horizontal inputs of CCD arrays. It comprises two high
capacitance drivers (H1/H2) and two low capacitive
drivers for handling Reset Gate (RG)/Last H (HL) inputs
of a CCD device.
CCD Driver Rails
Each of the four driver outputs has its own set of high
and low rail supply connections. The positive rail
connections for the drivers are RG_VP, HL_VP, H1_VP,
H2_VP. The negative driver rail connections are RG_VN,
HL_VN, H1_VN, H2_VN. (Note H1_VN = H2_VN and
should always be at the same voltage).
From an applications and physical routing standpoint, the
H1/H2 (high current drivers) have identical circuitry.
Likewise, the HL/RG (low current drivers) circuitry is the
same internally. In dual device applications, the user is
free to swap driver outputs to accommodate layout
requirements.
Once the user has defined the “Driver” amplitudes
required by the CCD, Device bias connections, VPLUS and
VSUB must be connected to the maximum and minimum
voltage required.
The ISL55112 H1/H2 have fast rise / fall times into large
capacitive loads. H1/H2 are designed with short
propagation delays and tightly controlled skew, allowing
the device to be used on large, fast CCD arrays, used in
image processing applications
VPLUS should be connected to the most positive voltage.
VSUB should be connected to the most negative voltage.
Accordingly, the VPLUS/ VSUB connections can only be
determined once the CCD device driver output amplitude
requirements have been determined.
Supply Voltages
Dual Video CCD Connection Considerations
The ISL55112 has three types of pins when it comes to
supply voltages: Logic, driver rails and device bias
connections.
VDD and Ground Supply Connections
The ISL55112 has a logic supply (VDD) that can be set
from 2.7V to 5.5V. Hence the VDD supply voltage sets
the operating thresholds for the digital inputs
H1IN, H2IN, RGIN, HLIN, and EN pins are high speed
digital logic connections. Typically they are logic
connections coming from the master CCD timing
generator. PD should have fast transitions, but should not
run at frequencies above 1Hz.
10
Device Bias connections
Physical placement that keeps series inductance to a
minimum is important. The ISL55112 design
accommodates dual device placement close to a CCD
device.
H1 / H2 and RG / HL drivers are internally identical. The
user can rotate the device for PCB placement close to a
single CCD with dual-video requirements.
Power Supply Sequencing
The ISL55112 substrate is connected to the VSUB Pin.
Positive Protection is connected to the VPLUS pin.
The system supply GND connection will always be
present, and is the reference to all other supply voltages.
Therefore apply VDD, VPLUS, VSUB followed by the VP,
VN busses. Digital inputs should be driven as soon as all
FN6649.0
September 23, 2009
ISL55112
power inputs have settled but should not be allowed to
float during power-up and power-down operations.
Note: If VSUB floats high when VDD is applied, a 10k to
50k Resistor should be added from VSUB to ground. For
proper power up biasing, VSUB should not be allowed to
float high when only VDD is applied.
Power Supply Bypassing and Printed Circuit
Board Layout
(C1, C4, C6, C11). Figure 6 shows vias between bottom
decoupling and the device pins on top increase series
inductance. However, bottom decoupling replenishes the
top decoupling before and after edge currents occur.
Additional bulk decoupling (22µF to 4.7µF) should also be
used. This is low frequency decoupling and need not be
located as close to the output area of the device.
Maximum current occurs during edge-transition of the
driver outputs. Decoupling of the VP and VN rails for the
drivers is of paramount concern. This being especially
true of the high current drivers. Minimum possible lead
length from the VP/VN device connections to the
associated decoupling capacitors is key to device
performance.
Given transition times are the point of maximum current,
series inductance from the decoupling point to the VP/
VN connections and from the VOUT connection to the
CCD should be kept to the minimum possible values.
Note: The ISL55112 employs multiple bond wires on all
driver rail and driver output connections. Multiple bond
wires help reduce the device package internal bond wire
connection inductance.
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance.
Ground plane construction is highly recommended, lead
lengths should be as short as possible, and the power
supply pins must be well bypassed to reduce the risk of
oscillation.
FIGURE 5. TOP COMPONENT AND PCB ARTWORK
The “Evaluation Board” drawing depicts a conceptual
decoupling scenario. Capacitor values, placement and
quantities are subject to specific application
requirements. The key to decoupling, especially during
edge transitions, is to reduce the series inductance of the
VP/VN supply rails.
Decoupling Discussion and
Evaluation Board Information
• With split supply driver voltages, each VN and VP pin
should have a separate 0.1µF capacitor to ground.
The capacitors should be on the top layer of the PCB
to a ground plane. This avoids the operative
decoupling point having a via in series with the
device pin.
• Single supply applications require fewer decoupling
capacitors (VN rails are connected to ground. In this
case, the top layer should also be a ground plane
and VP pins should be decoupled as closely as
possible.
• In both cases, the return path series inductance
needs to be considered. The return current path of
the load and the decoupled point should be as close
as possible. Avoid/reduce Vias between driver rail
decoupling points and driver output to load.
Figure 5 shows the top decoupling provides the high
frequency driver rail decoupling during edge transitions
11
FIGURE 6. BOTTOM COMPONENT AND PCB ARTWORK
Output Impedance Control (OIC)
An external Resistor, ROIC, is used to set the output
impedance of the high current drivers. Selection of ROIC
resistance value enables the user to adjust high current
H1/H2 driver operation for a specific CCD product.
Rise and Fall times can be adjusted via the ROIC
resistance setting. This is accomplished by selecting an
ROIC resistance value from 40kΩ to 120kΩ. Actual
rise/fall timing will be the product of driver loading and
interconnect parasitics.
High current driver characteristics, which are normally
affected by temperature and process variations, are kept
to a minimum by the ISL55112 OIC feature.
FN6649.0
September 23, 2009
ISL55112
Dynamic Measurements
The ISL55112 drivers require minimum series inductance
to operate properly. Therefore it is not recommended
that test sockets be used when evaluating driver
performance. Parts should be soldered to an appropriate
layout that addresses both driver load and driver rail
decoupling series inductance.
Input Signals
The ISL55112 has logic signal inputs on H1,H2, RG and
HL drivers. The ISL55112 also has two “mode control”
pins (PD and EN) which enable the user to control power
requirements. Input signals switching thresholds are set
by the VDD to Gnd voltage.
Power Saving Mode Control
The ISL55112 offers two methods of power reduction.
The Power Down control pin is to be used in conjunction
with Enable pin. (See “Mode control Power-Down
sequence” and “Mode control Power-Up sequence” on
page 12).
When EN is set to the active state (High), the drivers will
respond to driver inputs. Reaction time to the 1st drive
pulse is defined in the electrical table as “tEN ON” on
page 7.
During initial Power-Up, H1 and H2 Outputs will be HIz
until a transition occurs on the H1 and H2 Inputs.
Device Power-Down (PD)
In Power-Down Mode, both input circuitry and gate drive
circuitry is powered down. Power-down should only be
used for static control. Do not exceed 1Hz of operation.
The recommended sequences for Power Mode control
are:
MODE CONTROL POWER-DOWN SEQUENCE
Device active (Enable High, Power Down Low)
• Set Power Down High Set Enable Low.
MODE CONTROL POWER-UP SEQUENCE
Device inactive (Enable Low, Power Down High)
Driver Standby (EN)
• Set Enable High, Set Power Down Low
(EN: Low, PD Low) In this state the gate drive circuit is
active but the front end receivers are shut off. Shorter
term power savings can be realized by using the EN
input.
Power Dissipation Considerations
When EN is disabled (EN: Low, PD: Low), the driver
outputs will stay in their last state prior to setting the EN
signal low. The “tEN off” specification indicates the
response time for the drivers to hold their present logic
state.
Specifying continuous data rates, driver loads and driver
level amplitudes are key in determining power supply
requirements as well as dissipation/cooling necessities.
Driver Output patterns also impact these needs. The
faster the pin activity, the greater the need to supply
current and remove heat.
TABLE 1. ISL55112 DETAILED POWER DISSIPATION FORMULA/EXAMPLE
FORMULA
VARIABLE
EXAMPLE
VALUES
UNIT
VARIABLES
SQUARED
CALCULATIONS
NOTES
POWER DISSIPATION FORMULA ISL55112: OPERATION VARIABLES
VDD
H_Diff
3.3
8
V
VDD2
V
H_Diff2
64
64
HL_VP-HL_VN
64
RG_VP-RG_VN
HL_Dif
8
V
HL_Diff2
RG_Diff
8
V
RG_Diff2
H1_Freq
40
MHz
10.89
VDD2
Hx_VP - Hx_VN
Operating Frequency
H2_Freq
40
MHz
Operating Frequency
HL_Freq
40
MHz
Operating Frequency
RG_Freq
40
MHz
Operating Frequency
H1_CLOAD
300
pF
High Capacitance Load
H2_CLOAD
300
pF
High Capacitance Load
HL_CLOAD
20
pF
Low Capacitance Load
RG_CLOAD
20
pF
Low Capacitance Load
Driver Loads
POWER DISSIPATION FORMULA ISL55112: DEVICE VARIABLES
Default Currents
IDD
1
12
mA
Stand By VDD Current
FN6649.0
September 23, 2009
ISL55112
TABLE 1. ISL55112 DETAILED POWER DISSIPATION FORMULA/EXAMPLE (Continued)
FORMULA
VARIABLE
IH
EXAMPLE
VALUES
UNIT
VARIABLES
SQUARED
6
mA
Stand By IH Current
CALCULATIONS
NOTES
Device Internal Capacitance
Log_Cint
3.5
pF
Per channel internal logic switching load
H1_Cint
60
pF
Effective Internal Driver Capacitance
H2_Cint
60
pF
Effective Internal Driver Capacitance
HL_Cint
6.3
pF
Effective Internal Driver Capacitance
RG_Cint
6.3
pF
Effective Internal Driver Capacitance
POWER DISSIPATION FORMULAS AND EXAMPLE CALCULATIONS
Wattage Sub Totals and Formula
Standby Watts
Example Calculation
=
VDD*IDD + H_DIFF*IH
0.0513
H1_Logic_Watts
=
Log_Cint*VDD2 * H1_Freq
0.0015
H2_Logic_Watts
=
Log_Cint*VDD2 * H2_Freq
0.0015
HL_Logic_Watts
=
RG_Logic_Watts
=
Log_Cint*VDD2 * HL_Freq
Log_Cint*VDD2 * RG_Freq
0.0015
H1_Cint_Watts
=
H1_Cint*H_Diff2 * H1_Freq
0.1536
H2_Cint_Watts
=
H2_Cint*H_Diff2 * H2_Freq
0.1536
HL_Cint_Watts
=
0.0161
RG_Cint_Watts
=
HL_Cint*HL_Diff2 * HL_Freq
RG_Cint*RG_Diff2 * RG_Freq
H1_Cload*H_Diff2 * H1_Freq
H2_Cload*H_Diff2 * H2_Freq
0.7680
H1_Cload_Watts
=
H2_Cload_Watts
=
HL_Cload_Watts
=
RG_Cload_Watts
=
0.0015
0.0161
0.7680
HL_Cload*HL_Diff2 * HL_Freq
RG_Cload*RG_Diff2 * RG_Freq
Total Watts
Total Watts
37
TJA
Power Dissipation Notes
Power dissipation consists of 4 contributors:
1. Contributor 1 corresponds to the Standby Current of
the VDD Logic Supply (IDD) and VP-VN Driver Rails
(IH)
2. Contributor 2 corresponds to the dissipation from
running the H1, H2, RG and HL Inputs. Log_Cint
specifies the basis for the power consumed from the
VDD Supply for each input.
3. Contributor 3 corresponds to the Driver Rail Supply
dissipation due to internal capacitance. The value of
H1_Cint, H2_Cint, RG_Cint and HL_Cint correspond
to the effective internal capacitance of the drivers.
4. Contributor 4 corresponds to the Driver Rail Supply
dissipation due to load capacitance. The value of
H1_Cload, H2_Cload, RG_Cload and HL_Cload
correspond to the external capacitance of the device
being driven.
These are approximate formulae and the actual values
may be 15% to 20% off.
13
Degrees over ambient
0.0563
0.0563
2.0455
75.68
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T JMAX - T AMAX
P DMAX = --------------------------------------------Θ JA
(EQ. 1)
where:
• TJMAX = Maximum junction temperature
• TAMAX = Maximum ambient temperature
• θJA = Thermal resistance of the package
• PDMAX = Maximum power dissipation in the package
The maximum power dissipation actually produced by an
IC is the total quiescent supply current times the total
power supply voltage, plus the power in the IC due to the
loads. Power also depends on number of channels
changing state and the frequency of operation. The
reader is cautioned against assuming the same level of
thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted. Great care must be taken to ensure Die
Temperature does not exceed +150°C Absolute Maximum
Thermal Limits.
FN6649.0
September 23, 2009
ISL55112
Important Note: The ISL55112 exposed pad is used for heat sinking of the device. It must be electrically
connected to the most negative supply potential needed for driver output (VSUB). Therefore, when
negative drive rails are used, the thermal pad (VSUB) must be isolated from ground.
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68kΩ, CL= 300pF for
H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
2.5
3.4
IOUT = -100mA
3.2
2.3
+85°C
rON (Ω)
rON (Ω)
+85°C
2.2
3.0
+25°C
2.8
2.6
IOUT= +100mA
2.4
2.1
+25°C
2.0
1.9
1.8
-40°C
-40°C
1.7
2.4
1.6
2.2
4
5
6
7
1.5
8
4
5
VH, DRIVE RAIL (V)
FIGURE 7. H1/H2 DRIVER SOURCE RESISTANCE vs
VH
29
20
+85°C
18
+85°C
rON (Ω)
rON (Ω)
25
24
23
+25°C
20
19
4.5
7.5
8.0
FIGURE 9. RG/HL DRIVER SOURCE RESISTANCE vs
VH
14
+25°C
15
-40°C
5.5
6.5
VH, DRIVE RAIL (V)
17
16
22
21
IOUT = +10mA
19
27
26
8
FIGURE 8. H1/H2 DRIVER SINK RESISTANCE VS VH
IOUT = -10mA
28
6
7
VH, DRIVE RAIL (V)
14
-40°C
4.5
5.5
6.5
VH, DRIVE RAIL (V)
7.5
8.0
FIGURE 10. RG/HL DRIVER SINK RESISTANCE vs VH
FN6649.0
September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68kΩ, CL= 300pF for
H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
2.9
2.8
2.15
ROIC = 120kΩ
2.10
VH 8V
IOUT = -100mA
ROIC = 80kΩ
2.6
ROIC = 68kΩ
2.5
ROIC = 80kΩ
2.00
1.95
2.4
1.90
ROIC = 40kΩ
2.3
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
1.85
2.5
FIGURE 11. H1/H2 SOURCE RESISTANCE vs VDD
930
ROIC = 68kΩ
ROIC = 40kΩ
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 12. H1/H2 SINK RESISTANCE vs VDD
3.10
950
+85°C TO -40°C
3.05
RISE/FALL TIME (ns)
910
890
IDD (µA)
VH 8V
IOUT = +100mA
2.05
rON (Ω)
rON (Ω)
2.7
ROIC = 120kΩ
870
850
830
810
790
FALL
3.00
2.95
2.90
RISE
2.85
770
750
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
2.80
2.5
5.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 14. H1/H2 RISE AND FALL vs VDD
FIGURE 13. STAND BY CURRENT (Isb) IDD vs VDD
9.0
3.7
8.5
3.5
RISE/FALL TIME (ns)
8.0
IH (mA)
7.5
7.0
+85°C
6.5
6.0
+25°C
5.5
-40°C
5.0
3.3
FALL
3.1
2.9
RISE
2.7
4.5
4.0
4.5
5.5
6.5
VH, DRIVE RAIL (V)
7.5
8.0
FIGURE 15. STAND BY CURRENT (Isb) IH vs VH
15
2.5
2.5
3.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
FIGURE 16. RG/HL RISE AND FALL vs VDD
FN6649.0
September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68kΩ, CL= 300pF for
H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
600
8
CL = OPEN
7
500
400
CL = 300pF, 22pF
5
IH (mA)
IDD (mA)
6
4
3
CL = 300pF, 22pF
300
200
CL = OPEN
2
100
1
0
0M
20M
40M
60M
80M
TOGGLE FREQUENCY (Hz)
0
0M
100M110M
2.8
2.4
+85°C OR -40°C
2.6
2.2
+25°C
2.4
2.2
LOGIC (V)
LOGIC (V)
100M110M
2.6
3.0
2.0
1.8
1.6
2.0
1.8
1.6
1.4
1.4
+25°C
1.2
1.2
+85°C OR -40°C
3.0
3.5
4.0
VDD (V)
4.5
5.0
3.5
4.0
VDD (V)
4.5
5.0
5.5
13
12
11
CL = 1000pF
CL = 680pF
110
9
8
7
CL = 680pF
6
5
4
2
CL = 300pF
CL = 50Ω
CL = 122pF
1
CL = 0pF
100
CL = 1000pF
10
3
CL = 50Ω
FIGURE 21. H1/H2 tr vs ROIC vs CL
16
3.0
FIGURE 20. ALL INPUTS VIL LOGIC THRESHOLDS
FALL TIME (ns)
14
13
12
11
10
9
8
7
6
5
4
CL = 300pF
3
2 CL = 122pF
1
0
40
50
60
70
80
90
ROIC (kΩ)
1.0
2.5
5.5
FIGURE 19. ALL INPUTS VIH LOGIC THRESHOLDS
RISE TIME (ns)
40M
60M
80M
TOGGLE FREQUENCY (Hz)
FIGURE 18. IH vs FREQUENCY (ALL OUTPUTS
ACTIVE)
FIGURE 17. IDD vs FREQUENCY (ALL OUTPUTS
ACTIVE)
1.0
2.5
20M
120
0
CL = 0pF
40
50
60
70
80
90
ROIC (kΩ)
100
110
120
FIGURE 22. H1/H2 tf vs ROIC vs CL
FN6649.0
September 23, 2009
ISL55112
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68kΩ, CL= 300pF for
H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
7.0
12.0
6.8
11.5
6.6 tpdf, CL = 122pF
tpdr, CL = 122pF
6.4
6.2
6.0
5.8
5.6
tpdf, CL = 50Ω
tpdr, CL = 50Ω
5.4
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
Typical Performance Curves
11.0
tpdf, CL = 1000pF
tpdr, CL = 1000pF
10.5
10.0
9.5 tpd , C = 680pF
f
L
9.0
tpdr, CL = 680pF
8.5
8.0
tpdf, CL = 300pF
5.2
7.5
5.0
-40
7.0
-40
-20
0
20
40
60
80
-20
0
PACKAGE TEMP (°C)
20
40
60
80
PACKAGE TEMP (°C)
FIGURE 23. H1/H2 tpdr/f vs TEMPERATURE vs CL
FIGURE 24. H1/H2 tpdr/f vs TEMPERATURE vs CL
9
12
11
8
+85°C
+25°C
7
-40°C
6
5
4
+85°C
10
FALL TIME (ns)
RISE TIME (ns)
tpdr, CL = 300pF
9
-40°C
8
7
+25°C
6
5
3
2
4
20
30
40
50
60
70
CL (pF)
80
90
3
20
100
FIGURE 25. RG/HL tr vs CL
2.2
50
60
70
CL (pF)
80
+25°C
100
tf
1.9
9.5
9.0
-40°C
8.5
90
CL = 122pF
2.0
TIME (ns)
PROPAGATION DELAY (ns)
2.1
+85°C
10.0
8.0
tr
1.8
1.7
1.6
1.5
1.4
7.5
7.0
20
40
FIGURE 26. RG/HL tf vs CL
11.0
10.5
30
1.3
30
40
50
60
70
80
CL (pF)
FIGURE 27. RG/HL tpdr vs CL
17
90
100
1.2
40
50
60
70
80
90
100
110
120
ROIC (kΩ)
FIGURE 28. H1/H2 tr/f vs ROIC
FN6649.0
September 23, 2009
ISL55112
Typical Performance Curves
VDD = 3.3V, VH = 4V, VN = -4V, ROIC = 68kΩ, CL= 300pF for
H1/2OUT, CL = 22pF for RG/HLOUT, Unless specified otherwise. Refer
to Figures 1, 2 and 3. (Information derived from ISL55112 Evaluation
board characterization. See AN1495 ISL55112 Evaluation Board).
3.4
RISE & FALL TIME (ns)
3.3
Die Characteristics
3.2
3.1
3.0
SUBSTRATE AND TQFN THERMAL PAD
POTENTIAL (POWERED UP):
H1 tr
H1 tf
2.9
VSUB
2.8
TRANSISTOR COUNT:
2.7
3900
2.6
PROCESS:
2.5
2.4
-40
SUB MICRON CMOS
-20
0
20
40
PACKAGE TEMP (°C)
60
80
FIGURE 29. H1 tr / tf vs TEMPERATURE
TQFN Package Discussion
Typically, power dissipation is a limiting factor in CCD
array driving applications. The key tool in removing heat
from the drivers is the thermal pad on the bottom of the
TQFN package.
Electrically, this exposed pad is connected to the device
substrate and is the most negative voltage. In
applications where negative drive rails are used, this pad
must be isolated from ground and connected to the
negative bus. However, the size of the thermal pad and
the associated voltage plane/layer it connects to
determines the heat dissipation capability of the pad.
TOP VIEW
BOTTOM VIEW
The TQFN Thermal Pad is the main tool for dealing
with Power Dissipation.
FIGURE 30. ISL55112 TQFN PAD LAYOUT EXAMPLE
TOP AND BOTTOM VIEWS
The footprint for the ISL55112 should include a “Thermal
Via Array” of through-holes. Hole size and spacing of
these vias should maximize heat transfer to the bottom
of the board and away from the device. Hole size should
accommodate solder wicking requirements. The quantity
of vias is limited by pad size and recommended spacing.
Vias should also have a solid connection to the associated
power plane.
Another item that affects thermal transfer is the layout
on the bottom of the board. Circuit lands that run parallel
with the package can actually become heat barriers. If
signals are routed on the bottom, try to route signal
paths (90°) away from the pad area. Make the exposed
pad area as large as possible on the bottom layer.
(Remember in negative voltage applications the pad
needs to be electrically isolated from the ground plane.)
Reference Intersil TB-389 A grid of 1.0mm to 1.2mm
pitch thermal vias, which drop down and connect to
buried copper plane(s), should be placed under the
thermal land. The vias should be about 0.3mm to
0.33mm in diameter, with the barrel plated to about 1.0
ounce copper. Although adding more vias (such as by
decreasing via pitch) will improve thermal performance,
diminishing returns will be seen as more and more vias
are added. Therefore, simply use as many vias as
practical for the thermal land size and your board design
ground rules.
Recommended Land Pattern (TQFN PCB
Footprint)
Please refer to the Package Outline Drawing for
recommended land size guidelines.
18
FN6649.0
September 23, 2009
ISL55112
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
9/23/09
FN6649.0
CHANGE
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL55112
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
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19
FN6649.0
September 23, 2009
ISL55112
Package Outline Drawing
L24.4x5C
24 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 10/07
4.00
PIN 1
A
2.65
24X0.40
PIN #1 INDEX AREA
CHAMFER 0.400
× X 45°
INDEX AREA
20
B
6
24
6
1
0.50
19
5.00
3.65
0.5x6=3.00 REF
7
13
12
0.10
4X
8
0.23±0.05
0.50
TOP VIEW
0.10 M C A B
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10 C
C
0.75
SEATING PLANE
0.08 C
(24x0.25)
SIDE VIEW
(4.80 TYP) (3.65)
(20x0.50)
0 . 20 REF
(2.65)
5
C
(24x0.60)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is
measured between 0.18mm and 0.28mm from the
terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but
must be located within the zone indicated. The pin #1
20
FN6649.0
September 23, 2009