S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER November. 1999. Ver. 0.1 Prepared by: Sangho Park [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Specification Revision History Version 2 Content Date 0.0 Original Aug.1999 0.1 The content of page 21 has been modified Nov.1999 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 CONTENTS INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSINGMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS ........................................................................................................................................... 7 OPERATION DESCRIPTION............................................................................................................................... 8 DISPLAY DATA TRANSFER ............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE .................................................. 9 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 18 RECOMMENDED OPERATION CONDITIONS.................................................................................................. 18 DC CHARACTERISTICS................................................................................................................................... 19 AC CHARACTERISTICS................................................................................................................................... 20 WAVEFORMS ................................................................................................................................................... 21 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD ........................ 22 3 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER INTRODUCTION The S6C0641 is a 300 channel or 309 channel output, TFT-LCD source driver for 64 gray scale displays. Data input is based on digital input consisting of 6 bits by 3 dots, which can realize a full-color display of 260,000 colors by output of 64 values gamma-corrected. This device has an internal D/A (Digital-to-Analog) converter for each output and 9 or 11 external power supplies. S6C0641 can be adopted to larger panel, and SHL (Shift Direction Selection) pin makes use of the LCD panel connection conveniently. Maximum operation clock frequency is 55 MHz at a 3.3 V logic operation. It can be applied to the TFT-LCD panel of SVGA, XGA standards. FEATURES • TFT active matrix LCD source driver LSI • 64 gray scale is possible through 9 or 11 external power supply and D/A converter • Line inversion display is possible • CMOS level input • Compatible with gamma-correction • Logic supply voltage: 3.0 - 5.5 V • LCD driver supply voltage: 3.0 - 5.5 V • Output dynamic range: 2.6 - 5.1 Vp-p • Maximum operating frequency: fMAX = 55 MHz (internal data transmission rate at 3.3 V operation) • Output: 300 / 309 outputs • TCP available 4 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Y001 Y002 Y003 Y307 Y308 Y309 BLOCK DIAGRAM Output Buffer VGMA1 VGMA11 11 D/A Converter 6 6 6 6 6 6 6 6 6 Data Latch CLK1 6 6 6 D00 - D05 6 D10 - D15 6 D20 - D25 6 CLK2 Data Control Data Register 18 100 / 103 bit Shift Register DIO2 SELT SHL TESTB DIO1 Figure 1. S6C0641 Block Diagram 5 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER PIN ASSIGNMENTS Y001 Y002 Y003 (Top View) S6C0641 Y004 Y306 Y307 Y308 Y309 Figure 2. S6C0641 Pin Assignments 6 VSS2 VDD2 VGMA10 VGMA8 VGMA6 VGMA4 VGMA2 D05 D04 D03 D02 D01 D00 D15 D14 D13 D12 D11 D10 DIO1 VSS1 SELT CLK2 VDD1 DIO2 CLK1 D25 D24 D23 D22 D21 D20 SHL VGMA1 VGMA3 VGMA5 VGMA7 VGMA9 VGMA11 VDD2 VSS2 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 PIN DESCRIPTIONS Symbol Pin Name VDD1 Logic power supply 3.0- 5.5 V VDD2 Driver power supply 3.0 - 5.5 V VSS1 Logic ground Ground (0 V) VSS2 Driver ground Ground (0 V) Y1 – Y309 Driver outputs The D/A converted 64 gray scale analog voltage is output. D0<0:5> - D2<0:5> Display data input SHL Description The display data is input with a width of 18 bits, gray-scale data (6 bits) by 3 dots (R,G,B) DX0: LSB, DX5: MSB This pin controls the direction of shift register in cascade connection. The shift direction of the shift registers is as follows. Shift direction control input SHL = H: DIO1 input, Y1 → Y309, DIO2 output SHL = L: DIO2 input, Y309 → Y1, DIO1 output DIO1 Start pulse input / output SHL = H: Used as the start pulse input pin. SHL = L: Used as the start pulse output pin. DIO2 Start pulse input / output SHL = H: Used as the start pulse output pin. SHL = L: Used as the start pulse input pin. CLK2 Shift clock input CLK1 Latch input SELT 300 / 309CH output control input VGMA1 – VGMA11 Gamma corrected power supplies TESTB Test input Refer to the shift register's shift clock input. the display data is loaded to the data register at the rising edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. This pin controls 300CH or 309CH output. SELT = H: 309CH output → Y151 to Y159 are useless. SELT = L: 300CH output. → Y151 to Y159 are useless. This pin is internally pulled-up.(Rpu = 30 kΩ) Input the gamma corrected power supplies from external source. VDD2 ≥ VGMA1 > VGMA2 > ……… > VGMA10 > VGMA11 ≥ VSS2 Keep gray-scale power supply unchanged during the gray-scale voltage output. TESTB = H: Normal operation mode TESTB = L: Test mode (OP AMP CUT-OFF) This pin is internally pulled-up.(Rpu = 30kΩ) 7 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER OPERATION DESCRIPTION DISPLAY DATA TRANSFER When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 300 / 309 channels are loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the next rising edge of CLK2 after the falling edge of DIO1 (or DIO2). EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device. 8 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE The LCD drive output voltages are determined by the input data and 11 gamma corrected power supplies (VGMA1 - VGMA11). SHL = H OUTPUT Y1 Y3 Y2 ...... - First DATA D00 - D05 D10 - D15 D20 - D25 Y307 Y308 Y309 Last ...... D00 - D05 D10 - D15 D20 - D25 SHL = L OUTPUT Y1 Y3 Y2 ...... - Last DATA D00 - D05 D10 - D15 D20 - D25 Y307 Y308 Y309 First ...... D00 - D05 D10 - D15 D20 - D25 Figure 3. Relationship between Shift Direction and Output Data VDD2 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VGMA9 VGMA10 VGMA11 VSS2 00H 07H 0FH 17H 1FH 27H 2FH 37H 3FH Figure 4. Gamma Correction Curve 9 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER Table 2. Relationship between Input Data and Output Voltage Value: In case of using 11 levels of Gamma-corrected power supplies (VGMA1 to VGMA11) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA1 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 – VGMA3) × 6/7 01H VH1 0 0 0 0 1 0 VGMA3 + (VGMA2 – VGMA3) × 5/7 02H VH2 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 – VGMA3) × 4/7 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 – VGMA3) × 3/7 05H VH5 VGMA3 + (VGMA2 – VGMA3) × 2/7 0 0 0 1 0 1 06H VH6 VGMA3 + (VGMA2 – VGMA3) × 1/7 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VGMA4 + (VGMA3 – VGMA4) × 7/8 VGMA4 + (VGMA3 – VGMA4) × 6/8 VGMA4 + (VGMA3 – VGMA4) × 5/8 VGMA4 + (VGMA3 – VGMA4) × 4/8 VGMA4 + (VGMA3 – VGMA4) × 3/8 VGMA4 + (VGMA3 – VGMA4) × 2/8 VGMA4 + (VGMA3 – VGMA4) × 1/8 VGMA4 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VGMA5 + (VGMA4 – VGMA5) × 7/8 VGMA5 + (VGMA4 – VGMA5) × 6/8 VGMA5 + (VGMA4 – VGMA5) × 5/8 VGMA5 + (VGMA4 – VGMA5) × 4/8 VGMA5 + (VGMA4 – VGMA5) × 3/8 VGMA5 + (VGMA4 – VGMA5) × 2/8 VGMA5 + (VGMA4 – VGMA5) × 1/8 VGMA5 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA6 + (VGMA5 – VGMA6) × 7/8 VGMA6 + (VGMA5 – VGMA6) × 6/8 VGMA6 + (VGMA5 – VGMA6) × 5/8 VGMA6 + (VGMA5 – VGMA6) × 4/8 VGMA6 + (VGMA5 – VGMA6) × 3/8 VGMA6 + (VGMA5 – VGMA6) × 2/8 VGMA6 + (VGMA5 – VGMA6) × 1/8 VGMA6 NOTE: VDD2≥VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11≥ VSS2 10 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 – VGMA7) × 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 25H VH37 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 – VGMA8) × 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 – VGMA8) × 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 – VGMA8) × 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 – VGMA8) × 4/8 2CH VH44 VGMA8 + (VGMA7 – VGMA8) × 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 – VGMA8) × 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 – VGMA8) × 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 – VGMA9) × 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 – VGMA9) × 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 – VGMA9) × 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 – VGMA9) × 4/8 34H VH52 VGMA9 + (VGMA8 – VGMA9) × 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 – VGMA9) × 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 – VGMA9) × 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 – VGMA10) × 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 – VGMA10) × 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 – VGMA10) × 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 – VGMA10) × 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 – VGMA10) × 2/7 3DH VH61 VGMA10 + (VGMA9 – VGMA10) × 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA1 equals 1) RGMA1 1.00 RGMA6 0.84 RGMA2 2.00 RGMA7 0.66 RGMA3 2.77 RGMA8 0.84 RGMA4 1.50 RGMA9 1.42 0.90 RGMA10 1.05 RGMA5 RGMA1 = 2.31 kΩ 11 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER Table 3. Relationship between Input Data and Output Voltage Value: In case of using 10 levels of Gamma-corrected power supplies (VGMA1 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA2 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 – VGMA3) × 6/7 01H VH1 0 0 0 0 1 0 VGMA3 + (VGMA2 – VGMA3) × 5/7 02H VH2 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 – VGMA3) × 4/7 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 – VGMA3) × 3/7 05H VH5 VGMA3 + (VGMA2 – VGMA3) × 2/7 0 0 0 1 0 1 06H VH6 VGMA3 + (VGMA2 – VGMA3) × 1/7 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VGMA4 + (VGMA3 – VGMA4) × 7/8 VGMA4 + (VGMA3 – VGMA4) × 6/8 VGMA4 + (VGMA3 – VGMA4) × 5/8 VGMA4 + (VGMA3 – VGMA4) × 4/8 VGMA4 + (VGMA3 – VGMA4) × 3/8 VGMA4 + (VGMA3 – VGMA4) × 2/8 VGMA4 + (VGMA3 – VGMA4) × 1/8 VGMA4 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VGMA5 + (VGMA4 – VGMA5) × 7/8 VGMA5 + (VGMA4 – VGMA5) × 6/8 VGMA5 + (VGMA4 – VGMA5) × 5/8 VGMA5 + (VGMA4 – VGMA5) × 4/8 VGMA5 + (VGMA4 – VGMA5) × 3/8 VGMA5 + (VGMA4 – VGMA5) × 2/8 VGMA5 + (VGMA4 – VGMA5) × 1/8 VGMA5 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA6 + (VGMA5 – VGMA6) × 7/8 VGMA6 + (VGMA5 – VGMA6) × 6/8 VGMA6 + (VGMA5 – VGMA6) × 5/8 VGMA6 + (VGMA5 – VGMA6) × 4/8 VGMA6 + (VGMA5 – VGMA6) × 3/8 VGMA6 + (VGMA5 – VGMA6) × 2/8 VGMA6 + (VGMA5 – VGMA6) × 1/8 VGMA6 NOTE: VDD2≥VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11≥ VSS2 12 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Table 3. Relationship between Input Data and Output Voltage Value (Continued) Input data G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 – VGMA7) × 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 25H VH37 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 – VGMA8) × 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 – VGMA8) × 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 – VGMA8) × 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 – VGMA8) × 4/8 2CH VH44 VGMA8 + (VGMA7 – VGMA8) × 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 – VGMA8) × 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 – VGMA8) × 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 – VGMA9) × 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 – VGMA9) × 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 – VGMA9) × 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 – VGMA9) × 4/8 34H VH52 VGMA9 + (VGMA8 – VGMA9) × 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 – VGMA9) × 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 – VGMA9) × 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 – VGMA10) × 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 – VGMA10) × 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 – VGMA10) × 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 – VGMA10) × 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 – VGMA10) × 2/7 3DH VH61 VGMA10 + (VGMA9 – VGMA10) × 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the RGMA2 equals 1) RGMA1 - RGMA6 0.42 RGMA2 1.00 RGMA7 0.33 RGMA3 1.39 RGMA8 0.42 RGMA4 0.75 RGMA9 0.71 RGMA5 RGMA1 = 4.62 kΩ 0.45 RGMA10 0.53 13 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER Table 4. Relationship between Input Data and Output Voltage Value: In case of using 10 levels of Gamma-corrected power supplies (VGMA2 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA3 + (VGMA2 – VGMA3) × 7/8 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 – VGMA3) × 6/8 01H VH1 0 0 0 0 1 0 02H VH2 VGMA3 + (VGMA2 – VGMA3) × 5/8 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 – VGMA3) × 4/8 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 – VGMA3) × 3/8 05H VH5 0 0 0 1 0 1 VGMA3 + (VGMA2 – VGMA3) × 2/8 06H VH6 VGMA3 + (VGMA2 – VGMA3) × 1/8 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VGMA4 + (VGMA3 – VGMA4) × 7/8 VGMA4 + (VGMA3 – VGMA4) × 6/8 VGMA4 + (VGMA3 – VGMA4) × 5/8 VGMA4 + (VGMA3 – VGMA4) × 4/8 VGMA4 + (VGMA3 – VGMA4) × 3/8 VGMA4 + (VGMA3 – VGMA4) × 2/8 VGMA4 + (VGMA3 – VGMA4) × 1/8 VGMA4 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VGMA5 + (VGMA4 – VGMA5) × 7/8 VGMA5 + (VGMA4 – VGMA5) × 6/8 VGMA5 + (VGMA4 – VGMA5) × 5/8 VGMA5 + (VGMA4 – VGMA5) × 4/8 VGMA5 + (VGMA4 – VGMA5) × 3/8 VGMA5 + (VGMA4 – VGMA5) × 2/8 VGMA5 + (VGMA4 – VGMA5) × 1/8 VGMA5 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA6 + (VGMA5 – VGMA6) × 7/8 VGMA6 + (VGMA5 – VGMA6) × 6/8 VGMA6 + (VGMA5 – VGMA6) × 5/8 VGMA6 + (VGMA5 – VGMA6) × 4/8 VGMA6 + (VGMA5 – VGMA6) × 3/8 VGMA6 + (VGMA5 – VGMA6) × 2/8 VGMA6 + (VGMA5 – VGMA6) × 1/8 VGMA6 NOTE: VDD2≥VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11≥ VSS2 14 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Table 4. Relationship between Input Data and Output Voltage Value (Continued) Input data G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 – VGMA7) × 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 25H VH37 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 – VGMA8) × 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 – VGMA8) × 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 – VGMA8) × 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 – VGMA8) × 4/8 2CH VH44 VGMA8 + (VGMA7 – VGMA8) × 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 – VGMA8) × 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 – VGMA8) × 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 – VGMA9) × 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 – VGMA9) × 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 – VGMA9) × 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 – VGMA9) × 4/8 34H VH52 VGMA9 + (VGMA8 – VGMA9) × 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 – VGMA9) × 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 – VGMA9) × 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA10 + (VGMA9 – VGMA10) × 6/7 38H VH56 1 1 1 0 0 1 VGMA10 + (VGMA9 – VGMA10) × 5/7 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA10 + (VGMA9 – VGMA10) × 4/7 1 1 1 0 1 1 3BH VH59 VGMA10 + (VGMA9 – VGMA10) × 3/7 3CH VH60 1 1 1 1 0 0 VGMA10 + (VGMA9 – VGMA10) × 2/7 3DH VH61 VGMA10 + (VGMA9 – VGMA10) × 1/7 1 1 1 1 0 1 3EH VH62 VGMA10 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1) RGMA1 RGMA2 1.00 RGMA6 0.37 RGMA7 0.29 RGMA3 1.21 RGMA8 0.37 RGMA4 0.66 RGMA9 0.62 RGMA5 RGMA1 + RGMA2 = 5.28 kΩ 0.39 RGMA10 0.46 15 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER Table 5. Relationship between Input Data and Output Voltage Value: In case of using 9 levels of Gamma-corrected power supplies (VGMA2, VGMA10 = OPEN) G/S Output voltage Input data DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 VGMA3 + (VGMA2 – VGMA3) × 7/8 00H VH0 0 0 0 0 0 1 VGMA3 + (VGMA2 – VGMA3) × 6/8 01H VH1 0 0 0 0 1 0 02H VH2 VGMA3 + (VGMA2 – VGMA3) × 5/8 0 0 0 0 1 1 03H VH3 VGMA3 + (VGMA2 – VGMA3) × 4/8 04H 0 0 0 1 0 0 VH4 VGMA3 + (VGMA2 – VGMA3) × 3/8 05H VH5 0 0 0 1 0 1 VGMA3 + (VGMA2 – VGMA3) × 2/8 06H VH6 VGMA3 + (VGMA2 – VGMA3) × 1/8 0 0 0 1 1 0 07H VH7 VGMA3 0 0 0 1 1 1 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VH8 VH9 VH10 VH11 VH12 VH13 VH14 VH15 VGMA4 + (VGMA3 – VGMA4) × 7/8 VGMA4 + (VGMA3 – VGMA4) × 6/8 VGMA4 + (VGMA3 – VGMA4) × 5/8 VGMA4 + (VGMA3 – VGMA4) × 4/8 VGMA4 + (VGMA3 – VGMA4) × 3/8 VGMA4 + (VGMA3 – VGMA4) × 2/8 VGMA4 + (VGMA3 – VGMA4) × 1/8 VGMA4 VH16 VH17 VH18 VH19 VH20 VH21 VH22 VH23 VGMA5 + (VGMA4 – VGMA5) × 7/8 VGMA5 + (VGMA4 – VGMA5) × 6/8 VGMA5 + (VGMA4 – VGMA5) × 5/8 VGMA5 + (VGMA4 – VGMA5) × 4/8 VGMA5 + (VGMA4 – VGMA5) × 3/8 VGMA5 + (VGMA4 – VGMA5) × 2/8 VGMA5 + (VGMA4 – VGMA5) × 1/8 VGMA5 VH24 VH25 VH26 VH27 VH28 VH29 VH30 VH31 VGMA6 + (VGMA5 – VGMA6) × 7/8 VGMA6 + (VGMA5 – VGMA6) × 6/8 VGMA6 + (VGMA5 – VGMA6) × 5/8 VGMA6 + (VGMA5 – VGMA6) × 4/8 VGMA6 + (VGMA5 – VGMA6) × 3/8 VGMA6 + (VGMA5 – VGMA6) × 2/8 VGMA6 + (VGMA5 – VGMA6) × 1/8 VGMA6 NOTE: VDD2≥VGMA1>VGMA2>VGMA3>VGMA4>VGMA5>VGMA6>VGMA7>VGMA8>VGMA9>VGMA10>VGMA11≥ VSS2 16 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 Table 5. Relationship between Input Data and Output Voltage Value (Continued) Input data G/S Output voltage DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 20H VH32 0 0 0 0 1 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 21H VH33 0 0 0 1 0 1 22H VH34 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 0 1 1 1 23H VH35 VGMA7 + (VGMA6 – VGMA7) × 7/8 24H VH36 0 0 1 0 0 1 VGMA7 + (VGMA6 – VGMA7) × 7/8 25H VH37 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 0 1 1 26H VH38 VGMA7 + (VGMA6 – VGMA7) × 7/8 0 0 1 1 0 1 27H VH39 VGMA7 0 0 1 1 1 1 1 0 1 0 0 0 VGMA8 + (VGMA7 – VGMA8) × 7/8 28H VH40 1 0 1 0 0 1 VGMA8 + (VGMA7 – VGMA8) × 6/8 29H VH41 1 0 1 0 1 0 VGMA8 + (VGMA7 – VGMA8) × 5/8 2AH VH42 1 0 1 0 1 1 2BH VH43 VGMA8 + (VGMA7 – VGMA8) × 4/8 2CH VH44 VGMA8 + (VGMA7 – VGMA8) × 3/8 1 0 1 1 0 0 2DH VH45 VGMA8 + (VGMA7 – VGMA8) × 2/8 1 0 1 1 0 1 2EH VH46 VGMA8 + (VGMA7 – VGMA8) × 1/8 1 0 1 1 1 0 2FH VH47 VGMA8 1 0 1 1 1 1 1 1 0 0 0 0 VGMA9 + (VGMA8 – VGMA9) × 7/8 30H VH48 1 1 0 0 0 1 VGMA9 + (VGMA8 – VGMA9) × 6/8 31H VH49 1 1 0 0 1 0 VGMA9 + (VGMA8 – VGMA9) × 5/8 32H VH50 1 1 0 0 1 1 33H VH51 VGMA9 + (VGMA8 – VGMA9) × 4/8 34H VH52 VGMA9 + (VGMA8 – VGMA9) × 3/8 1 1 0 1 0 0 35H VH53 VGMA9 + (VGMA8 – VGMA9) × 2/8 1 1 0 1 0 1 36H VH54 VGMA9 + (VGMA8 – VGMA9) × 1/8 1 1 0 1 1 0 37H VH55 VGMA9 1 1 0 1 1 1 1 1 1 0 0 0 VGMA11 + (VGMA9 – VGMA11) × 7/8 38H VH56 1 1 1 0 0 1 VGMA11 + (VGMA9 – VGMA11) × 6/8 39H VH57 1 1 1 0 1 0 3AH VH58 VGMA11 + (VGMA9 – VGMA11) × 5/8 1 1 1 0 1 1 3BH VH59 VGMA11 + (VGMA9 – VGMA11) × 4/8 3CH VH60 VGMA11 + (VGMA9 – VGMA11) × 3/8 1 1 1 1 0 0 3DH VH61 VGMA11 + (VGMA9 – VGMA11) × 2/8 1 1 1 1 0 1 3EH VH62 VGMA11 + (VGMA9 – VGMA11) × 1/8 1 1 1 1 1 0 3FH VH63 VGMA11 1 1 1 1 1 1 RGMA (Gamma-Corrected Resistance) Ratio. (if the sum of RGMA1 and RGMA2 equals 1) RGMA1 RGMA2 1.00 RGMA6 0.37 RGMA7 0.29 0.37 RGMA3 1.21 RGMA8 RGMA4 0.66 RGMA9 RGMA5 RGMA1 + RGMA2 = 5.28 kΩ 0.39 RGMA10 0.71 17 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER ABSOLUTE MAXIMUM RATINGS Table 6. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Logic supply voltage VDD1 -0.3 to 6.5 Driver supply voltage VDD2 -0.3 to 6.5 VGMA1 - 10 -0.3 to VDD2 + 0.3 Others -0.3 to VDD1 + 0.3 DIO1, 2 -0.3 to VDD1 + 0.3 Y1 - Y309 -0.3 to VDD2 + 0.3 Operation temperature Topr -20 to 75 Storage temperature Tstg -55 to 125 Input voltage Output voltage Unit V °C CAUTIONS: If LSIs are stressed beyond those listed above “absolute maximum ratings” , they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 - VGMA11 Turn off power order: VGMA1 - VGMA11 → VDD2 → control signal input → VDD1 RECOMMENDED OPERATION CONDITIONS Table 7. Recommended Operation Conditions (Ta = -20 to 75 °C, VSS1 = VSS2 = 0 V) 18 Parameter Symbol Min. Typ. Max. Unit Logic supply voltage VDD1 3.0 3.3 5.5 V Driver supply voltage VDD2 3.0 5.0 5.5 V Gamma corrected voltage VGMA1 – VGMA11 VSS2 - VDD2 V Maximum clock frequency fmax 55 MHz Output load capacitance CL 150 pF / PIN VDD1 = 3.3 V - - 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 DC CHARACTERISTICS Table 8. DC Characteristics (Ta = -20 to 75 °C, VDD1 = 3.0 to 5.5 V, VDD2 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol High level input voltage VIH Condition SHL, CLK2, D00 – D25, CLK1, DIO1 (DIO2) Min. Typ. Max. 0.7 VDD1 - VDD1 0 - 0.3 VDD1 -0.5 - 0.5 Low level input voltage VIL Input leakage current IL High level output voltage VOH DIO1 (DIO2), VDD1=3.3V IO = -1.0 mA VDD1 - 0.5 - - Low level output voltage VOL DIO1 (DIO2), VDD1=3.3V IO = +1.0 mA - - 0.5 Resistor R0 - R62 Unit V µA V Rn × 0.7 Rn × 1.3 Ω IVOH VDD2 = 5.0 V, Vx = 3.5 V, Vyo = 4.5 V - -1.5 -0.5 mA IVOL VDD2 = 5.0 V, Vx = 1.5 V, Vyo = 0.5 V 0.5 0.5 - mA Output voltage deviation ∆VO VSS2 + 0.2 V to VDD2 - 1.5 V - ±10 ±20 mV Output voltage range Vyo Input data: 00H to 3FH VSS2 + 0.2 - VDD2 - 0.2 V Logic part dynamic current IDD1 VDD1 = 3.0 V (2) - 3.5 5.5 mA IDD2 VDD1 = 3.0 V, VDD2 = 5.0 V, VGMA1 = 4.5 V, VGMA11 = 0.5 V - 5.5 7.0 Driver output current Driver part dynamic current NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y309. Vx is the voltage applied to analog output pins Y1 to Y309. 2. CLK1 period is defined to be 30 µs at fCLK2 = 30 MHz, data pattern = 101010 , (checkerboard pattern), Ta = 25 °C 19 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER AC CHARACTERISTICS Table 9. AC Characteristics (Ta = -20 to 75 °C, VDD2 = 3.0 to 5.5 V, VDD1 = 3.0 to 5.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Min. Typ. Max. Clock pulse width PWCLK - 18 - - Clock pulse low period PWCLK(L) - 4 - - Clock pulse high period PWCLK(H) - 4 - - tSETUP1 (1) 4 - - Data hold time tHOLD1 (1) 0 - - Start pulse setup time tSETUP2 (1) 4 - - Start pulse hold time tHOLD2 (1) 0 - - Start pulse delay time tPLH1 VDD1 = 3.3 V CL = 35 pF - - 14 CLK1 setup time tSETUP3 - 1 - - Driver output delay time1 tPHL1 (2) - - 3 Driver output delay time2 tPHL2 (3) - - 10 CLK1 pulse high period PWCLK1 - 2 - - Data invalid period tINV DIO1 (2) ↑ → CLK2↑ Last data timing tLDT - 0 - - ns CLK1-CLK2 time tCLK1–CLK2 CLK1↑ → CLK2↑ 6 - - ns Data setup time ns CLK2 period µs CLK2 period CLK2 period 1 NOTES: 1. Input condition (VIH = 0.7 VDD1, VIL = 0.3 VDD1) 2. The value is specified when the drive voltage value reaches the target output voltage level of 90% 3. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. 20 Unit CLK1 CLK2 DXX CLK1 CLK2 Y(1:309) CLK1 DIO2 output (DIO1 output) DIO1 input (DIO2 input) DXX CLK2 tSETUP3 tSETUP2 INVALID DATA PWCLK 1st LAST DATA tHOLD1 PWCLK(L) tSETUP1 0.5VDD1 tLDT PWCLK1 tHOLD2 tSETUP1 1st DATA tINV PWCLK(H) Target output voltage Target output voltage 90% tPLH1 LAST-1 LAST INVALID DATA tPHL2 tCLK1-CLK2 tHOLD1 tPHL1 VIH VIL 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER S6C0641 WAVEFORMS Figure 5. Waveforms 21 22 Figure 6. Waveforms Y (1:309) CLK1 CLK2 DXX CLK1 Last data N-1th DATA 1CLK2(Max.) DIO1 input (DIO2 input) CLK2 Nth DATA 0.5VDD1 Hold HI-Z blanking time = Min. 3CLK2 INVALID DATA 1CLK2(Min.) First data in the next line 2nd DATA Analog output 1st DATA 1CLK2 S6C0641 6 BIT 300 / 309 CHANNEL TFT-LCD SOURCE DRIVER RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD