. KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER August. 1999. Ver. 0.0 Prepared by: Myoung-Sik, Suh mail to: [email protected] Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 Specification Revision History Version 0.0 2 Content Original Date Aug.1999 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 CONTENTS INTRODUCTION ................................................................................................................................................. 4 FEATURES ......................................................................................................................................................... 4 BLOCK DIAGRAM .............................................................................................................................................. 5 PIN ASSIGNMENTS............................................................................................................................................ 6 PIN DESCRIPTIONS........................................................................................................................................... 7 OPERATION DESCRIPTION .............................................................................................................................. 8 DISPLAY DATA TRANSFER............................................................................................................................ 8 EXTENSION OF OUTPUT ............................................................................................................................... 8 RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE................................................. 8 ABSOLUTE MAXIMUM RATINGS .................................................................................................................... 14 RECOMMENDED OPERATION CONDITIONS ................................................................................................. 14 DC CHARACTERISTICS................................................................................................................................... 15 SINGLE EDGE AC CHARACTERISTICS.......................................................................................................... 16 DOUBLE EDGE AC CHARACTERISTICS ........................................................................................................ 17 SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) ................................................................... 18 DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1).................................................................. 19 RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD....................... 20 3 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER INTRODUCTION The KS0670 is a 384 / 402 channel output, TFT-LCD source driver for an 256 gray scale LCD panel. Data input is based on digital input consisting of 8 bits by 6 dots, which can realize a full-color display of 16,700,000 color by output of 256 values gamma-corrected. This device has an internal D/A (Digital-to-Analog) converter for each output and 16 (8-by-2) reference voltages. Because the output dynamic range is as large as 7.8 - 14.8 Vp-p, it is unnecessary to operate level inversion of the LCD's common electrode. Besides, to be able to deal with dot-line inversion when mounted on a single-side, output gray scale voltages with different polarity can be output to the odd number output pins and the even output pins. KS0670 can be adopted to larger panel, and SHL (shift direction selection) pin makes the use of the LCD panel connection conveniently. Maximum operation clock frequency is 75 MHz at 3.0 V logic operation, single edge and it can be applied to the TFT-LCD panel of UXGA standard. FEATURES • TFT active matrix LCD source driver LSI • 256G/S is possible through 16 (8 by 2) reference voltages and D/A converter • Both dot inversion display and N-line inversion display are possible • CMOS level input • Compatible with gamma-correction • Input data inversion function (DATPOL1,2) • Single edge, Double edge compatible (DEC) • Logic supply voltage: 2.5 - 3.6 V • LCD driver supply voltage: 8.0 - 15.0 V • Output dynamic range: 7.8 - 14.8 Vp-p • Maximum operating frequency: fMAX = 75 MHz (internal data transmission rate at 3.0 V operation, single edge) • Output: 384 / 402 outputs • TCP 4 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 Y001 Y002 Y003 Y400 Y401 Y402 BLOCK DIAGRAM Output Buffer BIAS TEST POL VGMA1 VGMA16 D/A Converter 16 8 8 8 8 8 8 8 8 Data Latch CLK1 8 8 8 DATPOL1 DATPOL2 Data Register 8 D10 - D17 8 D20 - D27 8 D30 - D37 8 D40 - D47 8 D50 - D57 8 24 Data Control D00 - D07 CLK2 8 24 67bit Shift Register DIO2 SHL SELT DEC DIO1 Figure 1. KS0670 Block Diagram 5 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER PIN ASSIGNMENTS Y001 Y002 Y003 (Top View) KS0670 Y004 Y399 Y400 Y401 Y402 Figure 2. KS0670 Pin Assignments 6 DIO1 D00 D01 D02 D03 D04 D05 D06 D07 D10 D11 D12 D13 D14 D15 D16 D17 D20 D21 D22 D23 D24 D25 D26 D27 TEST DATPOL1 DATPOL2 POL CLK1 CLK2 DEC VSS1 VGMA1 VGMA2 VGMA3 VGMA4 VGMA5 VGMA6 VGMA7 VGMA8 VSS2 VDD2 VGMA9 VGMA10 VGMA11 VGMA12 VGMA13 VGMA14 VGMA15 VGMA16 SELT SHL VDD1 D30 D31 D32 D33 D34 D35 D36 D37 D40 D41 D42 D43 D44 D45 D46 D47 D50 D51 D52 D53 D54 D55 D56 D57 DIO2 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 PIN DESCRIPTIONS Symbol VDD1 VDD2 VSS1 VSS2 Y1 - Y402 D0<0:7> - D5<0:7> Pin Name Logic power supply Driver power supply Logic ground Driver ground Driver outputs Description 2.5 - 3.6 V 8.0 - 15.0 V Ground (0 V) Ground (0 V) The D/A converted 256 gray-scale analog voltage is output. The display data is input with a width of 48 bits, Display data input gray-scale data (8 bits) by 6 dots (R,G,B) DX0: LSB, DX7: MSB This pin controls the direction of shift register in cascade connection. Shift direction control The shift direction of the shift registers is as follows. SHL input SHL = H: DIO1 input, Y1 → Y402, DIO2 output SHL = L: DIO2 input, Y402 → Y1, DIO1 output SHL = H: Used as the start pulse input pin. DIO1 Start pulse input/output SHL = L: Used as the start pulse output pin. SHL = H: Used as the start pulse output pin. DIO2 Start pulse input/output SHL = L: Used as the start pulse input pin. DATPOL1,2 = L: Display data is not inverted DATPOL1 Data inversion input DATPOL1 = H: Display data of D0<0:7> - D2<0:7> is inverted DATPOL2 DATPOL2 = H: Display data of D3<0:7> - D5<0:7> is inverted POL = H: The reference voltage for odd number outputs are VGMA9 – VGMA16 and those for even number outputs are VGMA1 – VGMA8. POL Polarity input POL = L: The reference voltage for odd number outputs are VGMA1 – VGMA8 and those for even number outputs are VGMA9 – VGMA16. Refer to the shift register's shift clock input. When DEC is Low, the display data is loaded to the data register at the rising edge of CLK2 Shift clock input CLK2.When DEC is High, the display data is loaded to the data register at the rising and falling edge of CLK2. Latches the contents of the data register at rising edge and transfers them to the D/A converter. Also, after CLK1 input, clears the internal shift register contents. After 1 pulse input on start, operates normally. CLK1 Latch input CLK1 input timing refers to the "Relationships between CLK1 start pulse (DIO1, DIO2) and blanking period" of the switching characteristic waveform. Outputs the G/S data at falling edge. Input the gamma corrected power supplies from external source. VGMA1 Gamma corrected power VDD2 > VGMA1 > VGMA2 > …… > VGMA15 > VGMA16 > VSS2 – supplies Keep gray-scale power supply unchanged during the gray-scale VGMA16 voltage output. SELT = L: 384 Output (Y193 - Y210 are disabled), SELT = H: 402 SELT Output selection input Output DEC = L: Single Edge, the display data is loaded to the data register at Double edge selection DEC the rising edge of CLK2. DEC = H: Double Edge, the display data is input loaded to the data register at the rising and falling edge of CLK2. TEST = L: Normal operation mode TEST Test input TEST = H: Test mode (OP AMP CUT-OFF, Rpd = 10kΩ) 7 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER OPERATION DESCRIPTION DISPLAY DATA TRANSFER (1) DEC = ”L” When DIO1 (or DIO2) pulse is loaded into internal latch on the rising edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer, so display data is valid on the next rising edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd rising edge of CLK2 after the rising edge of DIO1 (or DIO2). (2) DEC = ”H” When DIO1 (or DIO2) pulse is loaded into internal latch on the rising (or falling) edge of CLK2, DIO1 (or DIO2) pulse enables the operation of data transfer. display data is valid on the next falling (or rising) edge of CLK2. Once all the data of 402 (or 384) channels is loaded into internal latch, it goes into stand-by state automatically, and any new data is not accepted even though CLK2 is provided until next DIO1 (or DIO2) input. When next DIO1 (or DIO2) is provided, new display data is valid on the 2nd edge of CLK2 after the rising edge of DIO1 (or DIO2). EXTENSION OF OUTPUT Output pin can be adjusted to an extended screen by cascade connection. (1) SHL = "L" Connect DIO1 pin of previous stage to the DIO2 pin of next stage and all the input pins except DIO1 and DIO2 are connected together in each device. (2) SHL = "H" Connect DIO2 pin of previous stage to the DIO1 pin of next stage and all the input pins except DIO2 and DIO1 are connected together in each device. RELATIONSHIP BETWEEN INPUT DATA VALUE AND OUTPUT VOLTAGE The LCD drive output voltages are determined by the input data and 16 (8 by 2) gamma corrected power supplies (VGMA1 - VGMA16). Besides, to be able to deal with dot line inversion when mounted on a single-side, gradation voltages with different polarity can be output to the odd number output pins and the even number output pins. Among 8-by-2 gamma corrected voltages, input gray-scale voltages of the same polarity with respect to the common voltage, for the respective 8 gamma corrected voltages of VGMA1 - VGMA8 and VGMA9 - VGMA16. 8 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 SHL = H OUTPUT Y1 Y2 - Y3 ...... Y400 First DATA Y401 Y402 Last D00 - D07 D10 - D17 D20 - D27 ...... D30 - D37 D40 - D47 D50 - D57 Y1 Y2 Y3 ...... Y400 Y401 Y402 SHL = L OUTPUT DATA Last D00 - D07 D10 - D17 First D20 - D27 ...... D30 - D37 D40 - D47 D50 - D57 Figure 3. Relationship between Shift Direction and Output Data VDD2 VGMA1 32 VGMA2 32 VGMA3 VGMA4 VGMA5 128 48 VGMA6 14 VGMA7,8 VGMA9,10 VCOM 14 VGMA11 48 VGMA12 VGMA13 VGMA14 128 32 VGMA15 32 VGMA16 VSS2 00H 20H 40H 60H 80H A0H C0H E0H FFH Figure 4. Gamma Correction Curve 9 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER Table 1. Resistor Strings (R0 - R254, unit: Ω ) 10 Name Value Name Value Name Value Name Value R0 218 R32 70 R64 32 R96 32 R1 218 R33 70 R65 32 R97 32 R2 218 R34 70 R66 32 R98 32 R3 218 R35 70 R67 32 R99 32 R4 218 R36 70 R68 32 R100 32 R5 218 R37 70 R69 32 R101 32 R6 218 R38 70 R70 32 R102 32 R7 218 R39 70 R71 32 R103 32 R8 218 R40 70 R72 32 R104 32 R9 218 R41 70 R73 32 R105 32 R10 218 R42 70 R74 32 R106 32 R11 218 R43 70 R75 32 R107 32 R12 218 R44 70 R76 32 R108 32 R13 218 R45 70 R77 32 R109 32 R14 218 R46 70 R78 32 R110 32 R15 218 R47 70 R79 32 R111 32 R16 218 R48 70 R80 32 R112 32 R17 218 R49 70 R81 32 R113 32 R18 218 R50 70 R82 32 R114 32 R19 218 R15 70 R83 32 R115 32 R20 218 R52 70 R84 32 R116 32 R21 218 R53 70 R85 32 R117 32 R22 218 R54 70 R86 32 R118 32 R23 218 R55 70 R87 32 R119 32 R24 218 R56 70 R88 32 R120 32 R25 218 R57 70 R89 32 R121 32 R26 218 R58 70 R90 32 R122 32 R27 218 R59 70 R91 32 R123 32 R28 218 R60 70 R92 32 R124 32 R29 218 R61 70 R93 32 R125 32 R30 218 R62 70 R94 32 R126 32 R31 218 R63 70 R95 32 R127 32 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 Table 1. Resistor Strings (R0 - R254, unit: Ω ) (Continued) Name Value Name Value Name Value Name Value R128 32 R160 32 R192 50 R224 50 R129 32 R161 32 R193 50 R225 50 R130 32 R162 32 R194 50 R226 50 R131 32 R163 32 R195 50 R227 50 R132 32 R164 32 R196 50 R228 50 R133 32 R165 32 R197 50 R229 50 R134 32 R166 32 R198 50 R230 50 R135 32 R167 32 R199 50 R231 50 R136 32 R168 32 R200 50 R232 50 R137 32 R169 32 R201 50 R233 50 R138 32 R170 32 R202 50 R234 50 R139 32 R171 32 R203 50 R235 50 R140 32 R172 32 R204 50 R236 50 R141 32 R173 32 R205 50 R237 50 R142 32 R174 32 R206 50 R238 50 R143 32 R175 32 R207 50 R239 50 R144 32 R176 32 R208 50 R240 200 R145 32 R177 32 R209 50 R241 200 R146 32 R178 32 R210 50 R242 200 R147 32 R179 32 R211 50 R243 200 R148 32 R180 32 R212 50 R244 200 R149 32 R181 32 R213 50 R245 200 R150 32 R182 32 R214 50 R246 200 R151 32 R183 32 R215 50 R247 200 R152 32 R184 32 R216 50 R248 200 R153 32 R185 32 R217 50 R249 200 R154 32 R186 32 R218 50 R250 200 R155 32 R187 32 R219 50 R251 200 R156 32 R188 32 R220 50 R252 200 R157 32 R189 32 R221 50 R253 200 R158 32 R190 32 R222 50 R254 930 R159 32 R191 32 R223 50 11 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER Table 2. Relationship between Input Data and Output Voltage Value Input data 00H 01H : 18H : 1FH 20H 21H : 28H 29H : 3FH 40H 41H : 60H 61H : 7FH 80H 81H : A0H A1H : BFH C0H C1H : D8H D9H : EFH F0H F1H : F9H : FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 : 1 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 1 1 : 0 1 1 : 1 : 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 G/S Output voltage VH0 VH1 : VH24 : VH31 VH32 VGMA1 VGMA1 + (VGMA2 - VGMA1) × 218 / 6976 : VGMA1 + (VGMA2 - VGMA1) × (218 × 24) / 6976 : VGMA1 + (VGMA2 - VGMA1) × (218 × 31) / 6976 VGMA2 VH33 : VH40 VH41 : VH63 VH64 VGMA2 + (VGMA3 - VGMA2) × (70 × 1) / 2240 : VGMA2 + (VGMA3 - VGMA2) × (70 × 8) / 2240 VGMA2 + (VGMA3 - VGMA2) × (70 × 9) / 2240 : VGMA2 + (VGMA3 - VGMA2) × (70 × 31) / 2240 VGMA3 VH65 : VH96 VH97 : VH127 VH128 VGMA3 + (VGMA4 - VGMA3) × (32 × 1) / 2048 : VGMA3 + (VGMA4 - VGMA3) × (32 × 32) / 2048 VGMA3 + (VGMA4 - VGMA3) × (32 × 33) / 2048 : VGMA3 + (VGMA4 – VGMA3) × (32 × 63) / 2048 VGMA4 VH129 : VH160 VH161 : VH191 VH192 VGMA4 + (VGMA5 - VGMA4) × (32 × 1) / 2048 : VGMA4 + (VGMA5 - VGMA4) × (32 × 32) / 2048 VGMA4 + (VGMA5 - VGMA4) × (32 × 33) / 2048 : VGMA4 + (VGMA5 - VGMA4) × (32 × 63) / 2048 VGMA5 VH193 : VH216 VH217 : VH239 VH240 VGMA5 + (VGMA6 - VGMA5) × (50 × 1) / 2400 : VGMA5 + (VGMA6 - VGMA5) × (50 ×24) / 2400 VGMA5 + (VGMA6 - VGMA5) × (50 × 25) / 2400 : VGMA5 + (VGMA6 - VGMA5) × (50 × 47) / 2400 VGMA6 VH241 : VH249 : VH253 VH254 VH255 VGMA6 + (VGMA7 - VGMA6) × (200 × 1) / 2800 : VGMA6 + (VGMA7 – VGMA6) × (200 × 9) / 2800 : VGMA6 + (VGMA7 - VGMA6) × (200 × 13) / 2800 VGMA7 VGMA8 NOTE: VDD2 > VGMA1 > VGMA2 > VGMA3 > VGMA4 > VGMA5 > VGMA6 > VGMA7 > VGMA8 12 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 Table 2. Relationship between Input Data and Output Voltage Value (Continued) Input data 00H 01H : 18H : 1FH 20H 21H : 28H 29H : 3FH 40H 41H : 60H 61H : 7FH 80H 81H : A0H A1H : BFH C0H C1H : D8H D9H : EFH F0H F1H : F9H : FDH FEH FFH DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 : 1 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 0 0 : 1 0 0 : 1 1 : 0 1 1 : 1 : 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 0 1 G/S Output voltage VL0 VL1 : VL24 : VL31 VL32 VGMA16 VGMA16 + (VGMA15 - VGMA16) × (218 × 1) / 6976 : VGMA16 + (VGMA15 - VGMA16) × (218 × 24) / 6976 : VGMA16 + (VGMA15 - VGMA16) × (218 × 31) / 6976 VGMA15 VL33 : VL40 VL41 : VL63 VL64 VGMA15 + (VGMA14 - VGMA15) × (70 × 1) / 2240 : VGMA15 + (VGMA14 - VGMA15) × (70 × 8) / 2240 VGMA15 + (VGMA14 - VGMA15) × (70 × 9) / 2240 : VGMA15 + (VGMA14 - VGMA15) × (70 × 31) / 2240 VGMA14 VL65 : VL96 VL97 : VL127 VL128 VGMA14 + (VGMA13 - VGMA14) × (32 × 1) / 2048 : VGMA14 + (VGMA13 - VGMA14) × (32 × 32) / 2048 VGMA14 + (VGMA13 - VGMA14) × (32 × 33) / 2048 : VGMA14 + (VGMA13 - VGMA14) × (32 × 63) / 2048 VGMA13 VL129 : VL160 VL161 : VL191 VL192 VGMA13 + (VGMA12 - VGMA13) × (32 × 1) / 2048 : VGMA13 + (VGMA12 - VGMA13) × (32 × 32) / 2048 VGMA13 + (VGMA12 - VGMA13) × (32 × 33) / 2048 : VGMA13 + (VGMA12 - VGMA13) × (32 × 63) / 2048 VGMA12 VL193 : VL216 VL217 : VL239 VL240 VGMA12 + (VGMA11 - VGMA12) × (50 × 1) / 2400 : VGMA12 + (VGMA11 - VGMA12) × (50 × 24) / 2400 VGMA12 + (VGMA11 - VGMA12) × (50 × 25) / 2400 : VGMA12 + (VGM11 - VGMA12) × (50 × 47) / 2400 VGMA11 VL241 : VL249 : VL253 VL254 VL255 VGMA11 + (VGMA10 - VGMA11) × (200 × 1) / 2800 : VGMA11 + (VGMA10 - VGMA11) × (200 × 9) / 2800 : VGMA11 + (VGMA10 - VGMA11) × (200 × 13) / 2800 VGMA10 VGMA9 NOTE: VSS2 < VGMA16 < VGMA15 < VGMA14 < VGMA13 < VGMA12 < VGMA11 < VGMA10 < VGMA9 13 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER ABSOLUTE MAXIMUM RATINGS Table 3. Absolute Maximum Ratings (VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit Logic supply voltage VDD1 -0.3 to 5.0 V Driver supply voltage VDD2 -0.3 to 16 V VGMA1 - 16 -0.3 to VDD2+0.3 Others -0.3 to VDD1+0.3 DIO1, 2 -0.3 to VDD1+0.3 Y1 – Y402 -0.3 to VDD2+0.3 Operating power dissipation Pd 300 (1) mW Operation temperature Top -20 to 75 °C Storage temperature Tstg -55 to 125 °C Input voltage Output voltage V V CAUTIONS: If LSIs are stressed beyond those listed above “absolute maximum ratings”, they may be permanently destroyed. These are stress ratings only, and functional operation of the device at these or any other condition beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Turn on power order: VDD1 → control signal input → VDD2 → VGMA1 - VGMA16 Turn off power order: VGMA1 - VGMA16 → VDD2 → control signal input → VDD1 RECOMMENDED OPERATION CONDITIONS Table 4. Recommended Operation Conditions (Ta = -20 to 75 ° C, VSS1 = VSS2 = 0 V) Parameter Symbol Min. Typ. Max. Unit Logic supply voltage VDD1 2.5 3.3 3.6 V 8.0 12.0 15.0 V VGMA1 – VGMA8 0.5 VDD2 - VDD2 - 0.1 V VGMA9 – VGMA16 VSS2 + 0.1 - 0.5 VDD2 V Driver part output voltage Vyo VSS2 + 0.1 - VDD2 - 0.1 V Maximum clock frequency (Single edge/Double edge) fmax Driver supply voltage Gamma corrected voltage Output load capacitance VDD2 (1) (1) CL VDD1 = 2.5 V 55 / 40 VDD1 = 3.0 V 75 / 55 - - NOTE: 1. Relationship between TFT-LCD panel and Pd (Pd ∝ CL * (VDD2) * fCLK1) 2 14 TFT-LCD panel standard CL = 140pF CL = 200pF SXGA max. VDD2 = 15 V max. VDD2 = 13 V UXGA & WUXGA max. VDD2 = 14 V max. VDD2 = 12 V 200 MHz pF / PIN 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 DC CHARACTERISTICS Table 5. DC Characteristics (Ta = -20 to 75 ° C, VDD1 = 2.5 to 3.6 V, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition Min. Typ. Max. High level input voltage VIH 0.8 VDD1 - VDD1 Low level input voltage VIL 0 - 0.2 VDD1 Input leakage current IL SHL, CLK2, D00 - D57, CLK1, SELT, DATPOL1, DATPOL2, DEC, POL, DIO1 (DIO2) -1 - 1 High level output voltage VOH DIO1 (DIO2), IO = -1.0 mA VDD1 - 0.5 - - Low level output voltage VOL DIO1 (DIO2), IO = +1.0 mA - - 0.5 Resistor R0 R254 Refer to Table 1. Resistor Strings Rn × 0.7 IVOH VDD2 = 10.0 V, Vx = 3.5 V, Vyo = 9.5 V(1) - IVOL VDD2 = 10.0 V, Vx = 6.5 V, Vyo = 0.5 V(1) Driver output current Output voltage deviation ∆VO µA V Ω -2.0 -1.0 mA 1.0 2.0 - mA VSS2 + 0.1 V to VDD2 - 1.5 V - ±7 ±15 VDD2 - 1.5 V to VDD2 - 0.1 V - ±10 ±20 dVrms Input data: 00H to FFH - ±3 ±10 Output voltage range Vyo Input data: 00H to FFH VSS2 + 0.1 - VDD2 – 0.1 Logic part dynamic current IDD1 VDD1 = 3.0 V (3) - 4.0 7.0 IDD2 (4) Driver part dynamic current V Rn × 1.3 Output RMS voltage deviation (2) Unit mV V mA VDD2 = 10 V - 10.0 15.0 NOTES: 1. Vyo is the output voltage of analog output pins Y1 to Y402. Vx is the voltage applied to analog output pins Y1 to Y402. 2. dVrms is a maximum deviation value from ideal difference between high output and low output at the same gray scale. 3. CLK1 period is defined to be 15.6 µs at fCLK2 = 54 MHz, DEC = L, data pattern = 10101010 (checkerboard pattern), Ta = 25 °C. 4, Yout Load Condition 2kΩ 4kΩ 4kΩ YOUT 20pF VCOM = 0.5 VDD2 2kΩ 40pF 4kΩ 20pF 4kΩ Figure 5. Yout Load Condition 15 KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER SINGLE EDGE AC CHARACTERISTICS Table 6. AC Characteristics (Ta = -20 to 75 ° C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = L) Parameter Symbol Condition VDD1 = 2.5 to 3.0 V VDD1 = 3.0 to 3.6 V Min. Max. Min. Max. Unit Clock pulse width PWCLK - 18 - 13 - Clock pulse low period PWCLK(L) - 3 - 2 - Clock pulse high period PWCLK(H) - 3 - 2 - Data setup time tSETUP1 - 3 - 2 - Data hold time tHOLD1 - 0 - 0 - Start pulse setup time tSETUP2 - 3 - 2 - Start pulse hold time tHOLD2 - 0 - 0 - DATPOL-CLK2 setup time tSETUP4 - 3 - 2 - DATPOL-CLK2 hold time tHOLD4 - 0 - 0 - Start pulse delay time tPLH1 CL = 20 pF - 15 - 11 CLK1 setup time tSETUP3 - 2 - 2 - Driver output delay time1 tPHL1 - 4 - 4 Driver output delay time2 tPHL2 PWCLK1 = 1 µs, Refer Figure 5. Yout Load Condition - 8 - 8 CLK1 pulse high period PWCLK1 - 0.5 2 0.5 2 Data invalid period tINV - 1 - 1 - Last data timing tLDT - 1 - 1 - CLK2 period CLK1-CLK2 time tCLK1-CLK2 CLK1↑ or ↓ → CLK2↑ 8 - 6 - ns POL-CLK1 time tPOL-CLK1 POL↑ or ↓ → CLK1↑ 8 - 6 - ns 16 ns CLK2 period µs 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 DOUBLE EDGE AC CHARACTERISTICS Table 7. AC Characteristics (Ta = -20 to 75 ° C, VDD2 = 8 to 15 V, VSS1 = VSS2 = 0 V, DEC = H) Parameter Symbol Condition VDD1 = 2.5 to 3.0 V VDD1 = 3.0 to 3.6 V Min. Max. Min. Max. Unit Clock pulse width PWCLK - 25 - 18 - Clock pulse low period PWCLK(L) - 4 - 3 - Clock pulse high period PWCLK(H) - 4 - 3 - Data setup time tSETUP1 - 4 - 3 - Data hold time tHOLD1 - 0 - 0 - Start pulse setup time tSETUP2 - 4 - 3 - Start pulse hold time tHOLD2 - 0 - 0 - DATPOL-CLK2 setup time tSETUP4 - 4 - 3 - DATPOL-CLK2 hold time tHOLD4 - 0 - 0 - Start pulse delay time tPLH1 CL = 20 pF - 15 - 15 CLK1 setup time tSETUP3 - 1 - 1 - Driver output delay time1 tPHL1 - 4 - 4 Driver output delay time2 tPHL2 PWCLK1 = 1 µs , Figure 5. Yout Load Condition - 8 - 8 CLK1 pulse high period PWCLK1 - 0.5 2 0.5 2 Data invalid period tINV - 0.5 - 0.5 - Last data timing tLDT 1 - 1 - CLK2 period CLK1-CLK2 time tCLK1-CLK2 CLK1↑ or ↓ → CLK2↑ 8 - 6 - ns POL-CLK1 time tPOL-CLK1 POL↑ or ↓ → CLK1↑ 8 - 6 - ns ns CLK2 period µs 17 18 Figure 6. Waveforms, DEC = L POL tPOL-CLK1 LAST DATA tLDT tHOLD4 DXX HI-Z PWCLK1 tHOLD2 tSETUP4 tHOLD1 PWCLK(L) 0.5VDD1 tSETUP3 tSETUP2 INVALID DATA 1st tSETUP1 1st DATA tINV CLK1 CLK2 Y(1:402) CLK1 DIO2 output (DIO1 output) DIO1 input (DIO2 input) DATPOL1 DATPOL2 DXX CLK2 PWCLK tCLK1-CLK2 tPHL2 tPHL1 VIH VIL Target output voltage Target output voltage 90% tPLH1 LAST-1 LAST INVALID DATA PWCLK(H) KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER SINGLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) POL DXX CLK1 CLK2 Y(1:402) CLK1 DIO2 output (DIO1 output) DIO1 input (DIO2 input) DATPOL1 DATPOL2 DXX CLK2 tSETUP3 tSETUP2 INVALID DATA PWCLK 1st tPOL-CLK1 LAST DATA tLDT tHOLD1 LAST-2 Target output voltage Target output voltage 90% tPLH1 LAST PWCLK(L) LAST-1 INVALID DATA tCLK1-CLK2 tPHL2 tPHL1 PWCLK(H) VIH VIL 0.5VDD1 tHOLD4 tHOLD1 2nd tSETUP1 HI-Z PWCLK1 tHOLD2 tSETUP4 tSETUP1 1st DATA tINV 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER KS0670 DOUBLE EDGE WAVEFORMS (VIH = 0.8 VDD1, VIL = 0.2 VDD1) Figure 7. Waveforms, DEC = H 19 20 Figure 8. Waveforms Y2N:even number output Y2N-1:odd number output POL CLK1 DXX CLK1 DIO1 input (DIO2 input) CLK2 Nth DATA Last data N-1th DATA VGMA9 - VGMA16 VGMA1 - VGMA8 HI-Z VGMA1- VGMA8 VGMA9 - VGMA16 VGMA1 - VGMA8 HI-Z First data in the next line 2nd DATA 1/2CLK2 (DEC = H ) 1st DATA VGMA9 - VGMA16 HI-Z blanking time = Min. 4CLK2 INVALID DATA Charge sharing period tLDT 2CLK2(Min.) 0.5VDD1 HI-Z KS0670 8 BIT 384 / 402 CHANNEL TFT-LCD SOURCE DRIVER RELATIONSHIPS BETWEEN CLK1, START PULSE (DIO1, DIO2) AND BLANKING PERIOD