SANYO LA17000M

Ordering number: ENN6522
Monolithic Linear IC
LA17000M
Tuner System IC with Built-in PLL
for Car Audio Applications
Overview
Package Dimensions
The LA17000M is an all-in-one car tuner IC that incorporates a PLL frequency synthesizer and all functions of an
AM/FM tuner in a single chip. By combining two chips, a
PLL (LC72144 equivalent) and an FM tuner IC (LA1781M
equivalent) into a single chip (*PLL + AM (up conversion)
+ FMFE + IF + NC + MCP + MRC), and as a result of
optimal chip partitioning, the LA17000M improves the
performance of car tuner systems, eliminates adjustments,
and provides high reliability, all at a lower cost.
unit: mm
3255-QFP80
[LA17000M]
17.2
0.8
14.0
60
41
61
40
80
21
14.0
17.2
Features
• PLL on chip
• ADC (6 bits, 1 channel)
• IF counter and I/O port on chip permit simplification
of the interface.
• Supports AM double conversion.
0.65
0.25
20
0.15
(2.7)
0.1
3.0max
• Enhanced noise countermeasures
• Excellent tri-signal characteristics
• Improved medium and weak electric field NC
characteristics
• Improved separation characteristics
• Anti-birdie filter on chip (analog/digital output)
• Multipath sensor output (analog/digital output)
1
(0.83)
SANYO: QFP80 (14 x 14)
• Cost-saving features
• AM double conversion (Up conversion method)
• Enhanced FM-IF circuit
(When there is interference from adjacent frequencies,
the software handles switching of the CF between
wide and narrow automatically.)
• Because deviations in IF gain are only 1/3 that of
earlier devices, adjustment is simplified when this IC
is incorporated into a set; this IC also includes a shifter
pin for VSM adjustment.
• Suited for smaller devices
• Permits high-frequency signal line processing in a
tuner pack.
• Easily conformes to FCC standards
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
62901RM (II) No. 6522-1/54
LA17000M
Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Allowable power dissipation
Symbol
Conditions
VCC1 max
Pins 6, 56, and 77
VCC2 max
Pins 7, 61, 70, 75, and 76
VDD max
Pin 19
Pd max
Ratings
Ta ≤ 85°C, * With board
Unit
8.7
V
12.0
V
6.0
V
950
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–40 to 150
°C
Ratings
Unit
* Specified board: 114.3 × 76.1 × 1.6 mm3, glass epoxy
Operating Conditions at Ta = 25°C
Parameter
Recommended supply voltage
Operating supply voltage range
Symbol
Conditions
Pins 6, 7, 56, 61, 70, 75, 76, and 77
8.0
V
Pin 19
5.0
V
VCC op
7.5 to 8.5
V
VDD op
4.5 to 5.5
V
VCC
Tuner Block
Operating Characteristics at Ta = 25°C, VCC = 8.0 V, VDD = 5.0 V, in the specified Test Circuit
Parameter
Symbol
Conditions
Ratings
typ
min
max
Unit
[FM characteristics] FM IF input
Current drain
ICCO-FM
Demodulated output
Channel balance
Total harmonic distortion
CB
S/N-FM IF
AM suppression ratio IF
AMR IF
Separation
10.7 MHz, 100 dBµV, 1 kHz,
ratio of pin15 and pin 16
60
98
110
mA
220
330
445
mVrms
–1
0
+1
dB
0.4
1
THD-FMmono 10.7 MHz, 100 dBµV, 1 kHz, 100% mod, pin 15
Signal-to-noise ratio IF
Muting attenuation
No input, I56 + I61 + I70 + I75 + I76 + I79
10.7 MHz, 100 dBµV, 1 kHz, 100%mod,
pin 15 output
10.7 MHz, 100 dBµV, 1 kHz, 100% mod, pin 15
10.7 MHz, 100 dBµ, 1 kHz, fm = 1 kHz, pin 15
at 30% AM
82
dB
55
68
dB
Att-1
10.7 MHz, 100 dBµV, 1 kHz, attenuation on
pin 15 when V49 = 0 → 2 V
3
8
13
dB
Att-2
10.7 MHz, 100 dBµV, 1 kHz, attenuation on
pin 15 when V49 = 0 → 2 V *Note 1
13
18
23
dB
Att-3
10.7 MHz, 100 dB µV, 1 kHz, attenuation on
pin 15 when V49 = 0 → 2 V *Note 2
26
31
36
dB
10.7 MHz, 100 dBµ, L + R = 90%,
pilot = 10%, pin 15 output ratio
25
35
Separation
Stereo ON level
ST-ON
Pilot modulation at which V17 < 0.5 V
Stereo OFF level
ST-OFF
Pilot modulation at which V17 > 3.5 V
10.7 MHz, 100 dBµV, L + R = 90%,
pilot = 10%, pin 15
1.2
Main total harmonic distortion
%
75
THD-Main L
4.1
dB
6.6
3.1
0.4
%
%
1.2
%
Pilot cancellation
PCAN
10.7 MHz, 100 dBµV, pilot = 10%,
pin 15 signal/PILOT-LEVEL leak DIN AUDIO
12
22
SNC output attenuation
AttSNC
1
5
9
dB
HCC output attenuation
AttHCC-1
10.7 MHz, 100 dBµV, L – R = 90%,
pilot = 10%, V44 = 3 V → 0.6 V, pin 15
10.7 MHz, 100 dBµV, 10 kHz, L + R = 90%,
pilot = 10%, V45 = 3 V → 0.6 V, pin 15
10.7 MHz, 100 dBµV, 10 kHz, L + R = 90%,
pilot = 10%, V45 = 3 V → 0.1 V, pin 15
1
5
9
dB
6
10
14
dB
AttHCC-2
dB
Continued on next page.
No. 6522-2/54
LA17000M
Continued from preceding page.
Ratings
Parameter
Symbol
Input limiting voltage
VIN-LIM
Muting sensitivity
SD sensitivity
VIN-MUTE
SD-sen1 FM
Conditions
Signal meter output
typ
max
Unit
10.7 MHz, 100 dBµV, 30% mod, IF input that
decreases the input reference output by –3 dB
29
36
IF input level non-mod when V49 = 2 V
IF input non-mod (at least 100 mVrms) at
which the IF count buffer output turns on
19
27
35
dBµV
48
56
64
dBµV
SD-sen2 FM
IF counter buffer output
min
dBµV
48
56
64
dBµV
VIFBUFF-FM1
10.7 MHz, 100 dBµV, non-mod, pin 38 output,
during SEEK
145
245
330
mVrms
VIFBUFF-FM2
10.7 MHz, 100 dB µV, non-mod,
pin 38 output, during RDS mode
145
245
330
mVrms
VSM FM-1
No input, pin 42 DC output non-mod
0.0
0.1
0.3
V
VSM FM-2
50 dBµ, pin 42 DC output non-mod
0.65
1.6
2.4
V
VSM FM-3
70 dBµ, pin 42 DC output non-mod
2.4
3.2
4.2
V
VSM FM-4
4.9
5.8
6.5
V
140
210
280
kHz
0.00
0.1
0.3
V
Muting bandwidth
BW-MUTE
100 dBµ, pin 42 DC output non-mod
100 dBµV, when V49 = 2 V
Bandwidth non-mod
Muting drive output
VMUTE-100
100 dBµV, 0 dBµ, pin 49 DC output non-mod
[FM FE Block]
N-AGC on input
VNAGC
83 MHz, non-mod, input at which pin 2 is
2.0 V or less
72
79
86
dBµV
W-AGC on input
VWAGC
83 MHz, non-mod, input at which pin 2 is
2.0 V or less (when KEYED-AGC is 4.0 V)
90
97
104
dBµV
83 MHz, 80 dBµ, non-mod, FECF output
83 MHz, 80 dBµ, non-mod, 5 V applied to CF
(pin 10), FECF output
9
13
17
dB
13
17
21
dB
No input, pin 5 output
51
67
102
mVrms
Conversion gain
A. V1
A. V2
Oscillator buffer output
VOSCBUFFFM
[NC Block] NC input (pin 30)
τ GATE
Gate time
Noise sensitivity
SN
f = 1 kHz, 1 µs, 100 mVp-o pulse input
1 kHz, 1 µs pulse input that starts noise
canceller operation. Measured at Pin 30.
15
µs
18
mVp-o
[MRC Block]
MRC output
VMRC
MRC operating level
MRC sensor output
MRC-ON
V42 = 5 V
Input level on pin 48 that is below
pin 42 = 5 V and pin 43 = 2 V, f = 70 kHz
2.1
2.25
2.4
V
22
33
44
mVrms
1.5
1.9
V
VMRC-sensor1 V42 = 5 V, pin 34 output
VMRC-sensor2 V42 = 5 V, pin 48 output, f = 70 kHz, 100 mVrms
2.1
2.9
V
[AM Characteristics] AM ANT input
Practical sensitivity
S/N-30
1 MHz, 30 dBµV, fm = 1 kHz, 30% mod, pin 15
15
Detection output
VO-AM
1 MHz, 74 dBµV, fm = 1 kHz, 30% mod, pin 15
1 MHz, 74 dBµV, output reference, input width
at which output drops by 10 dB, pin 15
105
160
220
mVrms
50
55
60
mVrms
AGC-F.O.M
VAGC-FOM
Signal-to-noise ratio
S/N-AM
1 MHz, 74 dBµV, fm = 1 kHz, 30% mod
Total harmonic distortion
THD-AM
1 MHz, 74 dBµV, fm = 1 kHz, 80% mod
Signal meter output
VSMAM-1
1 MHz, 30 dBµV, non - mod
VSMAM-2
1 MHz, 120 dBµV, non - mod
Oscillator buffer output
Wideband AGC sensitivity
VOSCBUFFAM-1 No input, pin 5 output
47
dB
52
dB
0.5
1.2
%
0.6
1
1.4
V
3.4
4.5
5.9
170
210
V
mVrms
W-AGCsen1
1.4 MHz, input when V62 = 0.7 V
87
93
99
dBµV
W-AGCsen2
1.4 MHz, input when V62 = 0.7 V (during SEEK)
78
84
90
dBµV
Continued on next page.
No. 6522-3/54
LA17000M
Continued from preceding page.
Parameter
SD sensitivity
IF buffer output
Symbol
SD-sen1AM
Conditions
1 MHz, ANT input level at which IF count
output turns on
SD-sen2AM
1 MHz, ANT input level at which SD pin turns on
VIFBUFF-AM
1 MHz, 74 dBµV, non-mod, pin 38 output
Ratings
typ
min
27
max
33
39
27
33
39
150
220
Unit
dBµV
dBµV
mVrms
PLL Block
Allowable Operating Ranges at Ta = –40 to +85°C, VDD = 5 V, VSS = 0 V
Parameter
Symbol
Conditions
High-level input voltage
VIH1
CE, CL, DI, I/O-1, I/O-2
Low-level Input voltage
VIL1
CE, CL, DI, I/O-1, I/O-2, SDSTSW
Output voltage
Input amplitude
Guaranteed crystal oscillator
ranges
Input amplitude
Ratings
min
typ
max
Unit
2.2
VDD + 0.3
V
0
0.8
V
VO1
DO
0
6.5
V
VO2
I/O-1, I/O-2
0
13
V
fIN1
XIN; Sine wave, capacitor coupled
1
8
MHz
fIN2
PLLIN; Sine wave, capacitor coupled
10
160
MHz
fIN3
HCTR; Sine wave, capacitor coupled
XIN, XOUT; CI ≤ 70 Ω
(X’tal: 10.25, 10.35 MHz); Note 1
0.4
25
MHz
10.1
10.5
MHz
XIN
X’tal
200
1500
mVrms
VIN2-1
VIN1
PLLIN; 10 ≤ f < 130 MHz; Note 2
40
1500
mVrms
VIN2-2
70
1500
mVrms
VIN3-1
PLLIN; 130 ≤ f <160 MHz; Note 2
HCTR; 0.4 ≤ f < 25 MHz: Serial data;
CTC = 0: Note 3
40
1500
mVrms
VIN3-2
HCTR; 8 ≤ f <12MHz: Serial data;
CTC = 1: Note 4
70
1500
mVrms
Data setup time
tSU
DI, CL: Note 5
0.45
µs
Data hold time
tHD
DI, CL: Note 5
0.45
µs
Clock low-level time
tCL
CL: Note 5
0.45
µs
Clock high-level time
tCH
CL: Note 5
0.45
µs
CE wait time
tEL
CE, CL: Note 5
0.45
µs
CE setup time
tES
CE, CL: Note 5
0.45
µs
CE hold time
tEH
CE, CL: Note 5
0.45
Data latch change time
tLC
Data output time
tDC
Note 5
DO, CL; Dependent on pull-up resistance,
board capacity: Note 5
DO, CL; Dependent on pull-up resistance,
board capacity: Note 5
tDH
µs
0.45
µs
0.2
µs
0.2
µs
Note 1:
Recommended CI value for crystal oscillator
CI ≤ 70 Ω (X’tal: 10.25, 10.35 MHz)
However, because the characteristics of the X’tal oscillation circuit depend on the board and circuit constants,
we recommend requesting that the X’tal manufacturer perform the evaluation.
Note 2: Refer to the program divider configuration.
Note 3: Serial data: CTC = 0
Note 4: Serial data: CTC = 1
Note 5: Refer to the serial data timing.
No. 6522-4/54
LA17000M
PLL Characteristics
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Built-in feedback resistors
Symbol
Conditions
Ratings
min
typ
max
Unit
Rf1
XIN
1
MΩ
Rf2
PLLIN
500
kΩ
Rf3
HCTR
250
kΩ
Hysterisis width
VHIS
CE, CL, DI
High-level output voltage
VOH1
PD1, PDS, SEEKSW; IO = –1 mA
VDD–1.0
VOH2
XBUF; IO = –0.5 mA
VDD–1.5
VOL1
PD1, PDS, SEEKSW; IO = –1 mA
VOL2
VOL3
Low-level output voltage
VOL4
High-level input current
Low-level input current
0.1VDD
V
V
V
1
V
XBUFF; IO = –0.5 mA
1.5
V
I/O-1 to I/O-2; IO = 1.0 mA
0.2
V
I/O-1 to I/O-2; IO = 2.5 mA
0.5
V
I/O-1 to I/O-2; IO = 5.0 mA
1
V
I/O-1 to I/O-2; IO = 9.0 mA
1.8
V
DO; IO = 5.0 mA
1
V
µA
IIH1
CE, CL, DI; VIN = 6.5 V
5
IIH2
I/O-1 to I/O-2; VIN = 13 V
5
µA
IIH3
XIN; VIN = VDD
2
11
µA
IIH4
PLLIN; VIN = VDD
4
22
µA
IIL1
CE, CL, DI; VIN = 0 V
5
µA
IIL2
I/O-1 to I/O-2; VIN = 0 V
5
µA
IIL3
XIN; VIN = 0 V
2
11
µA
IIL4
PLLIN; VIN = 0 V
4
22
µA
5
µA
Output off leakage current
IOFF1
I/O-1 to I/O-2; VO = 13 V
IOFF2
DO; VO = 6.5 V
5
µA
High-level 3-state off leakage
current
IOFFH
PD1, PDS; VIN = VDD
0.01
200
nA
Low-level 3-state off leakage
current
IOFFL
PD1, PDS; VIN = 0 V
0.01
200
nA
+0.5
LSB
200
600
kΩ
10
15
mA
5
10
mA
3
mA
Input capacitance
CIN
A/D converter linearity error
Pull-down transistor on
resistance
Err
6
Rpd1
PLLIN
Supply current
IDD1
VDD; X’tal = 10.25 MHz,
fIN2 = 160 MHz,
VIN2 = 70 mVrms,
fIN3 = 25 MHz,
VIN3 = 40 mVrms
IDD2
VDD; PLL block halt (PLL INHIBIT),
X’tal OSC operation (10.25 MHz)
IDD3
VDD ; PLL block halt, X’tal OSC halt
MRC SENSOR AUTO ADJ (MOS)
–0.5
80
pF
No. 6522-5/54
330Ω
SEP-VOL -H
SEP-VOL -L
P1
1µF
100kΩ
20kΩ
100kΩ
10kΩ
30kΩ
1µF
8200pF
16V/1µF
1µF
KEYED AGC
FM SD
VREF
QD IN
QD OUT
AFC IN
0.047µF
42
41
5.6kΩ
40
1µF
GND 39
U +5V
7
3
IF COUNT BUFF SEEK/STOP SELECT 38
VR
450kHz
PC OUT 36
66 FM IF BYPASS
PC IN 35
67 FM IF IN
MRC SENSOR OUT ADC 0 34
68 AM IF IN
SEEKSW 33
69 1st IF OUT
1MΩ
MPX VCO 37
912kHz
64 RF AGC
CR
VCC
43
0.22µF
C-HCC
44
MRC OUT
AM LC
45
AM/FM S-METER
PILOT DET
46
0.022µF
10.7Hz
50Ω
47
2
—5V
33kΩ
1µF
0.022µF
47kΩ
HCTR 32
71 AM SD ADJ/WIDE AGC IN
MPX-FREO
CR
0.01µF
U +5V
7
3
SW07
MRC-SENSOR-OUT
2
CC
+ 0.01µF6 50Ω
—
CC
IF-COUNT-BUFF
CR
4
I/O1 31
LA17000M
CC
—5V
0.01µF
50Ω
70 AM MIX OUT
+ 0.01µF6 50Ω
—
0.01µF
1000pF
180pF
CC
4
1MΩ
SW14
112LDA
48
P1
47kΩ
112NME
0.022µF
49
SNC
50
HCC
51
NC IN
52
DET OUT
53
65 2nd MIX IN
10.7Hz 0.022µF
SW13
FM-IF-INPUT
MUTE
MRC-IN
SIGNAL-MATER-Z
DET-OUT
NC-IN
NC-IN-GND
SW11
54
PHASE COMP
47kΩ 47kΩ
0.01µF
—5V
SIGNAL-MATER-1
0.01µF
55
MUTE
56
FM S-METER MRC IN
57
63 FM MUTE ADJ
3.3µF 1kΩ
4
+ 3
—2
330Ω
6
82pF
62 AM ANTD/WIDE AGC
0.022µF
1MΩ
50Ω
10kΩ
82pF
IF AGC
0.01µF 7
SW09
SW08
10kΩ
0.1µF
58
61
5V
VDDSNC/HCC1
MRC-OUT
59
AM FT
180pF
750pF
10kΩ
60
+5V
100kΩ
1µF
240kΩ
+
+
1µF
—15V
100kΩ
SVC203
100
kΩ
6.8kΩ
82pF
16V/100µF
22µF
0.1µF
1MΩ
AM-STREO-OUT
AM-STREO-OUT-GND
0.01µF
10kΩ
NC
NC 5 7
1
+ 3
6
— 2
4
43kΩ
10kΩ
+15V
0.1µF
1st-IF-OUT
SW12
DET-ADJ
NC
NC 8 7
1
+ 3
6
—2
5
0.1µF
4
—15V
+12V
50Ω
+15V
0.1µF
—15V
10kΩ
SYS-PS-—15V
DZ1
SYS-PS+12V
CENTER-MATER
—5V
15kΩ
—15V
0.22µF
G
I
O
L79MO5T
2200pF
G
0.22µF
+
+5V
0.01µF 0.01µF
16V/47µF
SYS-PS-GND
+15V
L78MO5T
I
O
+
0.01µF 0.01µF
SYS-PS+15V
DO 30
150Ω
18kΩ
76 MIX OUT
X IN 25
77 FE VCC
I/O2 24
22pF
22pF
FE GND
FMOSC
OSC BUFFER
AM/FM
AM OSC
NC Sens
NC AGC
XBUFF IN
Gore OUT
LPF OUT
MPX Pdot IN
NC MPX GND
Lch OUT
Rch out
SDSTSW
PLL IN
PLL VDD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1MΩ
10kΩ
2.2kΩ 10kΩ
D
G
—5V
+
2nd-OSC-BUFF
0.01µF
PLL -VCC
FMIF AM NC MPX VCC
16V/100µF
0.01µF
+
VF/IMZ-G
VF/IMZ-S
VF/IMZ-F
PLL-IN
SW06
50Ω
100pF
CR
VT-OUT
16V/10µF
0.1µF
P1
L-CH-OUT
NC-LPF-OUT
R-CH-OUT
ST-SD
GATE-OUT
0.1µF —15V
SW05
NC-HPF-OUT
OSC-BUFF-OUT
SW18
FM-VCC
4
0.01µF —5V
SW04
+
—2
+15V
NC
NC 5 7
1
+ 3
6
—2
4
CF SW
CC
U 0.1µF
0.01µF
6
3
SW03
CR
0.01µF
SW02
50Ω
1MΩ
7
1000pF
CC
S 2SK583
—15V 0.1µF
+5V
CC
+ 0.01µF6 50Ω
—
4
0.01µF
100pF
51kΩ
P1
+
2
CC
7
NC
3 + 5 1
NC
2
6
—
4
3.3µF
0.022µF
+15V 0.1µF
16V/1µF
U +5V
7
3
PLL VCC
10kΩ
6800pF
0.015µF
112LDA
0.01µF
1MΩ
0.47µF
51kΩ
30pF
150pF 112LDA
30
kΩ
200kΩ
PD1
10kΩ
0.015µF
270pF
NC
SOFP80
350Ω
0.022µF
+
0.022µF
10kΩ
0.022µF
30pF
3SK263
0.022µF
FM ANTD
1
PLL VSS 21
X-IN
SW17
IOZ
PDS 22
FM RF AGC
30kΩ
10pF
30Ω
80 FM MIX IN
16V/100µF
30kΩ
18pF
0.022µF
1000pF
79 AM 1st MIX IN
5pF
0.1µF
1SV234
NC
XBUFF 23
FM-AGC
FM-MIX-INPUT
+12V
50Ω
X OUT 26
200Ω
75 MIX OUT
100Ω
1SV234
CE 27
0.022µF
8pF
100kΩ
510Ω
10pF
0.022µF
0.022µF
10.7Hz
100kΩ
+
E
0.022µF
74 NARROW AGC IN/MUTE ATT ADJ
30kΩ
SW01
FM-ANT-DUMP
6pF
1SV234
100µH
25Ω
D
S
1000pF
50Ω
FM-ANT-INPUT
1SV234
AM-ANT-DUMP
100kΩ
0.022µF
G
33mH
65pF
30Ω
100µH
16V/47µF
FC18
15pF
CI 28
78 1st IF IN (NARROW)
B
AM-ANT-INPUT
73 AM RF AGC OUT
IF-COUNT-IN
SW16
IO1
DO
DUT-CCB-DI
DUT-CCB-CL
DUT-CCB-CE
100µH
100pF
C
150Ω
180kΩ
AM-VCC
0.022µF
15pF
33Ω
15pF 560Ω
0.022µF
2.2µH
16V/100µF
+
82pF 82pF
68pF
30Ω
CL 29
9
1
8
2
7
3
6 712-12 4
1025MHz
200kΩ
30kΩ
k
SW40
SW41
RF-MIX-VCC
RF-MIX-VCC-G
72 1st IF (WIDE)
10.7MHz
k
50Ω
Test Circuit
16V/47µF
LA17000M
A13289
No. 6522-6/54
LA17000M
[FM IF Selectivity Switching Circuit]
Features
1) Comprises an FM/AM one-chip system.
2) Up conversion method is adopted for AM.
3) Uses an IF filter with a center frequency that is the same as the middle frequency of FM.
4) Uses a narrowband filter in AM mode.
5) Uses a narrowband filter in FM mode only during SEEK or when there is interference from adjacent frequencies.
6) Uses a wideband filter for normal reception in FM mode.
7) For an RDS AF search, switches to a narrowband filter and detects SD.
8) High sensitivity for detecting interference from adjacent frequencies.
Advantages
1) This FM/AM one-chip tuner system (an IC that includes a microcontroller interface) allows for improved adjacent
frequency interference characteristics without increased cost.
2) Prevents SD and IF count misdetection (station detection) during seek search, RDS AF search, and auto memory
operations.
3) Permits adoption of an IC for certain functions without increasing the number of IC pins.
4) CF selectivity can be switched by the software in the microcontroller that controls the tuner, making it easy to
achieve performance differentiation through the software.
(The software can freely set the CF switching timing and conditions.)
5) Detects the radio wave status in the field through detection of SD, desired station field intensity, IF count output, and
adjacent station field intensity. This IC offers improved adjacent frequency interference characteristics by switching
the CF automatically when interference is being generated from an adjacent frequency.
[IF Band Switching Circuit]
Purpose
This AM/FM one-chip tuner IC automatically switches the FM selectivity, prevents misdetection during SEEK operations, and offers improved adjacent frequency interference characteristics without any increase in cost.
New Technological Features
1. Comprises an AM/FM one-chip IC.
2. Because the narrowband CF that is used by the AM UP conversion system is also used for FM, additional external
components required by earlier systems can be eliminated.
3. Uses a wideband CF during normal FM reception for high sound quality.
4. Uses a narrowband CF for AM reception, and if interference is being generated from adjacent frequencies during
FM reception.
5. Uses a narrowband CF during SEEK and RDSAF search operations, preventing misdetection of SD and IF count
due to adjacent stations.
6. CF switching is performed at the first IF amp input, and the amp gain is adjusted automatically to a suitable level
according to the CF band form AM/FM or FM.
7. Switching of the CF input and the first IF amp gain is controlled by a microcontroller through the interface. The
pins that are controlled are connected to the I/O ports of the microcontroller, and are controlled by the
microcontroller’s internal software.
8. Detection of adjacent frequency interference during FM reception is based on S-meter output, SD, and IF count
output. The IF count buffer frequency fluctuates when interference is being generated from adjacent frequencies.
This fluctuation is used to make the detection of interference from adjacent frequencies possible. (Related patents
have been applied for.)
Conventional Technologies
1. Comprised of a dedicated IC for IF band switching, or of multiple ICs.
2. None of the AM/FM all-in-one chip systems include the functions provided by the LA17000M.
3. Requires a narrowband CF especially for FM, resulting in increased costs. (Does not share the AM narrowband CF.)
4. Because CF switching control is handled by analog circuits or logic circuits, the switching timing can only be
controlled through uniform conditions. Control by software is not possible.
No. 6522-7/54
LA17000M
Conceptual Diagram of the FM-IF Band Switching System
Wideband
filter
FM
RF
Limiter
amp
Wideband
filter
Mixing
Narrowband
filter
FM
DET
IF
counter
SL
Local
oscillation
Control
circuit
Field
intensity
VCC
LO
A13290
Level
Wideband
A
Narrowband
f (MHz)
10.7
A13291
Fud
Fd
B
10.7
f (MHz)
A13292
C
FdL
Fd
FdH
A13293
D
FdL
Fd
FdH
A13294
No. 6522-8/54
LA17000M
I/O Port Assignment Table
I/O-0
DI data
OUTPUT
PLL output port
L: Reception mode
H: Seek mode
INPUT
PLL input port
OPEN: RDS
I/O-1
I/O-2
DI data
I/O-3
DO data
Unused
OUTPUT
PLL output port
H: Dx mode
L: Lo mode
INPUT
I/O-3 = 0 (input port)
OUT3 = 1 (OPEN or high)
PLL input port
When reception mode is set
H: Monaural
L: Stereo
When seek mode is set
H: SD ON
L: SD OFF
Cannot be set as output port
The MRC sensor reads DO data from the PLL microcontroller’s 6-bit A/D converter.
Currently, aside from the CCB data lines, only three lines are connected to the controller microcontroller: CF/SW,
AUDIO mute, and AM/FM band switching port.
Selectivity Switching Evaluation Software
Tuner processing
I/O port state
CF switching
Seek
State-based Data Switching Table
Manual preset
Receiving
Remarks
WIDE
NARROW
AUDIO mute output
ON
Switchable but fixed by software
OFF
Switchable but fixed by software
Lo
Processing is performed according
to the setting
Dx
Processing is performed according
to the setting
Lo/Dx
Seek mode
Mode switching
Reception mode
I/O-3 is SD output
I/O-3 is monaural/stereo output
RDS mode
I/O-3 is SD output
Output ON
Seek mode
RDS mode
Output OFF
Reception mode
IF count
No. 6522-9/54
LA17000M
Additional Settings (Added to the LC72144M)
Output (DI)
Mode
Tuner mode switch
Settings
When set
Seek mode
DI data IN2
I/O-0 = 1 (output port)
OUT0 = 1 (Hi)
For seek
Reception mode
DI data IN2
I/O-0 = 1 (output port)
OUT0 = 0 (Lo)
For seek-stop and for receiving
RDS mode
DI data IN2
I/O-0 = 0 (input port)
OUT0 = 1 (OPEN)
For AF search
Lo mode
DI data IN2
I/O-2 = 0 (output port)
OUT2 = 0 (Lo)
When setting Lo mode
Dx mode
DI data IN2
I/O-2 = 1 (output port)
OUT2 = 1 (Hi)
When setting Dx mode
Mute ON
DI data IN2
I/O-0 = 1 (output port)
OUT1 = 1 (Hi)
For tuning processing
Mute OFF
DI data IN2
I/O-0 = 1 (output port)
OUT1 = 1 (Lo)
When switching reception mode
Lo/Dx switch
Hard mute *1
Note: *1. Depends on the I/O ports usage.
Input (DO)
DO data
Monaural/stereo
Sensor
SD
MRC output
Conditions
OUT data I3 = 1 (Hi)
Monaural state
OUT data I3 = 0 (Lo)
Stereo state
When the tuner mode is set to
reception mode
OUT data I3 = 1 (Hi)
SD ON
OUT data I3 = 0 (Lo)
SD OFF
When the tuner mode is set to seek or
RDS mode
OUT data ADC0
AD00 to AD05
6 bit
Start AD conversion and then read
after conversion is completed.
3.3 V at 6-bit resolution
*2
*2
Note: *2. I/O-3 = 0 (input port) and OUT3 = 1 (Hi) must already be set in the DI data (IN2) settings.
Other settings
In the LA17000
CF switch
Pin 10
Soft mute (AUDIO mute)
Pin 49
AM/FM switch
Pin 6
Setting
When set
Hi: Wide (wideband setting)
For normal operation
Lo: Narrow (narrowband
setting)
When there is interference from
adjacent frequencies
Hi: Forced mute
When setting mute
Lo: Mute off
When cancelling mute
Lo: AM
For AM reception
Hi: FM
For FM reception
No. 6522-10/54
LA17000M
Correspondence of Pins Between the LA17000M, the LA1781M, and the LC72144M
LA1781
Pin No.
Pin Function
LA17000M
Pin No.
1
FN ANTD
2
FM RF AGC
2
3
FE GND
3
4
FM OSC
4
5
AM/FM OSC buff.
5
6
FE VCC
6
7
AM VCC
7
8
Noise AGC-Sense
8
Pin Function
LC72144M
Pin No.
1
9
Noise AGC-ADJ
9
10
AM 2nd OSC
10
11
Gate Out
11
12
Memory circuit pin
12
13
Pilot In
13
14
NC, MPX GND
14
15
MPX L-Out
15
16
MPX R-Out
16
26
Seek → AM/FM SD
Stop → FM ST IND
17
Both I/O-3 and SD/ST-IND
23
18
FMIN
16
19
VDD
17
20
PD1
18
21
VSS
19
22
PDS
20
23
XBUF
22
24
I/O-2
8
25
XIN
24
26
XOUT
1
27
CE
2
28
DI
3
29
CL
4
30
DO
5
31
I/O-1
9
32
HCTR/I-6
11
33
I/O-0
12
Both ADC0 and MRC
sensor output
7
19
MRC sensor output
34
17
Pilot Can. ADJ
35
18
Pilot Can. ADJ
36
20
MPX VCO
37
23
IF count buffer and
seek/stop switch
38
25
GND
39
21
PHASE COMP.
40
22
PHASE COMP.
41
24
AM/FM S-meter
42
27
MRC OUT
43
Continued on next page.
No. 6522-11/54
LA17000M
Continued from preceding page.
LA1781
Pin No.
Pin Function
LA17000M
Pin No.
28
SNC control input
44
29
HCC control input
45
30
Noise canceller IN
46
31
AM/FM detector output
47
32
FM S-meter output
48
33
MUTE drive
49
34
AFC IN
50
35
QD OUT
51
36
CD IN
52
37
VREF
53
38
FMSD
54
39
GND Keyed AGC
55
40
VCC
56
41
HCC capacitor
57
42
AM L.C.
58
43
Pilot detector
59
44
IF AGC
60
45
AM IFT (IF output)
61
46
AM ANTD
W-AGC IN
62
47
FM Mute ON ADJ
63
48
RF AGC
64
49
AM 2nd MIX IN
65
50
FM IF BYPASS
66
51
FM IF IN
67
52
AM IF IN
68
53
1st IF amplifier output
69
54
AM MIX OUT
70
55
W-AGC IN
AM SD ADJ
71
56
1st IF IN
72
57
AM RF AGC OUT
73
58
N-AGC IN
74
59
1st MIX OUT
75
60
1st MIX OUT
76
61
F.E.VCC
77
64
FM MIX IN
78
62
AM MIX IN
79
63
FM MIX IN
80
Pin Function
LC72144M
Pin No.
1st IF narrow IN
No. 6522-12/54
LA17000M
PLL Block Functions
• High-speed programmable divider
• FMIN
: 10 to 160 MHz .......................... Pulse swallower method
• General-purpose counter
• HCTR
: 0.4 to 25.0 MHz ........................ Frequency measurement
• Crystal oscillator
: Two frequencies selectable: 10.35/10.25 MHz
• Reference frequencies : 12 frequencies selectable:
50, 30, 25, 12.5, 6.25, 3.125, 10, 9, 3, 5, and 1kHz
*1
*1 *1
*1: Not available when using the 10.25 MHz crystal oscillator
• Phase comparator
• Dead zone can be controlled
• Unlock detection circuit
• Sub-charge pump for high-speed locking
• Deadlock clear circuit on chip
• A/D converter ................................ 6 bits: 1 input (linked directly to MRC sensor output)
• Serial data I/O
Communications with controller possible in CCB format
• Power-on reset circuit
• On-chip crystal oscillator output buffer
• 2nd IF injection signal for AM up conversion (10.35/10.25 MHz)
• I/O port .......................................... General-purpose I/O: four ports
No. 6522-13/54
LA17000M
Serial Data Timing
VIH
CE
tCH
CL
VIH
VIL
tCL
VIH
VIL
tEL
DI
VIL
VIH
VIL
tSU
VIL
tES
VIH
tEH
VIH
VIL
tHD
tDC
tDH
DO
tLC
Internal
data latch
Old
New
A13295
When CL is Stopped at the low level
VIH
CE
tCL
tCH
VIH
CL V
IL
VIH
VIL
tEL
DI
VIL
VIH
VIL
tSU
VIH
VIL
tHD
tES
tDC
VIH
tEH
tDH
DO
tLC
Internal
data latch
Old
New
A13296
When CL is Stopped at the high level
No. 6522-14/54
LA17000M
PLL Block Pin Description
Symbol
Pin No.
Description
XIN
XOUT
25
26
X’tal OSC
PLL IN
18
Local
oscillator
signal input
Function
Pin Circuit
• For connecting the crystal oscillator.
(10.35, 10.25, 7.2 or 4.5 MHz)
A13297
• FMIN is selected when DVS in the serial data
input is set to 1.
• The input frequency range is from 10 to
160 MHz.
• The signal is transmitted to the swallow
counter.
• The divisor can be set to a value in the range
272 to 65535.
CE
27
Chip enable
• This pin is set high during serial data input to
the PLL (DI) or during serial data output (DO).
CL
29
Clock
• This pin is the clock for data synchronization
during serial data input to the PLL (DI) or
during serial data output (DO).
A13298
Ｓ
A13299
DI
28
Input data
• This is the input pin for serial data that is
transferred from the controller to the PLL.
Ｓ
A13300
Ｓ
A13301
DO
30
Output data
• This is the output pin for serial data that is
transferred from the controller to the PLL.
A13302
VDD
19
VSS
21
I/O-1
I/O-2
STSD SW
31
24
17
SEEK SW
33
Power supply
Ground
Generalpurpose
I/O ports
Generalpurpose
I/O port
• This is the PLL power supply pin. Supply 4.5 V
to 5.5 V to this pin when the PLL is operating.
• When power is first applied to this pin, the
power-on reset circuit operates.
• This is the PLL ground pin.
• These are general-purpose I/O ports.
• The output circuits open-drain.
• During a power-on reset, I/O-1 and I/O-2
become input ports. STSD SW becomes an
output port, and is fixed low.
• These ports can be switched between input
and output according to the serial data that is
transferred from the controller (I/O-1, I/O-2,
STSD SW).
A13303
• This is a general-purpose I/O port.
• The output circuits are complementary
circuits.
• During a power-on reset, this port becomes
an input port.
• This port can be specified as an input or
output port by the serial data that is transferred from the controller.
A13304
ADC0
34
ADC input
• This is the A/D converter input pin.
The converter is a 6-bit successive-approximation A/D converter.
For details, refer to the page that describes
the A/D converter configuration.
A13305
Continued on next page.
No. 6522-15/54
LA17000M
Continued from preceding page.
Symbol
Pin No.
PD1
20
0
PDS
HCTR
XBUF
22
32
23
Description
Main
charge
pump
output
Sub-charge
pump
output
Generalpurpose
counter
X’tal
oscillator
buffer
Function
Pin Circuit
• This is the PLL charge pump output pin.
When the frequency of the local oscillation
signal frequency is divided by N is higher than
the reference frequency, a high level signal is
output from the PD1 pin. When the frequency
is lower, a low level signal is output. If the
frequencies match, the pin goes to high
impedance.
A13306
• A high-speed lockup circuit can be formed by
using this pin in combination with the main
charge pump.
• For details, refer to page that describes the
charge pump configuration.
A13307
• Serial data: HCTR is selected if CTS1 = 1 is
set.
• The input frequency is 0.4 to 25 MHz.
• The signal is passed through to the generalpurpose counter internally, via the 1/2
frequency divider. An integrating count can
also be kept.
• The count result is output from the MSB of
the general-purpose counter through the
output pin DO.
• For details, refer to page that describes the
general-purpose counter configuration.
• Serial data: Prohibited when HCTR = 0.
• This is the output buffer for the crystal
oscillator circuit.
• Serial data: When XB = 1 is set, the output
buffer operates and the crystal oscillator
signal (pulse) is output.
When XB = 0, this pin outputs a low level.
(When a power-on reset is executed, XB = 0
and the output buffer is fixed at the low level.)
A13308
XOUT
A13309
No. 6522-16/54
LA17000M
Procedures for Input and Output of Serial Data
Data I/O is handled through the Computer Control Bus (CCB), SANYO’s audio IC serial bus format. This IC uses CCB
with 8-bit addressing.
I/O mode
Address
B0
B1
B2
B3
A0
A1
A2
A3
Description
[1]
IN1
0
0
0
1
0
1
0
0
• Control data input (serial data input) mode.
• 32-bit data input
[2]
IN2
1
0
0
1
0
1
0
0
• Control data input (serial data input) mode.
• 32-bit data input
[3]
OUT
0
1
0
1
0
1
0
0
• Data output (serial data output) mode.
• The bit count output is equal to the clock cycle count.
I/O mode setting
CE
CL
DI
B0
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
DO
First Data OUT
A13310
i) Serial Data Input (IN1/IN2)
tSU，tHD，tES，tEC，tEH ＞ 0.45μs
tLC ＜ 0.45μs
CE
tES
tEC
tEH
CL
tSU
DI
tHD
B0
B1
B2
B3
A0
A1
A2
A3
P0
P1
P2
P3
CTS0 CTS1 GT0
GT1
tLC
Internal data
A13311
ii) Serial data output (OUT)
tSU，tHD，tES，tEC，tEH ＞ 0.45μs
tLC，tDH ＜ 0.2μs (*1)
CE
tES
tEC
tEH
CL
tSU
tHD
DI
B0
DO
(*2)
B1
B2
B3
A0
A1
A2
A3
tDC
tDH
I7
I6
I5
I4
AD13 AD12 AD11 AD10
(*2)
A13312
*1: Because the DO pin is an N-channel open drain pin, the data transition time varies according to the pull-up resistance
and the board capacitance.
*2: The DO pin is normally open.
No. 6522-17/54
(15) PD-L
(16) TEST
(14) DZ-C
(13) XTAL
(12) UNLOCK
(4) DO-C
(11) U/I-C
(6) U-CTR
(10) O-PORT
(5) ADC
(9) SDST-PORT
(7) I/O-C
DI
SEEKSW
I/O-1
I/O-2
SDSTSW
1
1
ADI0
ADI1
OUT0
OUT1
OUT2
OUT3
0
0
CTP
CTC
HCTR
1
IL0
IL1
ULD
UL0
UL1
XS0
XS1
XB
DZ0
DZ1
TEST0
TEST1
TEST2
DLC
(6) U-CTR
(5) ADC
(4) DO-C
(3) R-CTR
(2) PD-C
(1) P-CTR
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
SNS
DVS
PDC0
PDC1
R0
R1
R2
R3
DT0
DT1
ADS
CTE
CTS0
CTS1
GT0
GT1
DI
(8) SEEK-PORT
LA17000M
DI Control Data (Serial Data Input) Configuration
[1] IN1
Address
0 0 0 1 0 1 0 0
First Data IN1
A13313
[2] IN2 Mode
Address
1 0 0 1 0 1 0 0
First Data IN2
A13314
No. 6522-18/54
LA17000M
Description of DI Control Data
No.
Control block/Data
Description
Programmable divider data
• This data sets divisor for the programmable divider. P15 is a binary value that is
designated as the MSB. The LSB changes depending on DVS and SNS.
P0 to P15
DVS
SNS
ISB
Divisor setting (N)
1
1
P0
272 to 65535
Related data
* DVS = 1 (DVS = 0: Prohibited)
(1)
• These values select the signal input pin (PLL IN) for the programmable divider,
and switch the input frequency range.
DVS, SNS
DVS
SNS Input pin
1
1
Input pin frequency range
PLLIN
10 to 160 MHz
* For details, refer to “Programmable Divider Configuration.”
Sub-charge pump
control data
• This data controls the sub-charge pump.
PDC1
PDC0
0
1
1
*
0
1
PDC, PDC1
(2)
UL0, UL1,
DLC
Subcharge pump status
High impedance
Charge pump on (when unlocked)
Charge pump on (normal operation)
* The sub-charge pump can be used to form a high-speed lockup circuit in
combination with PD0 and PD1 (main charge pump).
• For details, refer to the page on charge pump.
Reference divider data
R0 to R3
(3)
• This is the reference frequency (fref) selection data.
R3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reference frequency
Prohibited
50
25
25
12.5
6.25
3.125
3.125
10
9 *1
5
1
9 *1
30 *1
*2 PLL INHIBIT + X’tal OSC STOP
*2 PLL INHIBIT
*1: Prohibited when X’tal OSC = 10.25 MHz.
*2: PLL INHIBIT (backup mode)
The programmable divider block stops, the PLL IN pin is pulled down to
GND, and the charge pump output goes to the floating state.
Continued on next page.
No. 6522-19/54
LA17000M
Continued from preceding page.
No.
Control block/Data
DO, I/O-5 pin control data
Description
Related data
• This data determines the output on the DO pin and the I/O-5 pin.
ULD
DT1
DT0
DO pin
0
0
0
0
0
0
1
1
0
1
0
1
Low when unlocked
end-AD
end-UC
IN (*1)
ULD
DT0, DT1
IL0, IL1
I/O-1
I/O-2
end-AD: End of conversion by the A/D converter
end-UC: End of conversion by the general-purpose counter
DO
(4)
Start
End
CE：Hi
(I-1 changes)
A13315
*1
IL1
IL
IN
0
0
1
1
0
1
0
1
Open
I-1 (pin status)
I-2 (pin status)
If I-1 changes, DO goes low. (Note)
* However, if the I/O-1 and I/O-2 pins are specified as output ports, these pins
are open.
Note: Cannot be used when X’tal OSC is set to STOP. (DO does not change.)
[When the reference divider data: R3 = R2 = R1 = 1 and R0 = 0]
A/D converter control data
(5)
ADS
ADI0
• A/D converter conversion start data.
ADS = 1: A/D conversion reset and start
0: A/D conversion reset
ADI1
ADI0
1
1
0
0
1
0
1
0
AD input pin
Stopped
ADC0
Not usable
Not usable
Continued on next page.
No. 6522-20/54
LA17000M
Continued from preceding page.
No.
Control block/Data
General-purpose counter
control data
CTS0, CTS1
CTE
GT0, GT1
(6)
CTP
CTC
I/O port control data
(7)
Description
Related data
• This data sets the general-purpose counter input pin (HCTR).
CTS1
Measurement time
Measurement mode
1
0
HCTR
—
Frequency
Not measured
HCTR
• General-purpose counter measurement start data
CTE = 1: Count start
= 0: Count reset
• This data determines the measurement time (frequency mode) and number of
periods (period mode) for the general-purpose counter.
GT1
GT0
0
0
1
1
0
1
0
1
Frequency measurement mode
Wait time (ms)
CTP = 0
CTP = 1
4
3 to 4
1 to 2
8
3 to 4
1 to 2
32
7 to 8
1 to 2
64
7 to 8
1 to 2
Measurement
time (ms)
Period
measurement
mode
1 period
1 period
2 periods
2 periods
• CTP = 0: When a count reset is executed (CTE = 0), the general-purpose
counter input is pulled down.
= 1: When a count reset is executed (CTE = 0), the general-purpose
counter input is not pulled down, and the wait time is reduced.
However, immediately after CTP = 1 is set, the start of the count
must wait until the general purpose counter input pin is biased.
• The input sensitivity is reduced when CTC = 1. (Sensitivity: 10 to 30 mVrms)
• This data specifies whether an I/O port is an input port or an output port.
“data”= 0: Input port
= 1: Output port
I/O-1 to I/0-2
OUT0 to OUT3
ULD
* During a power-on reset, I/O-0 and I/O-2 become input ports.
STSD SW becomes an output port.
SEEK SW
• This data determines the status of the SEEK SW pin.
“data” = 0: 2.5[V] output
* This pin is open and the midpoint bias is output by an external circuit.
“data” = 1: 0[V] or 5[V] output
* Determined by the OUT0 data.
SDST SW
• AM/FM SD, FM-ST IND output dual-purpose pin
“data” = 0: Fixed
= 1: Prohibited
(8)
(9)
Output port data
(10)
OUT0 to OUT2
(11)
General-purpose counter
input control data
• This data determines the output on output ports O-0 through O-3.
“data” = 1: Open or Hi
= 0: Low
* Invalid if specified as an input port or unlocked output.
• This data converts the general-purpose counter pin to an input port.
HCTR = 0: Prohibited
= 1: HCTR (general-purpose counter)
I/O-0 to I/O-3
ULD
I/O-0 to I/O-3
ULD
I/O-0 to I/O-3
ULD
CTS1
HCTR
Continued on next page.
No. 6522-21/54
LA17000M
Continued from preceding page.
No.
(12)
Control block/Data
Description
Unlock detection data
• This data selects the phase error (øE) detection width that is used for evaluating
PLL lock.
If a phase error that exceeds the øE detection width in the following table is
generated, the signal is deemed to be unlocked. When the signal is unlocked,
the detection pin (DO or I/O-5) goes low.
UL1, UL0
UL1
DT0
0
0
1
1
0
1
0
1
øE detection width
Stop
0
±0.5 µs
±1 µs
Related data
Detection pin output
Open
Direct output of øE
Extend øE by 1 to 2 ms
Extend øE by 1 to 2 ms
ULD
DT0, DT1
φE
Extention
1 to 2ms
DO
Unlocked output
A13316
Crystal oscillator circuit
(13)
XS0, XS1
XB
Phase comparator control
data
(14)
DZ0, DZ1
• This is the crystal oscillator selection data.
XS1
XS0
X’tal OSC
0
0
1
1
0
1
0
1
Prohibited
Prohibited
10.25 MHz
10.35 MHz
R0 to R3
* When a power-on reset is executed, 10.25 MHz is selected.
• Crystal oscillator buffer (XBUF) output control data.
XB = 0: Buffer output: OFF (This mode is selected when a power-on reset is
executed.)
XB = 1: Buffer output ON
* For FM reception (using the PD0 pin), XBUF output must be off.
• This data controls the phase comparator dead zone.
DZ1
DZ0
Dead zone mode
0
0
1
1
0
1
0
1
DZA
DZB
DZC
DZD
• When a power-on reset is executed, DZA is selected.
Charge pump control data
(15)
DLC
IC test data
(16)
TEST0
TEST1
TEST2
• This data is used to force the charge pump output to the low level (VSS level).
DLC = 1: Low level
= 0: Normal operation
* If a deadlock occurs because the VCO control voltage (Vtune) is 0 V and VCO
oscillation is stopped, it is possible to escape the deadlock by forcing the
charge pump output to low level and setting Vtune to VCC.
When a power-on reset is executed, normal operation mode is selected.
• This is the IC test data.
Set TEST0 = 0.
TEST1 = 0
TEST2 = 0
* When a power-on reset is executed, all the test data is set to zero.
No. 6522-22/54
LA17000M
DO Output Data (Serial Data Output) Configuration
[3] OUT mode
Address
DI
0 1 0 1 0 1 0 0
☆ ☆☆☆
(2) U-CTR
✩: “0” data
☆ ☆ ☆ ☆☆ ☆ ☆ ☆
(4) ADC1
(3) ADC0
☆☆
AD05
AD04
AD03
AD02
AD01
AD00
☆☆ ☆☆
(1) IN-PORT
DO
I3
I2
I1
I0
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
First Data OUT
A13317
No.
(1)
(2)
Control block/Data
Description
Related data
I/O port data
• I0 to I3 is the latched data reflecting the status of the input ports: I/O-0 to I/O-3.
The data is latched at the point that data output mode is set.
The pin status is latched regardless of the input/output specification.
Pin status = Hi: 1
Low: 0
I/O-1 to I/O-2
SEEK SW
HCTR
I3 to I0
General-purpose counter
binary data
C19 to C0
(3)
A/D converter
ADC0 data
AD05 to AD00
• C19 to C0 is the latched data reflecting the contents of the general-purpose
counter (a 20-bit binary counter).
C19
C0
←
←
MSB of binary counter
LSB of binary counter
• AD05 to AD00 is the latched data reflecting the results when the ADC0 pin
input signal undergoes AD conversion.
AD05
AD00
←
←
MSB
LSB
CTS0
CTS1
CTE
ADI1
ADS
No. 6522-23/54
LA17000M
Programmable Divider Configuration
4bits
12bits
(A)
PLL IN
fvco/N
Swallow
Counter
Programmable
Divider
PD
φE
fref
fvco = fref × N
A13318
DVS SNS
(A)
1
*
Input pin
Divisor setting (N)
PLL IN
272 to 65535
Input frequency range
10 to 160 MHz
Minimum input sensitivity f[MHz]
(A) PLL IN
10 ≤ f < 130
130 ≤ f <160
40 mVrms
70 mVrms
General-purpose Counter Configuration
In the LA17000M, the general-purpose counter consists of a 20-bit binary counter. The count results can be read
through the DO pin, MSB first.
General-purpose counter
(20-bit binary counter)
1
2
HCTR
L
S
B
(FIF)
CTS
M
S
B
DO pin
0 to 3 4 to 7 8 to 11 12 to 1516 to 19
4/8/32/64
ms
GT
CTE
GT1, GT0
C = FIF × GT
A13319
When using the general-purpose counter for cycle measurement, the measurement period can be selected from among 4,
8, 32, and 64 ms through the GT0 and GT1 data. The cycle of the signal that is input to the HCTR pin or the LCTR pin
can then be measured by counting the number of pulses that are input to the general-purpose counter within this measurement period.
When using the general-purpose counter to measure a cycle, it is also possible to measure the cycle of a signal that is
input to the LCTR pin according to the number of check signals (refer to the “Check Signal Frequency” table below)
input to the general-purpose counter within one or two cycles of the signal that is input to the LCTR.
Check Signal Frequency
X tal OSC
10.25 MHz
Check signal
10.25 kHz
S1
10.35 MHz
fref = 30, 9, 3 kHz
fref other than 30, 9, 3 kHz
1030 kHz
1150 kHz
CTS1
Input pin
Measurement mode
Frequency range
Input sensitivity
1
HCTR
Frequency
0.4 to 25.0 MHz
40 mVrms *1
*1 CTC = 0: 40 mVrms; however, when CTC = 1, the frequency range is HCTR: 8 to 12 MHz
CTC = 1: 70 mVrms
No. 6522-24/54
LA17000M
CTC data: This is the input sensitivity switch data; when CTC = 1, the input sensitivity is degraded.
HCTR: Minimum input sensitivity standard f [MHz]
CTC
0 (Normal mode)
1 (Degraded mode)
0.4 ≤ f < 8
8 ≤ f < 12
12 ≤ f < 25
40 mVrms
40 mVrms
(1 to 10 mVrms)
40 mVrms
70 mVrms
(30 to 40 mVrms)
—
—
—: Not stipulated (operation not guaranteed)
( ): Actual performance estimates (reference value)
CTP data: This is data that determines the status of the general-purpose counter input pin (HCTR/LCTR) when a
general-purpose counter reset (CTE = 0) is executed.
CTP = 0: Pulls down the general-purpose counter input pin.
= 1: Does not pull down the general-purpose counter input pin, reducing the wait time to 1 or 2 ms.
When setting CTP = 1, do so at least 4 ms prior to starting the count (CTE = 1). If the counter is not to be
used, set CTP = 0.
GT1
GT0
0
0
1
1
0
1
0
1
Frequency measurement mode
Wait time
CTP = 0
CTP = 1
4 ms
3 to 4 ms
8
1 to 2 ms
32
7 to 8 ms
64
Measurement
time
Cycle
measurement
mode
1 cycle
2 cycles
IF Counter Operation
Before starting counting with the general-purpose counter, the general-purpose counter must first be reset by setting CTE
= 0. The general-purpose counter is made to start counting by setting serial data CTE = 1. The serial data is finalized
within the PLL by changing CE from high to low, but input to the HCTR pin must be started within the wait period after
CE is sent low at the very latest. After measurement ends, the count results from the general-purpose counter must be
read while CTE = 1. (Once CTE is set to zero, the general-purpose counter is reset.) Furthermore, the signal that was
input to the HCTR pin is passed through to the general-purpose counter after having been divided by 1/2 internally.
Therefore, the general-purpose count results are actually 1/2 the actual frequency of the signal that was input to the
HCTR pin.
CE
CTE = 1
data
Wait time
Frequency measurement time
Measurement
time
Signal input
40 mVrms or more*
(when measuring frequency)
* CTC = 0: 40 mVrms
CTC = 1: 70 mVrms
A13320
No. 6522-25/54
LA17000M
Integrated Count
※ CTE=1
※ CTE=1
※ CTE=0
CE
Internal data latch
(CTE)
GT
(integration)
General-purpose counter
Restart
Start
Reset
end-UC
Count end
A13321
* CTE: 0 →
1→
• General-purpose counter reset
• General-purpose counter start
• Setting to “1” again causes a restart.
When using integrated counting, the count value is accumulated in the general-purpose counter.
Be careful about counter overflows.
Count value: 0H to FFFFFH (1048575)
When using integrated counting, resending serial data (IN1) with CTE = 1 restarts measurement with the
general-purpose counter, and the count results are added to the previous count results.
A/D Converter Configuration
This is a 6-bit successive-approximation converter with a conversion time of 0.56 ms. Full scale (when the data is 3FH)
is (63/96) x VDD.
VDD
Multiplexer
＋
Evaluation
circuit
−
ADC0
Vref
ADI0 ADI1
2R
2R
Comparator
R
R
R
R
R
2R
2R
2R
2R
2R
MSB
2R
LSB
ADS
Decoder
ADO3
ADO2
ADO1
ADO0
ADO4
☆ ☆
ADO5
63
Vref max= ×VDD
96
☆ ☆ ☆ ☆ ☆ ☆ ☆ ☆
REGISTER
DO pin
☆ : “0” data
A13322
No. 6522-26/54
LA17000M
ADI1
ADI0
1
1
0
0
1
0
1
0
Input pin
Prohibited
ADC0
Prohibited
Prohibited
* Since the PLL block in the LA17000M does not provide an
external pin for ADI1, the function cannot be used. ADI0
is linked directly to the pin 34 MRC sensor output, and is
used exclusively for multipath signal intensity detection.
CTS=1
CE
Conversion end
ADC0
Conversion
tWA1：0.08 to 0.11ms
tWA2：0.08 to 0.09ms
tAD ：0.56 to 0.62ms
tWA1
end-AD
tAD
Conversion start
A13323
Charge Pump Configuration
DLC
fvco/N
Phase
Detector
PD1
(MAIN)
fref
DZ0
Clock
UL0
UL1
DZ1
Unlock
Detector
and
Subcharge
Pump Cont
PDC0 PDC1
PDS
Unlock
(SUB)
D0, I/O-5 pin
A13324
PDC1 PDC0
0
1
1
*
0
1
PDS (sub-charge pump status)
DLC
High impedance
Charge pump on (when unlocked)
Charge pump on (at all times)
0
1
PD1, PDS
Normal operation
Forced low
If the unlocked state is detected during a channel change, the PDS (sub-charge pump) operates, R1 ← R1M/R1S, the
low-pass filter time constant is reduced, and lockup is accelerated.
R1M
VCC
PD0
R1S
PDS
Vtune
A13325
* Unlock detection data: UL1 = 1 must be set. This sets the unlock detection width to “±0.5 µs” or “±1 µs” mode; if a
phase difference that is greater than the value in question is detected, the signal is unlocked and the sub-charge pump
operates. As the locked condition is approached and the phase difference falls to less than the unlocked detection
width, the sub-charge pump stops operating (goes to high impedance).
No. 6522-27/54
LA17000M
Other Items
[1] Notes on the Phase Comparator Dead Zone
DZ1
DZ0
Dead zone mode
Charge pump
Dead zone
0
0
DZA
ON/OFF
– –0 s
0
1
DZB
ON/ON
–0 s
1
0
DZC
OFF/OFF
+0 s
1
1
DZD
OFF/OFF
++0 s
Since correction pulses are output from the charge pump even if the PLL is locked when the charge pump is in the
ON/ON state, the loop can easily become unstable. This point requires special care when designing application
circuits.
The following problems may occur in the ON/ON state.
• Side band generation due to reference frequency leakage
• Side band generation due to both the correction pulse envelope and low frequency leakage
Schemes in which a dead zone is present (OFF/ON) have good loop stability, but have the problem that acquiring a
high C/N ratio can be difficult. On the other hand, although it is easy to acquire a high C/N ratio with schemes in
which there is no dead zone, it is difficult to achieve high loop stability. Therefore, it can be effective to select DZA
or DZB, which have no dead zone, in applications which require an FM S/N ratio in excess of 90 to 100 dB, or in
which an increased AM stereo pilot margin is desired. On the other hand, we recommend selecting DZC or DZD,
which provide a dead zone, for applications which do not require such a high FM signal-to-noise ratio and in which
either AM stereo is not used or an adequate AM stereo pilot margin can be achieved.
Dead Zone
The phase comparator compares fp to a reference frequency (fr) as shown in Fig. 1. Although the characteristics of
this circuit (see Fig. 2) are such that the output voltage is proportional to the phase difference ø (line A), a region
(the dead zone) in which it is not possible to compare small phase differences occurs in actual ICs due to internal
circuit delays and other factors (line B). A dead zone as small as possible is desirable for products that must provide
a high S/N ratio.
However, since a larger dead zone makes this circuit easier to use, a larger dead zone is appropriate for popularlypriced products. This is because it is possible for RF signals to leak from the mixer to the VCO and modulate the
VCO in popularly-priced products in the presence of strong RF inputs. When the dead zone is narrow, the circuit
outputs correction pulses and this output can further modulate the VCO and generate beat frequencies with the RF
V
signal.
RF
(A)
MIX
Leak
fr
Reference Divider
fp
Programmable Divider
(B)
φ (ns)
Phase
Detector
LFP
VCO
Dead Zone
Fig. 1
Fig. 2
A13327
A13326
[2] Notes on the PLL IN and HCTR pins
Coupling capacitors must be placed extremely close to these pins. The capacitance should be about 100 pF. If a
capacitor with a capacitance of 100 pF or less is not used with HCTR in particular, there will be a long wait until the
bias level is reached, which may sometimes cause miscounting.
[3] Notes on IF counting
When using the general-purpose counter for IF counting, be certain to have the microcontroller determine whether
the IF-IC SD (Station Detector) signal is present or not, and to turn on the IF count buffer output and conduct the
count, but only if the SD signal is present. Conducting an auto search using only the IF count is not reliable, since
there is a possibility of stopping even where there is no station due to leaked output from the IF count buffer.
[4] Using the DO pin
Aside from data output mode, the DO pin can also be used to check for the completion of counting by the generalpurpose counter, unlock detection output, and to check for changes in the input pins. It is also possible to input the
status of the input pins (I/O-1, I/O-2) to the controller, unchanged, via the DO pin.
No. 6522-28/54
LA17000M
[5] Cautions concerning the use of XBUF
When the XBUF output is on (AM up conversion is being used), the XBUF signal may leak to the adjacent pins
(PD0, I/O-3), so do not use PD0 and I/O-3 for AM reception control. (Use the PD1 pin for the AM reception charge
pump.) When using PD0 and I/O-3 for FM reception control, the XBUF output must be turned off (XB data = 0).
[6] Power supply pins
To filter out noise, insert a capacitor of at least 2000 pF between the power supply pins VDD and VSS. The capacitor
must be located as close to the pins as possible.
Tuner Block Pin Description
Pin No.
Function
1
Antenna damping drive
pin.
Equivalent circuit
Description
Pin 62
VCC
ANT
RF
AGC
The antenna damping current flows
to this pin when the pin 2: RF AGC
voltage is VCC-VD.
1000pF
300Ω
100Ω
1
100Ω
1000pF
A13328
2
RF AGC
FET 2nd gate voltage control pin.
VCC
FET
2ND GATE
＋
12kΩ
2
ANT
N
AGC
DET
W
AGC
DET
VCC
KEYED
AGC
3
F.E.GND
4
OSC
DAMPING
DRIVER
A13329
OSC pin with built-in Tr. capacitor for
oscillator circuit.
VCC
18pF
4
20pF
VT
60pF
A13330
Continued on next page.
No. 6522-29/54
LA17000M
Continued from preceding page.
Pin No.
Function
6
F.E.VCC, AM/FM switch
pin
Equivalent circuit
Description
Pin 6 is shared for FM F.E.VCC and
the AM/FM SW circuit.
SD
VCC
6
510Ω
AM/FM Switch
Circuit
＋
−
＋
FM.F.E
AGC 100kΩ
V6 voltage
Mode
8V
→
FM
OPEN
→
AM
3.3V
8V
3
GND
7
A13366
AM OSC
7
First OSC for AM.
Permits oscillation up to the SW
band.
ALC circuit connected.
VCC
A L C
A13331
8
9
Noise AGC sensitivity
AGC adjusting pin
Pin 8 is the noise sensitivity setting
pin. After setting a moderate field
(approximately 50 dBµ), use the pin 9
AGC adjusting pin to make the
setting for weak fields (approximately
20 to 30 dBµ).
3kΩ
15kΩ
3kΩ
200Ω
8
9
3kΩ
＋
0.47μF
1MΩ
0.01μF
A13332
10
AM 2nd OSC
10kΩ
10kΩ
5.6V
TO 2nd
MIX
10kΩ
100pF
10kΩ
10
5V
SW
51kΩ
SWON
pin 78 input
SOWOPen pin 78 input
Shared pin.
CF selectivity switch.
Select either 10.7 MHz 1st IF input
pin 72 or pin 78.
• A second local oscillation signal is
injected by the PLL XBuffer.
* The PLL X’tal is as follows:
AM 9 kHz step 10.35 MHz
AM 10 kHz step 10.25 MHz
(NDK AT-51 type: XTAL oscillator)
PLL
XBuffer
A13367
Continued on next page.
No. 6522-30/54
LA17000M
Continued from preceding page.
Pin No.
11
12
Function
Memory circuit pin
Memory circuit pin
Equivalent circuit
0.01μF
13
6800pF
12
Description
Memory circuit used when the noise
canceller is in operation.
3.9kΩ
11
VCC
Differential
amp
Gate
circuit
LPF
13
A13333
Pilot input
Pin 13 - PLL circuit signal input pin.
VCC
30kΩ
PLL
N.C
12
13
0.01μF
A13334
14
N.C, MPX, MRC, GND
GND for N.C/MPX/MRC circuit.
15
16
MPX output (LEFT)
MPX output (RIGHT)
De-emphasis
50 µs; 0.015 µF
75 µs; 0.022 µF
VCC
3.3kΩ
3.3kΩ
15
16
0.015μF
0.015μF
A13335
Continued on next page.
No. 6522-31/54
LA17000M
Continued from preceding page.
Pin No.
17
Function
Equivalent circuit
Description
SD pin
Stereo indicator
For FM:
V17 switches among three modes
according to the following voltages.
5 V: Operates in conjunction with
the SD pin and the IF count
buffer.
2.5 V:Operates as SD pin in forced
SD mode. RDS AF9AR.
0 V: Reception mode stereo
indicator
Stereo
indicator
AM/FM
SD
SEEK/STOP
switch
17
For AM: (two modes: 0 and 5 V)
5 V: Operates as SEEK SD pin.
0 V: Reception mode, not used
100kΩ
VDD
35
Pilot canceller signal
input
A13342
The pilot signal level requires
adjustment since it changes
according to variations in the IF
output level, etc.
VCC
20kΩ
6.7kΩ
10kΩ
35
36
0.01μF
100kΩ
A13336
36
Pilot canceller signal
output
Pin 36 pilot canceller signal output
pin.
VCC
1.5kΩ
35
36
0.01μF 100kΩ
A13337
Continued on next page.
No. 6522-32/54
LA17000M
Continued from preceding page.
Pin No.
37
Function
Equivalent circuit
VCO
Description
Oscillation frequency: 912 kHz.
Murata CSB912JF108
CSB
912
JF108
37
VREF
10pF
A13338
40
41
PHASE COMP.
PHASE COMP.
VREF
15kΩ
＋
15kΩ
19kΩ
41
＋
＋
40
A13339
38
IF count buffer
SEEK/STOP switch
4.9V
＋
−
50kΩ
＋
−
1.3V
AM MUTE
VCC
IF count buffer
10kΩ
SW
＋
−
150Ω
50F
SD circuit
38
51kΩ
Shared pin for the IF count buffer (AC
output) and SEEK/STOP switch (DC
input).
V38 switches among three modes
according to the following voltages.
For FM:
5 V: SEEK mode
2.5 V: Forced SD mode, RDS mode
0 V: Reception mode
For AM (two modes: 0 and 5V)
5 V: SEEK mode
0 V: Reception mode
*When interference from an adjacent
FM frequency is detected:
2.5 V: Use RDS mode.
STOP
IF
BUFF.
Forced SEEK
SD 2.5V 5V
A13340
Continued on next page.
No. 6522-33/54
LA17000M
Continued from preceding page.
Pin No.
42
Function
Equivalent circuit
AM/FM S-meter
Description
Constant current drive-type S-meter
output.
VCC
FM
S-meter
48
48
Dedicated FM S-meter
10kΩ
AM
S-meter
When AM is set, pin 48 outputs a
1 mA current, which turns HCC OFF.
42
10kΩ
AM/FM
SW
AM/FM
SW
MRC
43
MRC control voltage
time constant
A13341
The MRC detection time constant is
determined 1 kΩ and C2 when
discharging and by a constant
current of 7 µA and C2 when
charging.
VCC
VCC
C2
43
＋
7μA
500Ω
5kΩ
to pin 44
A13343
44
SNC control input pin
Controls sub-output with an input of 0
to 1 V.
SNC voltage is determined by the RA
and RB component voltage. This
sets the separation blend curve.
VREF
VCC
＋
VCC
43
RB = 5 kΩ on chip
RA is external
RB
RA
44
A13344
45
HCC control input pin
VREF
Controls high frequency output with
an input of 0 to 1 V.
Control through the MRC output is
also possible.
Use at least a 100 kΩ resistor when
using pin 48 FM S-meter for control.
48
45
＋
1μF
A13345
Continued on next page.
No. 6522-34/54
LA17000M
Continued from preceding page.
Pin No.
46
47
Function
Equivalent circuit
Noise canceller input
AM/FM detection
output
Description
Pin 46: N.C. input
Input impedance 50 kΩ
VCC
FM
detection
output
Pin 47: AM.FM detection output
For FM: Low impedance
For AM: 10 kΩ output
To improve low-band separation, use
a coupling capacitor of at least 10 µ.
47
10kΩ
VCC
1μF
AM
detection
＋
46
50kΩ
4.2V
A13346
48
IF S-meter output and
MRC DC input pin
FM S-meter output block
MRC AC input block
VCC
Adjust an external 1-kΩ resistor to
attenuate and control the MRC AC
input.
48
10kΩ
＋
1μF
1kΩ
MRC input
A13347
49
Mute driver output
1) The mute time constant is
determined by an external CR as
follows:
Attack time
TA = 10 kΩ × C1
C1
＋
0.1μF
Release time
TR = 50 kΩ × C1
49
VCC
50kΩ
SEEK
OFF
SOFT
MUTE
MUTE
AMP.
10kΩ
HOLE
DET
BAND
MUTE
50kΩ
SD circuit
2) Noise convergence adjustment
Fine adjustments can be made
when there is no input to the ANT
input by inserting a resistor
between pin 49 and GND.
3) Mute off function
Short pin 49 with GND using a
4-kΩ resistor.
A13348
Continued on next page.
No. 6522-35/54
LA17000M
Continued from preceding page.
Pin No.
50
51
52
53
Function
AFC
QD output
QD input
VREF
Equivalent circuit
0.1μF V
REF
Description
• R1: Resistor that determines the
band muting function.
Increasing the value of R1 narrows
the band
Reducing the value of R1 widens
the band.
R1
VCC
C
R2
53
52
51
• Null voltage
Voltage between pins 50 and 53
during tuning:
V50-53 = 0 V
Band muting turns on when
|V50-53| ≥ 0.7 V.
50
VCC
Quadrature
detection
V53 = 4.9V
390Ω
HOLE
DET
3pF
1kΩ
1F limiter AMP
BAND
MUTE
A13349
54
FM SD Adi
R
Current of 130 µA flows from pin 54
and comparison voltage is
determined by external resistance.
SD ADJ
54
130μA
＋
−
SD
Comparator
42
S-meter
55
Keyed AGC
AM stereo buffer
S-meter
A13350
The keyed AGC operates when the
voltage divided by the 6.4-kΩ and
3.6-kΩ resistors on S-meter output
pin 42 falls below the voltage
determined by the resistor between
pin 55 and GND.
42
6.4kΩ
3.6kΩ
Shared pin for the AM stereo decoder
IF buffer.
Comparator
KEYED
AGC
＋
−
55
1.3V
90μA
VCC
AM IF out
50pF
150Ω
A13351
Continued on next page.
No. 6522-36/54
LA17000M
Continued from preceding page.
Pin No.
57
Function
Equivalent circuit
Description
HCC capacitor
HCC frequency characteristics are
determined by the capacitance of the
external capacitor.
VCC
20kΩ
＋
20kΩ
57
2200pF
A13352
58
AM L.C. pin
In AM mode, this changes the
frequency characteristics of the
unneeded audio band below 100 Hz
in order to produce clear audio.
VCC
C
58
VCC
DET
50kΩ
Note:
The capacitor for the LC must be
connected to VCC (pin 56) (because
the detection circuit operates with
VCC as a reference).
1kΩ
＋
−
50kΩ
1kΩ
The cutoff frequency fC is determined
by the following formula:
A13353
59
fC = 1/2 π × 50 kΩ × C
Inserting a 1-MΩ resistor between
pin 59 and VCC forces MONO.
Pilot detector
VCC
19kHz 0°
BIAS
30kΩ
30kΩ
＋
30kΩ
59
1μF
＋
A13354
Continued on next page.
No. 6522-37/54
LA17000M
Continued from preceding page.
Pin No.
60
Function
Equivalent circuit
IF AGC
＋
0.022μF
240kΩ
58
DET
60
Description
Q1: Seek time constant switch
τ = 2.2 µF × 300 k
VCC
C
2.2μF
2 SEEK
τ = 2.2 µF × 10
Connect external C to VCC (because
the IF amplifier operates with VCC as
a reference).
VCC
50kΩ
50kΩ
IF
AGC
G1
SEEK
ON
10Ω
A13355
61
Pin56 VCC
IF output
61
IF amplifier load
Pin56 VCC
DET
A13356
62
AM
ANT damping
drive output
Wideband AGC input
I62 = 6 mA max
ANT damping current
VCC
50pF
62
100Ω
20kΩ
VCC
W.AGC AMP.
ANT DAMPING
DRIVER
A13357
Continued on next page.
No. 6522-38/54
LA17000M
Continued from preceding page.
Pin No.
63
Function
Equivalent circuit
FM mute on Adjust
Description
Vary the external resistor to adjust
the mute on level.
30kΩ
R
63
VCC
140μA
＋
−
24ピン
Inverter circuit
MUTE
A13358
64
73
RF AGC bypass
RF AGC
RF AGC rectification capacitor
The distortion in low-frequency
modulation is determined as follows.
C64, C73 → Increase
Distortion → Good
Response → Slow
VCC
5.6V
10kΩ
64
＋
−
＋
Antenna
damping
3.3μF
C64, C73 → Decrease
Distortion → Worsens
Response → Fast
For AGC
73
＋
47μF
A13359
66
Be careful in regards to the GND
point for the limiter amplifier input C.
IF bypass
Ground C1 at a point that does not
increase AMR.
2.6V
67
FM IF input
10kΩ
10kΩ
66
C1
0.022μF
330Ω
67
IF in
A13360
68
IF input
Input impedance 2 kΩ
2kΩ
100Ω
68
A13361
Continued on next page.
No. 6522-39/54
LA17000M
Continued from preceding page.
Pin No.
69
72
78
Function
IF amplifier output
IF amplifier input wide
input
IF amplifier input
narrow input
Equivalent circuit
Description
VCC
1.3kΩ
IF OUT 69
500Ω
W IF IN 72
300Ω
300Ω
300Ω
V59 = 5.3 V
Output impedance
ROUT = 330 Ω
2.75V
N IF IN 78
SW2
SW1
A13362
70
65
MIX output 130 µA
MIX input
• 1ST.IF amplifier I/O pin
• Inversion amplifier
V78 = 2 V Narrow 1st IF input
V72 = 2 V Wide 1st IF input
Input impedance
RIN = 330 Ω
Pin 56
VCC
When SW1 open, SW2 short
When SW1 short, SW2 open
Switched by the CF band, switched
by voltage on pin 10.
Wire the MIX coil that is connected to
the pin 70 MIX output to pin 56
(VCC).
VCC pin 56
Pin 65 MIX input.
Input impedance
330 Ω
70
OSC
65
330Ω
A13363
71
W-AGC IN
AM SD Adjust
74
N-AGC IN
mute attenuation
adjusting pin
Pin 77
VCC
W-AGC
N-AGC
Pin 71, 74 DC cut capacitors are on
chip.
The AGC on level is determined by
the capacitance of C1 and C2.
Pin 71 is the SD sensitivity adjusting
pin for AM.
71
C1
MIX
IN
Output current I71 = 50 µA, and V71
varies according to the external
resistance.
SD is put into operation by
comparing V71 with the S-meter
voltage.
30pF
50pF
74
50μA
＋
−
MIX
OUT
S-meter
AM SD
A13364
Continued on next page.
No. 6522-40/54
LA17000M
Continued from preceding page.
Pin No.
75
76
80
Function
Equivalent circuit
Description
MIX ouput
1ST.IF
Double-balance type mixer
Pins 75 and 76, MIX output,
10.7 MHz output
O S C
MIX input
75
VCC
76
30Ω
Pin 80, MIX input
Emitter injection method and injection
amount are determined by the values
of C1 and C2.
Note:
The line for pin 80 must not approach
pins 75 and 76.
VCC
C1
10kΩ
80
5pF
RF AMP
500Ω
500Ω
A13365
79
1st MIX
INPUT
1st MIX input
Input impedance:
approximately 10 kΩ
AM 1st
MIX
to RF
Amp.
79
10kΩ
2.1V
A13368
No. 6522-41/54
LA17000M
Methods for Using the LA17000M
(1) About VCC and GND
Pin 56
VCC for FM IF, AM, NC, MPX, and MRC
Pin 39
GND for FM IF and AM
Pin 14
GND for NC, MPX and MRC
Pin 77
VCC for FM FE, AM 1st MIX, and 1st OSC
*Pin 6
VCC for FM FE and AGC, and AM/FM switch
Pin 3
GND for FM FE, AM 1st MIX, and 1st OSC
(2) Notes on AM coil connection
VCC for the 1st OSC coil that is connected to pin 7 should have the same electric potential as pin 77.
Connect pin 61 IFT to pin 70 MIX coil. VCC should have the same electric potential as pin 56.
(3) AM/FM switch
Pin 6 serves as FM, FE, and RFAGC VCC.
V
6pin
8
Pin 6 voltage
3.3
AM
FM
Mode
8
FM
OPEN
AM
AM
A13369
(4) Relationship between pin 38 and pin 17
4-1. For FM
Pin 17
STEREO indicator and SD dual-purpose pin
Pin 38
DC input SEEK, STOP pin (control pin)
AC output IF count buffer pin
38
51kΩ
17
5V
IF count buffer
51kΩ
SW1
0 to several kΩ
5V
100kΩ
SW2
A13370
A13371
SW1
SW2
Pin 38 voltage
Pin 17
OPEN
OPEN
5V
IF count buffer on
Pin 17
SD
ON
OPEN
2.5 V
IF count buffer on
High-speed SD
—
ON
0.7 V or less
OFF
Stereo indicator
Relationship Between Pin 38 Control Method and Output from Pins 38 and 17
No. 6522-42/54
LA17000M
Relationship between FMSD, IF count buffer output, S-meter, and mute drive output
S-meter
V42
R38 larger
V54
R38 smaller
V49
V49
0.7 V or
more
V49
0.7 V or
more
V17
5V
ON as
SD
SD
ON Stereo
SD ON
Monaural
V38AC
OFF
V38DC
IF count
buffer
on
OFF
IF count output ON
Note: IF count output is off in the LA1780/81. Turn the
IF count output on in the LA17000M only.
(This is done for use in detecting interference from
adjacent frequencies.)
5V
2.5V
0V
Switch this mode for use in SD
detection in RDSAF search, etc.
Use 2.5 V mode for detecting interference
from adjacent frequencies, and confirm
the IF count frequency.
A13372
About FM SD
4.9V
R
＋
−
R
＋
−
R
Band
mute
Mute drive
output
HOLE
CLET
STEREO
IND
Smeter
IF count buffer
＋
−
54
42
Connected
directly to PLL
and I/O-3
FM IF
49
38
17
5V
51kΩ
IF count output
2.5V 5V
SD
STEREO/MONO
A13373
No. 6522-43/54
LA17000M
4-2. For AM
S-meter
V42pin
R71 larger
V71
R71 smaller
V17
SD ON
V38AC
IF Buffer ON
OFF
V38DC
5V
0V
A13374
Pin 71 AM, SD, Adj Pin
(5) AM STEREO support pin
To AM ST decoder
VCC
GND
400 mVrms
450 kHz output
IFT
61
55
VCC
50pF 150Ω
KEYED AGC
IF AMP.
A13375
• To attenuate the pin 55 AC level, add capacitance between GND and pin 55. For example, if pin 67 is added between
GND and pin 55, the AM IF output decreases by about 6 dB.
No. 6522-44/54
LA17000M
(6) About MUTE ATT
It is possible to switch to one of three levels (–20 dB, –30 dB, or –40 dB) by means of the resistor between pin 74
and GND. (This also has an effect on the total gain of the tuner.)
74
100kΩ
R
R58
Mute ATT
OPEN
–20 dB
200 kΩ
–30 dB
30 kΩ
–40 dB
A13376
The attenuation can be reduced as shown
in the table above by reducing R49.
49
R49
A13377
MUTE
DRIVE
MUTE time constant
Attack 10 kΩ × C49
Release 50 kΩ × C49
MUTE
AMP
10kΩ
50kΩ
49
C49
A13378
VCC
200kΩ
Quadrature
detector
R
MUTE AMP.
（VCA）
＋
−
R
＋
−
N-AGC
MUTE
DRIVE
Limiter
R
74
49
to MIX OUT
47
DET OUT
OPEN
200kΩ
30kΩ
A13379
No. 6522-45/54
LA17000M
(7) MRC circuit
VCC
VCC
7μA
S-meter
FM
S-meter
50Ω
DC BUFFER
MRC
28
30kΩ
6.4kΩ
R28
10kΩ
3.6kΩ
42
5kΩ
OMRC
75pF 1kΩ
NOISE AMP
fc=70kHzのMPF＋AMP
48
＋
43
＋
C43
VCC
A13380
The stereo blend curve can be adjusted
through the R28 external resistor.
1) When there is no AC noise on pin 48
V42 = V43–VBE
↑
QMRC
V43 is approximately 2.5 V when ANT input is 60 dBµ or higher.
2) Because the MRC noise amplifier gain is fixed, adjust MRC by reducing the AC input level.
48
＋
A13381
3) The MRC attack and release are determined by C43 on pin 43.
Attack 7 µA • C27
Release 500 Ω • C27
(8) FM soft mute
R63 smaller
R63 larger
V42
R63 larger
V63
R63 smaller
A13382
Compare the pin 63 MUTE ON adjusting voltage and the V42 S-meter voltage, and adjust the MUTE ON point.
No. 6522-46/54
LA17000M
(9) About the noise canceller
The noise canceller improves the characteristics by implementing the circuits that determine the gate time with a
logic circuit.
Because a conventional noise canceller determines the time
constant according to CR as shown in Fig. 5, the rise time is
dependent on the CR, as shown in Fig. 6. This caused a delay
in the rise, which resulted in a deterioration of noise filtering
performance when the rise was delayed too much.
In the LA17000, the circuits that determine the gate time have
A13383
been configured with logic, resulting in a faster rise and
making more reliable noise filtering possible.
A13384
No. 6522-47/54
LA17000M
Block Diagram
0.022µF
AM
(STEFEO)
IF OUT
MUTE
OFF(RDS)
RF AGC
+
ANT
D
62
OSC
BUFF
FM IF
IN
44
65
F.F.19k
∠90
66
BUFF
AM SM
FM SM
AM SD
FM SD
PILOT
DET.
0.22µF
PILOT
CAN.
F.F.30k
∠0
Pdot C
0.01µF ADJ
100kΩ
33
UNTVERSAL
COUNTER
32
DATA SHIFT REGISTER
LATCH
MRC
SENOR
AUTO ADJ
5V
34
0.47µF
F.F.
SEEKSW
47kΩ
I/O-1
HCTR
100pF
I/O-1 51kΩ
LPF
W.B AGC
REFERENCE
DIVIDER
Keyed
AGC
F.E
REG
75
FM/AM
SWICH
26
BUFF
77
MAIN
HC
BUFF
AGC
ANT
D
30kΩ
4
5
FM
OSC
6
7
AM/FM
SW
AM
OSC
8
9
NC
Sens
NC
AGC
10
+
0.47µF
3.3µF
+
3
FE
GND
AM VCC
AM ANT IN
FM BF GND
FM ANT IN
30kΩ
VCC=8V
11
AM
OSC
micro contlorrer
I/O-2
12
13
Gore
OUT
14
15
MPX
Pdot IN
6800pF
16
0.01µF
17
SD
ST-IND
18
19
PLL IN
22
21
XBUFF
PDS
PLL
VSS
20
PD1
10kΩ
+
51kΩ
NC MPX
GND
CF SW
10kΩ
0.22µF
22kΩ
30pF
150pF
2
FM RF
AGC
X' IN 24pF
24
PHASE
DETECTOR
CHARGE
PUMP
GATE
1MΩ
1
FM
ANTD
0.022µF
FM
MIX IN
MAT
RIX
OSC
5pF
80
TRIG
X' OUT 24pF
51kΩ
POWER
ON
RESET
23
79
5pF
SUB
DEC
AM
1ST
OSC
78
CE
10.25
MHz
— +
25
MIX
DI
10kΩ
76
27
CL
5V
100kΩ
RF AGC
28
DO
0.01µF
HPH
29
CCB
I/F
SWALLOW
COUNTER
1/16,1/17 4Bits
AM/FM
VREF
73
30
10kΩ
CF
SW
0.015µF
72
12Bits
PROGRAMMABLE
DIVIDER
TWEET
0.01µF
0.022µF
1000pF
35
31
RF AGC
WB AGC
300pF
8pF
AM 1st
MIX IN
18pF
30Ω
36
TRIG
MIX
1st IF
Narrow IN
220Ω
CSB912TF108
MPX VCO
IF BUFFER
62pF
FE VCC
0.022µF
IF COUNT BUFF
SEEK/STOP switch
37
L.C.
0.022µF
0.022µF
+
MRC
MIX OUT
100Ω
PHASE
COMP
GND
VCO
VCO
STOP
0.015µF
150Ω
IF
AGC
DET
39
38
IF LIMIT
AMP.
AM SD ADJ
71
WIDE AGC IN
200kΩ
41
PHASE
COMP.
F.F.19k
∠90
AFC
CI AMP
15Ω
1000pF
42
SNC
MUTE
DRIVE
OC-C
DET
70
N-AGC IN
MUTE ATT ADJ
30Ω
43
0.22µF
SNC
45
1µF
62kΩ
1µF
1000pF
33kΩ 56kΩ
82kΩ
560Ω
1µF
0.47µF
0.01µF
46
HCC
64
74
100kΩ
10µF
HOLE
DET
69
AM RF AGC OUT
100kΩ
30kΩ
12kΩ
63
300Ω
1st IF IN
0.1µF
MUTE
AMP.
Q.DET
OSC
67
100µF
NC
47
+
350Ω
0.022µF
100kΩ
0.022µF
48
To
microcontroller
AM/FM
S-METER
40
10pF
0.022µF
510Ω
AM MIX OUT
1000pF
49
MRC
OUT
51kΩ
1st IF OUT
30kΩ
50
50kΩ
HCC
1µF
15pF
15pF
47µF
100kΩ
100µH
0.022µF
2nd MIX IN
51
DET
OUT
61
68
37pF
52
3.3µF
FM IF BYPASS
6pF
10kΩ
53
MUTE FM
DRIVE S-METER
+
100pF
VSM
SHIFTER
+
VREF
54
AFC
IN
+
SEEK→AM/FM SD
STOP→FM ST IND
SDSTSW
L-CH
R-CH
0.022µF
100µH
+
55
11kΩ
FC18
1000pF
56
QD
IN
+
47kΩ
FM MUTE
ON ADJ
100µH
VCC
57
FM
SD
+
0.47µF
47kΩ
1MH
470Ω
0.022µF
AM ANTD
WIDE AGC
0.022µF
33Ω
58
KEYED
AGC
+
SEP
ADJ
100kΩ
AM DET
59
C.
HCC
QD
OUT
+
1µF 5.6kΩ
60
AM
LC
+
+
10kΩ
PILOT
DET
10kΩ
0.1µF 0.22µF
24kΩ
IF
AGC
100µF
+
2200pF
+
0.022µF
1µF
2.2µF
33kΩ
PLL VDD=5V
FMIF AMNC FM/AM FMIF AM
MPX VCC
VT
GND
A13385
No. 6522-48/54
LA17000M
Recommended External Components
Component name
Manufacturer
Component
number
Component model number
AM loading coil
Toko
Sumida Electronics Co., Ltd.
L1
7TL-269ANS-0720Z
SA-1062
AM ANT-IN
Toko
Sumida Electronics Co., Ltd.
L2
7PSU-385BNS-027Z
SA-1048
AM RF LPF
Toko
Sumida Electronics Co., Ltd.
L3
5VUS-A286LBIS-15327
SA-1051
AM choke coil
Toko
Sumida Electronics Co., Ltd.
L4
8RB-187LY-222J
RC875-222J
AM 2nd MIX coil
Toko
Sumida Electronics Co., Ltd.
L7
5PG-5PGLC-5310N
SA-264
AM IF coil
Toko
Sumida Electronics Co., Ltd.
L8
7PSGTC-50002Y=S
SA-1063/SA-1112
AM OSC1 coil
Toko
Sumida Electronics Co., Ltd.
L9
7KSS-V666SNS-213BY
SA-359
AM/FM MIX coil with
selectivity switch
Toko
L10
7PSG-8261N-5202D=S
AM/FM MIX coil
without selectivity switch
Sumida Electronics Co., Ltd.
Toko
L10
SA-266
371DH-1108FYH
FM detection coil
Sumida Electronics Co., Ltd.
Toko
L14
SA-208
DM600DEAS-8407GLF
FM OSC coil
Sumida Electronics Co., Ltd.
Toko
L11
SA-125 (JP), SA-278 (US)
T-666NF-251APZ (JP), T-666SNF-2471B (US)
FM RF coil
Sumida Electronics Co., Ltd.
Toko
L12
SA-143 (JP), SA-250 (US)
T-666NF-269X (JP), T-666SNF-246JA (US)
FM ANT coil
Sumida Electronics Co., Ltd.
Toko
L13
SA-144 (JP), SA-231 (US)
T-666NF-268Z (JP), T-666SNF-244X (US)
MPX ceramic oscillator
Murata Manufacturing Co., Ltd.
Kyocera
VCO1
CSB912JF108 (912 kHz)
KRB-912F108 (912kHz)
PLL X’tal oscillator
Nihon Dempa kogyo
VCO2
LN-P-0001 (10.25, 10.35 MHz)
FM ceramic filter
Murata Manufacturing Co., Ltd.
CF1
SFE 10.7MS3A50K-A
FM/AM narrow band
ceramic filter
Murata Manufacturing Co., Ltd.
CF2
SFE 10.7 MTE
AM ceramic filter
Toko
Murata Manufacturing Co., Ltd.
CF3
LFCM450H
SFPS450H
AM pin diode
SANYO Electric Co., Ltd.
PIN1
1SV234/267
AMRF FET+TR
SANYO Electric Co., Ltd.
FET1
FC18
AM OSC1 varactor
SANYO Electric Co., Ltd.
VD2
SVC252/253
FM pin diode
SANYO Electric Co., Ltd.
PIN2
1SV234
FM RF amplifier FET
SANYO Electric Co., Ltd.
FET2
3SK263/264
FM RF/ANT/OSC varactor
SANYO Electric Co., Ltd.
VD3
SVC231/208
No. 6522-49/54
LA17000M
Crystal oscillator
Nihon Dempa Kogyo Co., Ltd.
Frequency:
10.25 MHz
CL:
16pF
Model name: LN-P-0001
10.35 MHz
16pF
LN-P-0001
Coil specifications
Sumida Electronics Co., Ltd.
[AM block]
AM FILTER (SA-1051)
1
2
AM OSC (SA-359)
S
3
3
4
2
6
4
1
AM IF1 (SA-264)
3
AM IF2 (SA-1063)
4
2
1
6
1
S
S
S
AM loading (SA-1062)
4
6
AM ANT IN (SA-1048)
4
3
2
1
4
3
S 2
3
6
2
6
1
S
6
S
For AM RF amplifier (RC875-222J)
0.1φ2UEW
[FM block]
FM RF (SA-1060)
S
3
4
4
3
6
1
6
S
S
FM OSC (SA-1052)
3
4
FM MIX (SA-266)
S
3
C1
4
8
2
1
(without selectivity switch)
2
2
1
FM ANT (SA-1061)
2
6
S
1
7
C2
6
S
FM DET (SA-208)
S
S
3
4
2
1
6
No. 6522-50/54
LA17000M
TOKO Co., Ltd.
[AM block]
AM FILTER (A286LBIS-15327)
1
2
3
AM OSC (V666SNS-213BY)
3
4
2
6
4
1
AM IF1 (7PSGTC-5001A=S)
3
6 0.05φ3UEW
AM loading (269ANS-0720Z)
3
1
6 0.05φ3UEW
AM ANT IN (385BNS-027Z)
3
4
4
2
2
1
4
2
2
1
AM IF2 (7PSGTC-5002Y=S)
3
4
6 0.1φ2UEW
6 0.05φ3UEW
1
6 0.06φ3UEW
For AM RF amplifier (187LY-222)
0.1φ2UEW
[FM block]
FM RF (V666SNS-208AQ)
S 3
4
2
1
4
2
1
φ0.12−2UEW
6 S
FM DET (DM600DEAS-8407GLF)
3
4
2
1
3
4
2
φ0.1−2UEW
6 S
FM OSC (V666SNS-205APZ)
3
FM ANT (V666SNS-209BS)
6 0.07φ2MUEW
φ0.1−2UEW
1
6 S
FM MIX (371DH-1108FYH)
S 3
4
2
5
1
6 S
(without selectivity switch)
φ0.07−2UEW
FM MIX (826IN-5202D=S)
3
4 S
2
5
S 1
(with selectivity switch)
External 82P2 in parallel (1-G, 3-G)
6 φ0.062UEW
No. 6522-51/54
LA17000M
20
VSM
MOD ON
SEP
−40
AMR
MOD OFF
−60
0
AF output, noise – dB
−20
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
VSM, THD − V, %
AF output, noise – dB
0
−80
MOD ON
VSM
−20
−40
MOD OFF
THD 30％
fm=400Hz
−60
−80
0
40
20
60
80
100
120
140
−100
−20
20
0
ANT input, IN – dBµ
AM2 Signal Interference Characteristics
60dBμ
S＋N
N
μI
B
40d
IN
Bμ
ON
VCC=8.5V
u
6
fD=1000kHz
od
m
fm=400Hz
fud
IN
Bμ
d
modu=30％
0
8
fuD=1040kHz
fm=1kHz ON/OFF
modu=30％
0d
−40
−60
60
80
100
120
140
ANT input, IN – dBµ
FM Antenna input Temperature Characteristics (1)
5
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev= kHz
ANT IN=80dBμ
4
3
2
1
dev=22.5kHz
−20
0
20
AF output, noise – dB
−20
40
60
8
120
140
80dBμS＋N
60dB
40dBμS＋N
μS＋
N
−20
40dBμIN
IN
Bμ
d
60
VCC=8.5V
fD=1000kHz
IN
fm=400Hz
Bμ
80d
modu=30％
fuD=1400kHz
fud modu ON
fm=1kHz ON/OFF
modu=30％
−40
−60
−80
40
60
80
100
120
140
ANT input, IN – dBµ
FM Antenna input Temperature Characteristics (2)
100
80
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
ANT IN=80dBμ
80
60
40
20
0
−40
100
6
0
20
40
60
80
100
FM Antenna input Temperature Characteristics (4)
80
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
7
−20
Ambient temperature, Ta – °C
VSM=60dBμ
4
40dBμ
3
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
60
LS − dBμ
S-meter voltage, VSM — V
100
dev=75kHz
FM Antenna input Temperature Characteristics (3)
2
80
AM2 Signal Interference Characteristics
Ambient temperature, Ta – °C
5
60
0
Separation, Sep — dB
AF output, noise – dB
40dBμS＋N
−80
40
Total harmonic distortion, THD – %
20
80dBμS＋N
0
40
ANT input, IN – dBµ
20
0
−40
THD 80％
fm=400Hz
THD 100％
THD 30％
−100
−20
AM I/O Characteristics
VCC=8.4V
fr=1MHz
fm=1kHz
dev=30％
VSM, THD − V, %
FM I/O Characteristics
20
40
20
20dBμ
LS
1
−20dBμ
0
−40
−20
0
20
40
60
Ambient temperature, Ta – °C
80
100
0
−40
−20
0
20
40
60
80
100
Ambient temperature, Ta – °C
No. 6522-52/54
LA17000M
100
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
S/N, AMR − dB
80
S/N
60
AMR
40
20
0
−40
−20
0
20
40
60
Ambient temperature, Ta – °C
80
FM Antenna input Temperature Characteristics (6)
40
Output voltage, VO – dBm
FM Antenna input Temperature Characteristics (5)
20
0
fm=1kHz
−20
fm=10kHz
−40
−60
−80
−40
100
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
ANT IN=80dBμ
0
−20
20
40
60
Ambient temperature, Ta – °C
80
100
FM Antenna input Temperature Characteristics (7)
VCC=8.4V
fr=98.1MHz
fm=1kHz
dev=22.5kHz
100
W-AGC
80
N-AGC
60
40
SD
20
0
−40
−20
0
20
40
60
80
100
Total harmonic distortion, THD – %
Ambient temperature, Ta – °C
AM Antenna input Temperature Characteristics (1)
5
VCC=8.4V
fr=1MHz
fm=400Hz
ANT IN=80dBμ
4
3
2
0％
dev=8
1
AM Antenna input Temperature Characteristics (2)
5
S-meter voltage, VSM — V
SD, W-AGC N-AGC − dBμ
120
4
3
VSM =60
dBμ
2
1
40dBμ
−20dBμ
20dBμ
dev=30％
0
−40
−20
0
20
40
60
80
0
−40
100
Ambient temperature, Ta – °C
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
100
80
60
AGCFOM
40
20
0
−40
−20
0
20
40
60
80
Ambient temperature, Ta – °C
0
20
40
60
80
100
100
AM Antenna input Temperature Characteristics (4)
100
SD sensitivity, SD – dBµ
120
−20
Ambient temperature, Ta – °C
AM Antenna input Temperature Characteristics (3)
AGCFOM − dB
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
ANT IN=80dBμ
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
80
60
40
SD
20
0
−40
−20
0
20
40
60
80
100
Ambient temperature, Ta – °C
No. 6522-53/54
LA17000M
AM Antenna input Temperature Characteristics (5)
120
W-AGC, N-AGC − dBμ
100
AM Antenna input Temperature Characteristics (6)
120
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
100
W-AGC
80
S/N − dB
80
N-AGC
60
40
20
20
−20
0
20
40
60
Ambient temperature, Ta – °C
80
100
S/N
60
40
0
−40
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
ANT IN=80dBμ
0
−40
−20
0
20
40
60
Ambient temperature, Ta – °C
80
100
AM Antenna input Temperature Characteristics (7)
Output voltage, VO – dBm
40
VCC=8.4V
fr=1MHz
fm=400Hz
dev=30％
ANT IN=80dBμ
20
0
VO
−20
−40
−60
−80
−40
−20
0
20
40
60
80
100
Ambient temperature, Ta – °C
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of June, 2001. Specifications and information herein are subject to
change without notice.
No. 6522-54/54