SANYO LA4587

Ordering number: EN5204A
Monolithic Linear IC
LA4587M
Preamplifier + Power Amplifier
for 1.5 V Headphone Stereos
Overview
Package Dimensions
The LA4587M is a system IC that includes all of the necessary
functions for a playback set on a single chip, reducing the
number of external components needed.
unit : mm
3102-QFP48D
[LA4587M]
Functions
. Stereo preamplifier (supports auto reverse function,
between metal and normal tape)
. switchable
Stereo power amplifier (OCL, mute function)
. Ripple filter
. Low boost function (BTL operation in low-frequency range)
. AMSS (Automatic Music Select System)
. Power switch
Features
. Preamplifier has a high open-loop gain (VG = 73 dB).
. Preamplifier requires no NF capacitor.
. Virtual ground capacitor can be 1 µF or less. (Lower
amplifier built in.)
is achieved by having a V
. impedance
Ripple filter requires no capacitor for preventing oscillation.
. Powerful output is obtained in low boost output
= 21 mW/V = 1.2 V, f = 100 Hz).
. (Po
A high-frequency cutoff capacitor is built into the
O
SANYO : QIP48D
CC
preamplifier and power amplifier inputs; anti-buzz provision.
Specifications
Allowable power dissipation, Pd max − mW
REF
Ambient temperature, Ta − °C
Maximum Ratings at Ta = 25 °C
Parameter
Maximum supply voltage
Allowable power dissipation
Symbol
Conditions
Ratings
Unit
VCC max
3.0
V
Pd max
635
mW
Operating temperature
Topr
–10 to +60
°C
Storage temperature
Tstg
–40 to +125
°C
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
13097HA(II)/N3095HA(II) No.5204-1/18
LA4587M
Operating Conditions at Ta = 25 °C
Parameter
Symbol
Recommended supply voltage
VCC
Operating supply voltage range
VCC op
Conditions
Ratings
Unit
1.5
V
0.95 to 2.2
V
Operation Characteristics at Ta = 25 °C, VCC = 1.2 V, f = 1 kHz, 0.775 V = 0 dBm,
RL = 10 kΩ (preamplifier), RL = 16 Ω (power amplifier)
Parameter
[Preamplifier + Power Amplifier]
Quiescent current
Voltage gain (closed)
[Preamplifier]
Voltage gain (open)
Voltage gain (closed)
Maximum output voltage
Total harmonic distortion
Equivalent input noise voltage
Interchannel crosstalk
Interchannel crosstalk between
F and R
Ripple rejection ratio
Symbol
ICCO1
ICCO2
VGT
Conditions
Rg = 2.2 kΩ, Rv = 0 Ω
When power switch is off
VO = –20 dBm, RV = 10 kΩ
min
8
54
typ
15
0.1
57
max
Unit
24
5
60
mA
µA
dB
VG0
VG1
VG2
VO max
THD1
VNI
CT1
VO = –20 dBm
VO = –20 dBm
VO = –20 dBm, f = 10 kHz, metal on
THD = 1 %
VG = 35.5 dB/NAB, VO = 100 mV
Rg = 2.2 kΩ, BPF: 20 Hz to 20 kHz
Rg = 2.2 kΩ, 1 kHz TUNE, VO = –20 dBm
60
34
25.5
100
45
73
35.5
28
210
0.1
1.3
56
CT2
Rg = 2.2 kΩ, 1 kHz TUNE, VO = –20 dBm
65
78
dB
Rr1
Rg = 2.2 kΩ, Vr = –30 dBm,
fr = 100 Hz, 100 Hz TUNE
45
52
dB
20.5
20.5
24.5
30
5
13
23
23
27.5
34
9
21
0.5
43
35
37
30.5
0.5
3.0
dB
dB
dB
mV
%
µV
dB
[Low Boost + Power Amplifier]
Voltage gain (closed)
Output power
Total harmonic distortion
Interchannel crosstalk
Output noise voltage
Ripple rejection ratio
Output mute voltage
Input resistance
Voltage gain difference
[Ripple Filter ]
VG3
VG4
VG5
VG6
PO1
PO2
THD2
CT3
VNO
Rr2
VM
Ri
∆VG3
Ripple rejection ratio
Rr3
Output voltage
[AMSS]
VRF
Operating output voltage
VOAMSS
VO = –20 dBm
VO = –20 dBm, L.B. = on
VO = –20 dBm, L.B. = on, f = 10 kHz
VO = –20 dBm, L.B. = on, f = 100 Hz
THD = 10 %
THD = 10 %, f = 100 Hz, L.B. = on
PO = 1 mW
VO = –20 dBm, RV = 0 Ω
RV = 0 Ω, BPF: 20 Hz to 20 kHz
RV = 0 Ω, Vr = –30 dBm,
fr = 100 Hz, 100 Hz TUNE
VIN = –30 dBm, 1 KHz TUNE, mute on
fr = 100 Hz, Vr = –30 dBm, VCC = 1.0 V,
IRF = 25 mA, 2SB1295, hFE6 rank used
VCC = 1.0 V, IRF = 25 mA
Preout voltage when AMSS VO = 0.6 Vp-p
Pin 34 is short-circuited through 270 kΩ.
38
25.5
25.5
30.5
38
1.5
48
dB
dB
dB
dB
mW
mW
%
dB
µV
50
74
dB
8
10
0
33
39
dB
0.89
0.93
V
1.80
2.55
–85
12
+1.5
3.60
dBm
kΩ
dB
mV
Note: L.B. = Low boost
No.5204-2/18
LA4587M
Block Diagram
Unit (resistance: Ω)
Test Circuit Diagram
Unit (resistance: Ω, capacitance: F)
No.5204-3/18
LA4587M
Sample Application Circuit
Unit (resistance: Ω, capacitance: F)
Note 1: Transistors equivalent to the 2SB1295 with hFE6 rank and upward are recommended.
Note 2: C18, C23, and C26 are oscillation prevention capacitors; a polyester film or ceramic capacitor (which can guarantee the
specified capacitance at operating temperatures) is recommended.
No.5204-4/18
LA4587M
Pin Functions
Unit (resistance:Ω, capacitance: F)
Pin No.
Pin name
45
R.F OUT
2
POWER OUT1
7
POWER OUTC
13
POWER OUT2
3
POWER NF REF1
9
POWER NF REFC
12
POWER NF REF2
4
POWER NF1
8
POWER NFC
11
POWER NF2
5
POWER H.P1
10
POWER H.P2
14
L.P2
Pin voltage
[V]
1.13
Internal equivalent circuit
* Pin voltage is when VCC = 1.2 V
Remarks
0.6
c A 160 Ω resistor is connected
between individual outputs
(between pins 2 and 7, and
between pins 13 and 7).
0.75
c Each power NF connection
0.75
c Each power NF connection.
0.75
c Grounded to VREF through a
1 kΩ resistor when low boost
is on (pin 41: floating).
0.75
c Low boost secondary LP
connection.
Continued on next page.
No.5204-5/18
LA4587M
Unit (resistance: Ω, capacitance: F)
Continued from preceding page.
Pin No.
Pin name
15
Low Boost NF
16
POWER IN2
18
POWER IN1
17
Pin voltage
[V]
0.75
Internal equivalent circuit
Remarks
c Low boost amplifier NF
connection.
0.75
c Each power input connection.
c The input resistance is
10 kΩ.
c An anti-buzz capacitor is built
in.
L.P1
0.75
c Low boost primary LP.
connection.
19
NFC2
0.75
20
NFC1
21
PRE NF1
28
PRE NF2
22
PRE OUT1
27
PRE OUT2
0.75
c Each preamplifier NF
connection.
c NF requires no capacitor.
0.45
c 200 kΩ is connected
between each output pin and
NF pin.
Continued on next page.
No.5204-6/18
LA4587M
Unit (resistance: Ω, capacitance: F)
Continued from preceding page.
Pin No.
Pin name
Pin voltage
[V]
0
23
METAL1
26
METAL2
24
AMSS IN1
25
AMSS IN2
29
PRE REV IN1
30
PRE REV IN2
31
PRE FWD IN2
32
PRE FWD IN1
33
VREF
0.75
34
REF
0.75
36
AMSS OUT
Internal equivalent circuit
Remarks
c Connected to GND through
3.9 kΩ in metal on mode (pin
40: floating)
0.75
c AMSS inverting input
connection.
c An external input resistor is
required.
0.75
b Pins 29 and 30 turn on in
REV mode (pin 39: GND).
c Pins 31 and 32 turn on in
FWD mode (pin 39: floating)
c When not using the head, a
bias resistor (2.2 kΩ) is
required between these pins
and VREF (pin 33).
c An anti-buzz capacitor is built
in.
c VREF amplifier output. Low
impedance is achieved due
to the output resistor (ro =
10 Ω).
c Inflow/outflow current:
200 µA max.
c The VREF amplifier is
referenced hereto.
c Outputs a pulse waveform in
accordance with the AMSS
IN (pins 24 and 25) input
level.
Continued on next page.
No.5204-7/18
LA4587M
Unit (resistance: Ω, capacitance: F)
Continued from preceding page.
Pin No.
Pin name
Pin voltage
[V]
Internal equivalent circuit
Remarks
37
POWER MUTE SW
41
Low Boost SW
38
POWER SW
c Power on when grounded.
39
FWD/REV SW
40
METAL SW
c When pin 39 is floating: FWD
mode; when grounded: REV
mode.
c When pin 40 is in FL mode:
metal on.
44
R.F REF
1.13
c RF is referenced hereto. An
external capacitor can be
used to vary RF SVRR.
46
R.F BASE
0.5
c Used for external PNP
transistor base drive.
c When pin 37 is grounded,
mute is on.
c When pin 41 is floating, low
boost is on.
No.5204-8/18
LA4587M
Description of External Components
.C
1
(1.0 to 10 µF):
.C,C :
. C , C (0.47 to 3.3 µF):
.C,C:
.C,C:
. C (0.1 to 22 µF):
. C , C (3.3 to 10 µF):
. C , C (1.0 to 3.3 µF):
.C ,C :
. C (1.0 to 4.7 µF):
. C , C , C (0.1 to 1.0 µF):
. C , C , C (3.3 to 10 µF):
VREF amplifier is referenced to this decoupling capacitor.
The VREF SVRR depends on the value of this capacitor.
Note that if the capacitance is reduced, the SVRR worsens.
2
10
Playback preamplifier EQ constant.
3
9
Preamplifier output capacitor.
4
8
AMSS input HPF capacitor.
5
7
EQ constant for metal (built-in resistance 3.9 kΩ ±15%).
6
VREF decoupling capacitor.
For high-frequency noise rejection.
11
12
NFC decoupling capacitor.
Note that if the capacitance is reduced, the preamplifier low-frequency gain decreases.
13
15
Power amplifier input capacitor (Input resistance: 10 kΩ).
14
17
Capacitor for low boost LPF.
The low boost gain depends on the capacitance.
16
Boost amplifier NF capacitator.
Note that if the capacitance is reduced, the low boost low-frequency gain decreases.
18
23
26
Oscillation blocking capacitator.
19
22
25
Power amplifier NF capacitor.
Note that if the capacitance is reduced, the power amplifier low-frequency gain decreases.
.C ,C :
. C (100 to 2200 pF):
. C (4.7 to 10 µF):
. C (22 to 220 µF):
. C (2.2 to 10 µF):
. C , C (0.047 to 0.22 µF):
.R,R :
.R,R:
.R,R:
.R,R:
.R,R:
.R ,R ,R :
. R , R (100 to 430 kΩ):
20
24
Bass high boost capacitor.
The high gain depends on the capacitance.
21
Oscillation blocking capacitator.
29
RF output decoupling capacitor. (Also serves as the power supply capacitor and the
oscillation blocking capacitor.)
28
Power supply capacitor.
30
RF is referenced to this LPF capacitor.
The RF SVRR depends on the capacitance.
31
32
Switching circuit smoothing capacitor. Must be adjusted according to the set timing.
1
10
For preamplifier gain adjustment.
2
9
Playback preamplifier EQ constant.
3
8
EQ constant for metal.
4
7
10 kΩ volume control.
5
6
For AMSS gain adjustment and HPF.
11
12
14
15
13
For oscillation blocking.
For switching circuit smoothing (discharge resistors).
No.5204-9/18
LA4587M
Operation Descprition
. Low boost system
Low-frequency region amplification: 12 dB/oct, high-frequency region amplification: 6 dB/oct.
Phase 90 °
Phase 180 °
. Note on low boost
The signals that are applied to each power input are mixed and then passed through a two-stage LPF. Because the signal levels
are attenuated by the LPF, level compensation is accomplished by amplifying the signals through a low boost amplifier located
in between. The phase of signals that pass through the secondary LPF is inverted relative to the input signal; these signals are
then input to each power amplifier.
. Note on channels 1 and 2
The positive phase signals that were input from the positive (‘‘+’’) input pins and the reverse phase signals that were input from
the negative (‘‘–’’) input pins and then were passed through the secondary LPF are all input, amplified, and then output.
. Note on the common amplifier
The phase of the signals that passed through the secondary LPF is inverted by the inverting amplifier; the signals (with reversed
phases relative to channels 1 and 2) are then input to the negative (‘‘–’’) inputs. The positive (‘‘+’’) input signals are grounded
to VREF, amplified by the inverting amplifier and then output.
The phase of the channel 1 and 2 amplifier outputs and the common amplifier outputs are made to oscillate with inverted
phases, making it possible to obtain the dynamic range efficiently.
No.5204-10/18
LA4587M
Sample Application Circuits for Low Boost Switching
Sample 1
Sample 2
In the above circuits, MID and MAX are switched by changing the gain of the boost amplifier.
The AMSS comparator
Block Diagram
No.5204-11/18
LA4587M
Operation Description
. The input amplifiers are inverting amplifiers. The gain and HPF characteristics can be adjusted through an external C-R
impedance).
. (input
The AMSS comparator outputs pulses for an input waveform that satisfies certain set conditions (frequency and voltage
level).
Input
Output
.When AMSS is not used, the input pins (pins 24 and 25) are connected to V
(pin 33).
REF
Notes on the ripple filter
. The RF SVRR can be adjusted by an external capacitor connected to pin 44.
3.3 µF → 39 dB
4.7 µF → 42 dB
10 µF → 47 dB
. It is recommended that external transistors be equivalent to the 2SB1295 with h
FE
6 rank and upward.
Note on power output
.The power amplifier output and the common amplifier output are connected by a resistor of approximately 160 Ω.
Notes on power mute
. Power mute turns off the fixed current that is supplied to the power section.
. The output DC when power mute is on is the V electric potential (0.75 V).
. The output impedance when power mute is on is approximately 10 kΩ.
REF
No.5204-12/18
LA4587M
SW Pin Equivalent Circuit Diagram
1. Power switch
On when power switch is grounded
IO = VCC/200 k + VCC – 0.7 V/22 kΩ
Pin 38
VS = 100 mV or less
2. Power mute and low boost switch
On when pin 37 power mute is grounded
On in pin 41 low boost switch floating mode
IO = 0.1 µA or less
VS = 80 mV or less
* The discharge resistance for
smoothing is 430 kΩ max.
3. FWD/REV, METAL switch
REV when pin 39 FWD/REV is grounded
On in pin 40 metal floating mode
IO = 7 µA or less
VS = 0.5 V or less
No.5204-13/18
LA4587M
Preamplifier
Open loop gain, VGo — dB
Closed loop gain, VG — dB
Quiescent current, ICCO — mA
VG,VGO – fi
On
On
DIN AUDIO used
Normal
Metal
Open-loop gain, VGo — dB
Closed-loop gain, VG — dB
Total harmonic distortion, THD — %
Supply voltage, VCC — V
VG, VGO – VCC
Preamplifier
to
Supply voltage, VO — mV
CT − fi between FWD/REV
Preamplifier
Crosstalk, CT — dB
Crosstalk, CT — dB
Supply voltage, VCC — V
Interchannel CT − fi
Frequency, fi — Hz
THD – VO
Preamplifier
Preamplifier
CVREF
used
used
Crosstalk, CT — dB
Between FWD/REV
Interchannel CT
Preamplifier
Frequency, fi — Hz
Output noise voltage, VNO — µV
Frequency, fi — Hz
Preamplifier
to
Supply voltage, VCC — V
Supply voltage, VCC — V
No.5204-14/18
LA4587M
VREF
Preamplifier
VREF
Ripple rejection ratio, SVRR — dB
VODC — %
VREF — %
VREF
FWD/REV
equivalent
Pre + VREF
Supply voltage, VCC — V
Supply voltage, VCC — V
VOUT — VCC
VOUT — fi
Output, VOUT — dBm
Output, VOUT — dBm
CVREF
VREF
CVREF
Supply voltage, VCC — V
Frequency, fi — Hz
VREF — IVREF
ro — Ω
VREF — V
VREF
VREF
CVREF
VREF
IVREF — µA
VO
Pre out. = 6 mV
Input H.P.
Input on both channels
Input on one channel
Pre-output — Hz
Operating output voltage, VoAMSS — mV
Operating output voltage, VoAMSS — mV
Supply voltage, VCC — V
VO
Input on both channels
Pre out. = 6 mV
Input on one channel
Supply voltage, VCC — V
No.5204-15/18
Pre-output — mV
Supply voltage, VCC — V
IRFO
Output ripple current, IRFO
— mA
Frequency, fR — Hz
Ripple rejection ratio, SVRR — dB
Operating output voltage, VoAMSS — mV
Output ripple voltage, VRFO — V
Input H.P
Ripple rejection ratio, SVRR — dB
Output ripple voltage, VRFO — V
Ripple rejection ratio, SVRR — dB
Input on one channel
Output ripple voltage, VRFO — V
Ripple rejection ratio, SVRR — dB
Output ripple voltage, VRFO — V
Input on both channels
Ripple rejection ratio, SVRR — dB
Output ripple voltage, VRFO — V
Ripple rejection ratio, SVRR — dB
LA4587M
Supply voltage, VCC — V
Supply voltage, VCC — V
IRFO
Output ripple current, IRFO
VRFO,
— mA
Ripple voltage, VR — mV
No.5204-16/18
LA4587M
fi
When low boost is on
Output on both
channels
When low boost is off
Voltage gain, VG — dB
Voltage gain, VG — dB
on
on
on
off
VO
Output on both channels
on
Supply voltage, VCC — V
PO
Output power, PO — mW
Output voltage, VO max — V
Frequency, fi — Hz
VO
Input on both channels
Supply voltage, VCC — V
PO — fi
L.B.= on
Output power, PO — mW
Output voltage, VO max — V
Supply voltage, VCC — V
VO max — fi
Input on both channels,
Load on both channels
L.B. + Power
Total harmonic distortion, THD — %
VODC — V
L.B. = on
Input on both chanels,
Load on both channels
Frequency, fi — Hz
THD — fi
Frequency, fi — Hz
Supply voltage, VCC — V
on
Input on both
channels
on
off
Input on both
channels No filter
Frequency, fi — Hz
No.5204-17/18
LA4587M
Crosstalk, CT — dB
off
on
on
off
Supply voltage, VCC — V
Frequency, fi — Hz
Ripple rejection ratio, SVRR — dB
Output noise voltage, VNO — µV
fi
off
on
Supply voltage, VCC — V
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment,
nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or
indirectly cause injury, death or property loss.
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
1 Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors
and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and
expenses associated with such use:
2 Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO
ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume
production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use
or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of January 1997. Specifications and information herein are subject to change without notice.
No.5204-18/18