Ordering number : EN5717 LA6542M Monolithic Linear IC LA6542M 4-Channel Bridge (BTL) Driver for CD-ROM Overview Package Dimensions The LA6542M is a 4-channel bridge (BTL) driver developed for CD-ROM applications. unit: mm 3204-MFP36SLF [LA6542] 19 • Integrated muting circuit (MUTE: Output OFF at Low, output ON at High. MUTE1 is for channels 1 and 2, and MUTE2 for channels 3 and 4.) 1 18 9.2 7.9 • 4-channel power amplifier with bridge circuit (BTL) • IOmax: 1A 0.15 • Slew rate 0.5 V/µs • Integrated thermal shutdown circuit 0.35 0.8 0.85 0.1 2.15 2.5max 15.3 10.5 36 0.65 Functions SANYO : MFP36SLF Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Conditions Maximum supply voltage 1 VCCmax Maximum supply voltage 2 VSmax VS1, 2 VINmax Input pins VIN1 to 4 Maximum input voltage Mute pin voltage Allowable power dissipation Ratings VMUTEmax Pd max IC only Unit 14 V 14 V 13 V 13 V 0.9 W Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended operation voltage 1 VCC 4 to 13 V Recommended operation voltage 2-1 V S1 4 to 13 V Recommended operation voltage 2-2 V S2 4 to 13 V *VCC ≥ VS1, 2 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co., Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN N1798RM(KI) No. 5717-1/7 LA6542M Electrical Characteristics at VCC = 12V, VS = 5V, Ta = 25°C Parameter VCC no-load current drain Ratings Conditions Symbol min ICC1 All outputs ON (MUTE1, MUTE2: High) ICC2 All outputs OFF (MUTE1, MUTE2: Low) VS1 no-load current drain IS1-1 CH1, 2 ON (MUTE1, MUTE2: High) IS1-2 CH1, 2 OFF (MUTE1, MUTE2: Low) VS2 no-load current drain IS2-1 CH3, 4 ON (MUTE1, MUTE2: High) IS2-2 CH3, 4 OFF (MUTE1, MUTE2: Low) Input voltage range Output voltage (source) 5 Unit max 10 20 mA 5 10 mA 10 30 mA 4 mA 10 30 mA 4 mA Potential difference between plus and minus outputs for CH1 to CH4 –50 50 mV VIN Input voltage range for VIN1 to VIN4 0.5 5 V Vsource Plus and minus outputs at high level 4.4 VOF1 to 4 Output offset voltage typ 4.7 V IO = 700 mA (sink) Vsink Plus and minus outputs at low level 0.3 0.6 V IO = 700 mA Closed circuit voltage gain VG Voltage gain between BTL amplifiers Slew rate SR (Note 1) 0.5 6 dB V/µs Mute ON voltage VMUTE MUTE1, MUTE2 voltage when output is ON (Note 2) 1.5 2 V Mute ON current IMUTE MUTE1, MUTE2 current when output is ON (Note 2) 6 10 µA Allowable power dissipation, Pd max – W Note 1: Guaranteed design value Note 2: MUTE works on all channels. At High, amplifier output is ON and at Low amplifier output is OFF (output impedance becomes HI). Pd max – Ta 1.2 1.0 IC only 0.9 0.8 0.6 0.54 0.4 0.2 0 –20 0 20 40 60 80 100 Ambient temperature, Ta – ˚C No. 5717-2/7 LA6542M Pin Assignment RF 1 36 RF RF 2 35 RF VOUT 3 34 VSS VIN– 4 33 VSS OUT VIN+ 5 32 VO1 MUTE1 6 31 VO2 VIN1 7 30 VS1 VG1 8 29 VO3 VIN2 9 28 VO4 VG2 10 27 VO5 VIN3 11 26 VO6 VG3 12 25 VS2 VIN4 13 24 VO7 VG4 14 23 VO8 MUTE2 15 22 VREF OUT VCC 16 21 VREF IN RF 17 20 RF RF 18 19 RF LA6542M Top view A11265 No. 5717-3/7 LA6542M Pin Function Pin number Pin name Equivalent circuit Pin function 1, 2 17, 18 19, 20 Substrate RF 16 VCC (minimum potential) 35, 36 V IN1, V IN2 V IN3, V IN4 8, 10 VG1, VG2 12, 14 VG3, VG4 16 22 V CC V REFOUT Input pins for CH1 and CH2 9 Drive 7, 9 11, 13 VIN 11 7 Input pins for CH3 and CH4 Input pins for CH1 and CH2 (for gain adjustment) 13 10 Input pins for CH3 and CH4 (for gain adjustment) VG 12 8 Power supply GND 1 A 14 2 17 18 19 22 VREF OUT 20 35 36 Level shift circuit reference voltage (V REF1 buffer amplifier output*) A11136 3 V OUT 4 V IN- OP amp output OP amp inverted input 5 V IN+ OP amp non-inverted input 6 MUTE1 15 MUTE2 CH1, CH2 output ON/OFF VCC 16 CH3, CH4 output ON/OFF MUTE1, 2 15 6 To bias circuit GND 1 2 17 18 19 20 35 36 A11138 21 V REFIN 23 V O8 CH4 inverted output (AMP8 output) 24 V O7 CH4 non-inverted output (AMP7 output) 26 V O6 27 V O5 28 V O4 29 V O3 31 V O2 32 V O1 Level shift circuit reference voltage input (V REF buffer amplifier input*) CH3 inverted output (AMP6 output) 16 VCC VO 31 26 23 CH2 inverted output (AMP4 output) CH2 non-inverted output (AMP3 output) Drive 29 24 CH3 non-inverted output (AMP5 output) CH1 inverted output (AMP2 output) 32 27 CH1 non-inverted output (AMP1 output) 28 GND 1 2 17 18 19 20 35 36 A11137 25 VS2 30 VS1 33 V SS -OUT 34 V SS CH3 (AMP5, AMP6), CH4 (AMP7, AMP8) output stage power supply CH1 (AMP1, AMP2), CH2 (AMP3, AMP4) output stage power supply Output stage reference voltage (V SS 1/2: typ) (V REF2 buffer amplifier output*) Connect to VS1, VS2 (resistance split) to generate V SSOUT *See block diagram on next page. No. 5717-4/7 LA6542M Block Diagram RF 1 RF 2 VOUT 3 Thermal shutdown MUTE1 MUTE2 VREF2 – 36 RF 35 RF 34 VSS 33 VSS OUT 32 V O1 31 V O2 30 V S1 29 V O3 28 V O4 27 V O5 26 V O6 25 V S2 24 V O7 23 V O8 22 VREF OUT 21 VREF IN + VIN– 4 VIN+ 5 MUTE1 6 VIN1 7 VG1 8 VIN2 9 VG2 10 VIN3 11 VG3 12 VIN4 13 VG4 14 MUTE2 15 – + – + VO1 to VO4 – Level shift + – + Level shift – + – + Level shift – + Level shift – + – + VO5 to VO8 – VCC 16 + VREF1 RF 17 20 RF RF 18 19 RF A11139 System Diagram (relationship between power supply and MUTE) CH1 MUTE1 VS1 CH2 CH3 MUTE2 VS2 CH4 A11140 No. 5717-5/7 LA6542M Sample Application Circuit 1 RF RF 36 2 RF RF 35 3 VOUT 4 VIN– VSS OUT 33 5 VIN+ VO1 32 Microprocessor 6 MUTE1 VO2 31 Focus input 7 VIN1 VS1 30 8 VG1 VO3 29 9 VIN2 VO4 28 10 VG2 VO5 27 11 VIN3 VO6 26 12 VG3 VS2 25 13 VIN4 VO7 24 14 VG4 VO8 23 Microprocessor 15 MUTE2 12V power supply 16 VCC 17 RF RF 20 18 RF RF 19 5V power supply VSS 34 Focus Tracking Tracking input LA6542M M Sled Sled input Spindle input M Spindle VREF OUT 22 VREF IN 21 Reference voltage A11141 No. 5717-6/7 LA6542M Gain Setting (input pins and adjustment pins) A simplified diagram of VIN and VG is shown below. 1) Consider an 11 kΩ (typ.) resistor inserted between VIN and VG. 2) When not the pin VG but the pin VIN is used alone, the BTL gain (between VO+ and VO– ) is set to 6 dB (0 dB for AMP only). This also applies for the case when VIN is not used and an 11 kΩ external resistor is connected to VG for input. 3) Gain is set by the input impedance as seen from point A. When VG only is used and the external resistor is R, the BTL gain (between VO+ and VO–) is 20 log (11 kΩ/R) + 6 dB. When an 11 kΩ resistor is inserted between VIN and VG, and input is via VIN, the combined resistance Rz as seen from point A is Rz = 5.5 kΩ. Gain is 20 log (11 kΩ /5.5 kΩ) + 6 dB = 12 dB. VG 11 kΩ VIN Level shift – VREF1 + VREF VSS 11 kΩ – AMP1 + VO+ – AMP2 + V O– A – VREF2 + 11 kΩ A11142 GND Offset Voltage This IC incorporates a level shifter circuit. The input references the VREF to be applied, and references the voltage (VSS – VBE (0.7))/2V to be output. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1998. Specifications and information herein are subject to change without notice. PS No. 5717-7/7