Ordering number : EN5833
CMOS IC
LC74798, 74798M
On-Screen Display Controller IC
Overview
Package Dimensions
The LC74798 and LC74798M are on-screen display
controller CMOS ICs that display characters and patterns
on the TV screen under microprocessor control. These ICs
include a built-in PDC/VPS/UDT interface circuit.
unit: mm
3193-DIP30SD
[LC74798]
Features
• Display format: 24 characters by 12 rows (Up to 288
characters)
• Character format: 12 (horizontal) × 18 (vertical) dots
• Character sizes: Three sizes each in the horizontal and
vertical directions
• Characters in font: 128
• Initial display positions: 64 horizontal positions and
64 vertical positions
• Blinking: Specifiable in character units
• Blinking types: Two periods supported: 1.0 second and
0.5 second
• Blanking: Over the whole font (12 × 18 dots)
• Background color
— 8 colors (internal synchronization mode): 4fSC
— 6 colors (internal synchronization mode): 2fSC
— Blue background only: NTSC
• Line background color
— Three lines can be set up.
— 8 line background colors (in internal synchronization
mode): 4fSC
— 6 line background colors (in internal synchronization
mode): 2fSC
• External control input: 8-bit serial input format
• On-chip sync separator and AFC circuits
• On-chip PDC/VPS/UDT interface circuit
• Video outputs: PAL and NTSC format composite video
outputs
• Package: DIP30SD (400 mil)
MFP30S (375 mil)
SANYO: DIP30SD
unit: mm
3216-MFP30S
[LC74798M]
SANYO: MFP30S
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
51898RM (OT) No. 5833-1/32
LC74798, 74798M
Pin Assignment
No. 5833-2/32
LC74798, 74798M
Pin Descriptions
Pin No.
Pin name
1
VSS1
2
XtalIN
Function
Ground
Crystal oscillator
3
4
XtalOUT
(MUTE input)
(MUTE)
CTRL1
(CHABLK)
Crystal oscillator input switching
(CHABLK output)
Notes
Ground connection (digital system ground)
These pins are used either to connect the crystal and capacitors used to form an external
crystal oscillator circuit to generate the internal synchronizing signals, or to input an
external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to
function as the MUTE input pin. When this pin is set low, the video output is held at the
pedestal level. (A pull-up resistor is built in and the input has hysteresis characteristics.)
Switches the mode between external clock input and crystal oscillator operation. A low
level selects crystal oscillator operation and a high level selects external clock input. As a
mask option, the CTRL1 input pin can be set to function as the CHABLK (character ·
frame) output. This is a 3-value output.
Enable input 2
Enable input for the PDC/VPS data output. Data output is enabled when this input is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
SCLK2
Clock input 2
Clock input for the PDC/VPS data output.
A pull-up resistor is built in and the input has hysteresis characteristics.
7
DOUT
Data output
PDC/VPS data output.
(This can be either an n-channel open-drain output or a CMOS output.)
8
SYNCJDG
9
CS1
10
5
CS2
6
Outputs the state of the external synchronizing signal presence/absence judgment.
External synchronizing signal judgment Outputs a high level when synchronizing signals are present.
output
Outputs the crystal oscillator clock when CS1 and RST are low.
(This signal is not output on command resets.)
Enable input 1
Enable input for the OSD serial data input.
Serial data input is enabled when this pin is low.
A pull-up resistor is built in and the input has hysteresis characteristics.
SCLK1
Clock input 1
Serial data input enable pin.
A pull-up resistor is built in and the input has hysteresis characteristics.
11
SIN1
Data input 1
Serial data input. A pull-up resistor is built in and the input has hysteresis characteristics.
12
VDD2
Power supply
Composite video signal level adjustment power supply (analog system power supply)
13
CPOUT
Charge pump output
Charge pump output. Connect a low-pass filter to this pin.
14
VCOIN
Oscillator control voltage input
VCO oscillator control voltage input. (For data slicing)
15
VSS3
Ground
Ground (VCO ground)
16
VCOR
Oscillator range adjustment
VCO oscillator range adjustment resistor connection
17
VCOIN2
Oscillator control voltage input 2
VCO oscillator control voltage input. For character display.
18
VDD3
Power supply (+5 V)
Power supply (+5 V: VCO power supply)
19
CVOUT
Video signal output
Composite video signal output
20
VSS2
Ground
Ground (analog system ground)
21
CVIN
Video signal input
Composite video signal input
22
CVCR
Video signal input
SECAM chrominance signal input
23
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
24
SYNIN
Sync separator circuit input
Video signal input to the internal sync separator circuit
25
SEPC
Sync separator circuit adjustment
Internal sync separator circuit adjustment
26
SEPOUT
Composite synchronizing signal output
Internal sync separator circuit composite synchronizing signal output. Can be switched to
function as a signal (high, low, or ST. pulse) output by the MOD0 setting when SEL0 is
high.
Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output
signal.
An integration circuit must be connected between this pin and the SEPOUT pin. This pin
must be tied to VDD1 if unused. This pin is valid when CTL3 is set high.
27
SEPIN
Vertical synchronizing signal input
28
CDLR
Background color phase adjustment
Background color phase adjustment resistor connection
29
RST
Reset input
System reset input.
A pull-up resistor is built in and the input has hysteresis characteristics.
30
VDD1
Power supply (+5 V)
Power supply (+5 V: digital system power supply)
Note *: A capacitor of at least 2000 pF must be connected between the VDD1 power supply and VSS1.
No. 5833-3/32
LC74798, 74798M
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
VDD max
Maximum supply voltage
Maximum input voltage
VIN
Maximum output voltage
VOUT
Allowable power dissipation
Pd max
Ratings
Unit
VDD1 and VDD2
VSS – 0.3 to VSS + 7.0
V
All input pins
VSS – 0.3 to VDD + 0.3
V
DOUT, SEPOUT, SYNCJDG
VSS – 0.3 to VDD + 0.3
Ta = 25°C
V
350
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
VDD1
VDD1 and VDD2
4.5
5.0
5.5
V
VDD2
VDD2
4.5
5.0
1.27 VDD1
V
VIH1
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
0.8 VDD1
VDD1 + 0.3
V
VIH2
CTRL1
0.7 VDD1
VDD1 + 0.3
V
VIL1
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
VSS – 0.3
0.2 VDD1
V
VIL2
CTRL1
VSS – 0.3
0.3 VDD1
V
Pull-up resistance
RPU
RST, CS1, CS2, SIN1, SCLK1, SCLK2, MUTE
Applies to pins set up by options.
Composite video signal input
VIN1
CVIN and CVCR: VDD1 = 5 V
voltage
VIN2
SYNIN : VDD1 = 5 V
Input voltage
VIN3
XtalIN (when used for external clock input)
fIN = 2fsc or 4fsc: VDD1 = 5 V
Supply voltage
Input high-level voltage
Input low-level voltage
Oscillator frequencies
FOSC1
25
50
1.5
2.0
90
kΩ
2.5
Vp-p
5.0
Vp-p
2.0
Vp-p
0.10
XtalIN and XtalOUT oscillator pins (2fsc : PAL)
8.867
MHz
XtalIN and XtalOUT oscillator pins (4fsc : PAL)
17.734
MHz
Note: Applications must be especially cautious about noise when using the XtalIN input pin in clock input mode.
Electrical Characteristics at Ta = –30 to +70°C, VDD1 = 5 V unless otherwise specified.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Input off leakage current
Ileak1
CVIN and CVCR
1
µA
Output off leakage current
Ileak2
CVOUT
1
µA
Output high-level voltage
VOH1
DOUT, SEPOUT, CPOUT, and SYNCJDG
VDD1 = 4.5 V, IOH = –1.0 mA
Output low-level voltage
VOL1
DOUT, SEPOUT, CPOUT, and SYNCJDG
VDD1 = 4.5 V, IOL = –1.0 mA
Three-value output voltage
VO
SYNC level
Pedestal level
Color burst low level
Color burst high level
VDD2 : VDD2 = 5 V
VSN
VPD
VCBL
VCBH
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
V
5.0
1.8
2.3
V
L
0
0.8
V
1
µA
CTRL1, SEPIN, VCOIN, and VCOIN2, VIN = VSS1
IDD2
V
3.3
IIL
VDD1: With all outputs open
Xtal : 17.734 MHz, VCO : 27 MHz
1.0
M
RST, CS1, CS2, SIN, SCLK1, SCLK2, CTRL1, MUTE,
SEPIN, VCOIN, and VCOIN2, VIN = VDD1
IDD1
V
H
IIH
Input current
Operating mode current drain
CHABLK: VDD1 = 5.0 V
3.5
–1
µA
40
mA
20
mA
(1)
0.80
V
(2)
1.00
V
(3)
1.40
V
(1)
1.37
V
(2)
1.57
V
(3)
1.97
V
(1)
1.07
V
(2)
1.27
V
(3)
1.67
V
(1)
1.67
V
(2)
1.87
V
(3)
2.27
V
Continued on next page.
No. 5833-4/32
LC74798, 74798M
Continued from preceding page.
Parameter
Background color low level
Background color high level
Frame level 0
Frame level 1
Character level
Symbol
VRSL
VRSH
VBK0
VBK1
VCHA
Conditions
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
CVOUT : VDD1 = 5.0 V,
VDD2 = 5.0 V
Ratings
min
typ
max
Unit
(1)
1.23 (1.16)
V
(2)
1.43 (1.36)
V
(3)
1.83 (1.76)
V
(1)
2.37 (2.01)
V
(2)
2.57 (2.21)
V
(3)
2.97 (2.61)
V
(1)
1.50
V
(2)
1.70
V
(3)
2.10
V
(1)
2.08
V
(2)
2.28
V
(3)
2.68
V
(1)
2.65
V
(2)
2.85
V
(3)
3.25
V
Notes: (1): When the sync level = 0.8 V
(2): When the sync level = 1.0 V
(3): When the sync level = 1.4 V
The values in parentheses for the background high and low levels are for blue background mode.
Timing Characteristics at Ta = –30 to +70°C, VDD1 = 5 ±0.5 V
Parameter
Symbol
Conditions
Ratings
min
typ
max
Unit
OSD write (See figure 1.)
Minimum input pulse width
Data setup time
Data hold time
One word write time
tW (SCLK)
SCLK1
tW (CS1)
CS1 (The period when CS1 is high)
tSU (CS1)
tSU (SIN)
200
ns
1
µs
CS1
200
ns
SIN1
200
ns
th (CS1)
CS1
2
µs
th (SIN)
SIN1
200
ns
tword
The 8-bit data write time
4.2
µs
twt
The RAM data write time
1
µs
PDC/VPS write (For the n-channel open-drain output circuit type. See figure 2)
tCKCY
SCLK2
2
µs
tCKL
SCLK2
1
µs
tCKH
SCLK2
1
µs
Setup time
tICK
SCLK2
10
µs
Output delay time
tCKO
DOUT
Minimum input pulse width
0.5
µs
Note: The OSD timing applies when the CMOS output circuit type is used.
No. 5833-5/32
LC74798, 74798M
Figure 1 OSD Serial Data Input Timing
<Test Load>
Note: DOUT goes to the high-impedance state while CS2 is high.
Figure 2 PDC/VPS Serial Output Test Conditions (For the n-channel open-drain output circuit type.)
No. 5833-6/32
Pedestal clamp
Data peak hold
circuit
(data slicing)
AFC circuit
data slicing
Data output
buffer
AFC circuit
for character
display
HSYNC peak hold
(HSYNC slicing)
Data slicer
Output control
Composite
sync signal
separation
control
Sync
discrimination
8-bit
latch
+
command
decoder
Horizontal
size
counter
Horizontal
character
size
register
Timing generator
Vertical
size
counter
Vertical
character
size
Line
control
counter
Character
control
counter
Sync signal
generator
Vertical
display
position
Vertical
dot
counter
Vertical
display
position
Horizontal
display
position
Horizontal
dot
counter
Horizontal
display
position
Display
control
register
Character output
control
Background control
Video output control
Blinking and
reverse
video control
Blinking and
reverse
video control
RAM write
address
counter
Decoder
Serial
↓
parallel
converter
Shift register
Font ROM
Decoder
Display RAM
LC74798, 74798M
System Block Diagram
No. 5833-7/32
LC74798, 74798M
Display Control Commands
Display control commands have an 8-bit format and are transferred using the serial input function. Commands consist of
a command identification code in the first byte and command data in the following bytes. The following commands are
supported.
1 COMMAND0: Display memory (VRAM) write address setup command
2 COMMAND1: Display character data write command
3 COMMAND2: Vertical display start position and vertical character size setup command
4 COMMAND3: Horizontal display start position and horizontal character size setup command
5 COMMAND4: Display control setup command
6 COMMAND5: Display control setup command
7 COMMAND6: Synchronizing signal detection setup command
8 COMMAND7 to COMMAND12: Display control setup commands
9 COMMAND13 to COMMAND17: VPS/PDC control commands
Display Control Command Table
First byte
Command
COMMAND0
Second byte
Command identification code
Data
Data
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
V3
V2
V1
V0
0
0
0
H4
H3
H2
H1
H0
1
0
0
1
0
0
0
0
at
c6
c5
c4
c3
c2
c1
c0
1
0
1
0
VS
VS
VS
VS
0
FS
VP
VP
VP
VP
VP
VP
21
20
11
10
5
4
3
2
1
0
HS
HS
HS
HP
HP
HP
HP
HP
(Write address setup)
COMMAND1
(Character write)
COMMAND2 (Vertical character size
and vertical display start position)
COMMAND3 (Horizontal character size
1
0
1
1
HS
21
20
11
10
1
1
0
0
TST
RAM
OSC
SYS
MOD
ERS
STP
RST
1
1
0
1
NP1
NP0
NON
INT
and horizontal display start position)
COMMAND4
(Display control)
COMMAND5
0
0
HP
5
4
3
2
1
0
0
BLK
BLK
BLK
BK
BK
RV
DSP
2
1
0
1
0
0
RSH
HLF
BCL
CB
PH
PH
LV2
INT
2
1
0
RN
SN
SN
SN
(Display control)
COMMAND6
1
1
1
0
SEL
1
1
1
1
1
1
1
1
0
(Synchronizing signal detection)
COMMAND7
MOD
DIS
0
0
LIN
0
0
COMMAND8
0
0
RN
2
1
0
3
2
1
0
0
0
0
CIN
CIN
VNP
VSP
MSK
MSK
EGL
SEL
CTL
SEL
SEL
ERS
SEL
0
1
0
LNA
LNA
LNA
LNA
LPA
LPA
3
2
1
0
2
1
0
LNB
LNB
LNB
LPB
LPB
LPB
(Display control)
COMMAND9
1
1
1
0
0
1
0
0
LNB
3
2
1
0
2
1
0
1
1
1
1
0
0
1
1
0
LNC
LNC
LNC
LNC
LPC
LPC
LPC
3
2
1
0
2
1
0
1
1
1
1
0
1
0
0
0
0
VSP
VSP
LNC
MOD
LNB
MOD
DCK
SLC
SEL
3
SEL
2
1
1
1
1
0
1
0
1
0
VIN
VIN
SEL
HLF
SEL
SEL
CTL
NP
2
22
TON
2
1
3
1
1
1
1
0
1
1
0
0
CPA
CPA
0
VPM
VPM
VPM
VPM
1
0
3
2
1
0
1
1
1
1
0
1
1
1
0
VMW VMW HBS
HBS
BMS
EMS
DCE
1
1
1
1
1
0
0
0
0
ECV
(Display control)
COMMAND11
(Display control)
COMMAND12
(Display control)
COMMAND13
(VPS/PDC control)
COMMAND14
(VPS/PDC control)
COMMAND15
SE2
SEL
2
1
0
ECV
ECV
ECV
ECV
ECV
15
14
13
12
11
5
ECP
ECP
ECP
ECP
ECP
ECP
(VPS/PDC control)
COMMAND16
1
1
1
1
1
0
0
1
0
1
1
1
1
1
0
1
0
0
(VPS/PDC control)
COMMAND17
(VPS/PDC control)
LPA
1
(Display control)
COMMAND10
SN
PH
MUT
(Display control)
RN
ON
ECP
19
18
17
16
15
14
13
0
ECP
ECP
ECP
ECP
ECP
ECP
25
24
23
22
21
20
Once written, a first byte command identification code is stored until the next first byte is written. However, when the display character data write command
(COMMAND1) is written, the LC74798/M locks into the display character data write mode, and another first byte cannot be written.
When the CS pin is set high, the LC74798/M is set to the COMMAND0 (display memory write address setup mode) state.
No. 5833-8/32
LC74798, 74798M
COMMAND0 (Display memory write address setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
0
5
—
0
4
—
0
3
V3
2
V2
1
V1
0
V0
Function
Notes
Command 0 identification code.
Sets the display memory write address.
0
1
0
1
Display memory line address (0 to B hexadecimal)
0
1
0
1
• Second byte
DA
0 to 7
Register
Contents
State
7
—
0
6
—
0
5
—
0
4
H4
3
H3
2
H2
1
H1
0
H0
Function
Notes
Second byte identification bit
0
1
0
1
0
Display memory column address (0 to 17 hexadecimal)
1
0
1
0
1
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
COMMAND1 (Display character data write setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
0
5
—
0
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
Function
Command 1 identification code.
Sets up display character data write mode.
Notes
When this command is input, the LC74798/M locks
in the display character data write mode until the
CS pin goes high
No. 5833-9/32
LC74798, 74798M
• Second byte
DA
0 to 7
7
Register
at
6
c6
5
c5
4
c4
3
c3
2
c2
1
c1
0
c0
Contents
State
Notes
Function
0
Character attribute off
1
Character attribute on
0
1
0
1
0
1
0
Character code (00 to 7F hexadecimal)
1
0
1
0
1
0
1
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
COMMAND2 (Vertical display start position and vertical character size setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
0
5
—
1
4
—
0
3
VS21
2
VS20
1
VS11
0
VS10
Command 2 identification code.
Sets the vertical display start position and the vertical character size.
0
1
VS20
0
1
0
1H/dot
2H/dot
1
3H/dot
1H/dot
VS21
0
1
0
1
Notes
Function
VS10
0
1
0
1H/dot
2H/dot
1
3H/dot
1H/dot
VS11
0
1
Second line vertical character size
First line vertical character size
• Second byte
DA
0 to 7
7
6
5
Register
—
FS
Function
0
Second byte identification bit
0
Crystal oscillator frequency: 2fsc
1
VP5
0
Crystal oscillator frequency: 4fsc
If VS is the vertical display start position then:
(MSB)
1
VS = H × 2 ∑ 2n VPn
0
H: the horizontal synchronization pulse period
4
VP4
3
VP3
2
VP2
1
VP1
0
Contents
State
(
5
n=0
Notes
)
1
0
The vertical display start position is set by the 6
bits VP0 to VP5.
The weight of bit 1 is 2H.
1
0
1
0
1
VP0
0
(LSB)
1
Character
display area
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-10/32
LC74798, 74798M
COMMAND3 (Horizontal display start position and horizontal size setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
0
5
—
1
4
—
0
3
HS21
2
HS20
1
HS11
0
HS10
Command 3 identification code.
Sets the horizontal display start position and the horizontal character
size.
0
1
HS20
0
1
0
1Tc/dot
2Tc/dot
1
3Tc/dot
1Tc/dot
HS21
0
1
0
1
Notes
Function
HS10
0
1
0
1Tc/dot
2Tc/dot
1
3Tc/dot
1Tc/dot
HS11
0
1
Second line horizontal character size
First line horizontal character size
• Second byte
DA
0 to 7
Register
Contents
State
7
—
0
6
—
0
5
HP5
0
(MSB)
1
4
HP4
3
HP3
2
HP2
1
HP1
0
Function
Notes
Second byte identification bit
0
1
0
1
0
1
If HS is the horizontal start position then:
(
5
HS = Tc × 2 ∑ 2n VPn
n=0
)
The horizontal display start position is set by the 6
bits HP0 to HP5.
The weight of bit 1 is 2Tc.
Tc: Period of the oscillator in operating mode.
0
1
HP0
0
(LSB)
1
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-11/32
LC74798, 74798M
COMMAND4 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
0
3
TSTMOD
2
RAMERS
1
OSCSTP
0
SYSRST
Notes
Function
Command 4 identification code.
Display character data write setup.
0
Normal operating mode
1
Test mode
This bit must be set to 0
0
Erasing RAM takes about 500 µs. (This operation
must be executed in the DSPOFF state.)
1
Erase display RAM. (The RAM data is set to 7F hexadecimal.)
0
Do not stop the crystal and VCO oscillators
1
Stop the crystal and VCO oscillators
Valid in external synchronization mode when
character display is off. It will no longer be possible
to detect VPS/PDC data
Reset all registers and turn display off
The registers are reset when the CS pin is low, and
the reset state is cleared when CS is set high
0
1
• Second byte
DA
0 to 7
7
Register
—
6
BLK2
5
BLK1
4
BLK0
3
BK1
2
BK0
1
RV
0
DSPON
Contents
State
0
Second byte identification bit
0
Character display area
1
Video display area
0
1
Notes
Function
BLK0
0
1
0
Blanking off
Character size
1
Frame size
Complete fill in size
BLK1
0
1
Specifies the size for complete fill in
0
Blinking period: About 0.5 s
1
Blinking period: About 1.0 s
0
Blinking off
1
Blinking on
0
Reverse video off
1
Reverse video on
0
Character display off
1
Character display on
Changes the blanking size
Switches the blinking period
Blinking in reverse video mode switches the display between
normal character display and reverse video display
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-12/32
LC74798, 74798M
COMMAND5 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
0
4
—
1
3
NP1
2
NP0
1
NON
0
INT
Notes
Function
Command 5 identification code.
Display control setup.
0
NTSC
1
PAL
0
525 lines
1
625 lines
0
Interlaced
1
Noninterlaced
0
External synchronization
1
Internal synchronization
Switches between NTSC and PAL
Modified by the external input signal V
Switches between interlaced and noninterlaced
video
Switches between external and internal
synchronization
• Second byte
DA
0 to 7
7
Register
—
6
RSHLV2
5
HLFINT
4
BCL
3
CB
2
PH2
Contents
State
0
Second byte identification bit
0
Background color level 1 (level that is different from blue)
1
Background color level 2 (level that is identical to the blue level)
0
Normal mode
1
Partial internal synchronization mode
0
Background color on
1
No background color (Only the background level is set)
0
Color burst signal output
1
Color burst signal output stopped
0
1
0
1
PH1
1
0
0
Notes
Function
PH0
Switches the background color signal level
Only valid in internal synchronization mode
Only valid when BCL is high
PH2
PH1
PH0
0
0
0
Background color (phase)
Cyan*
0
0
1
Yellow*
0
1
0
Red*
0
1
1
Blue*
1
0
0
Cyan blue
1
0
1
Green*
1
1
0
Orange
1
1
1
1
Background color specification
Magenta*
*: When 2fsc is used.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-13/32
LC74798, 74798M
COMMAND6 (Synchronizing signal detection setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
0
3
SEL0
2
MOD0
1
DISLIN
0
MUT
Notes
Function
Command 6 identification code.
Sets up synchronizing signal control.
0
MOD0
0
1
0
DAV
Sliced data width
1
CSYNC
ST.PULSE
SEL0
1
0
1
0
12 lines
1
10 lines
0
Normal output
1
CVIN is cut and CVOUT is held at the pedestal level
Switches the SEPOUT (pin 26) output
Switches the number of lines displayed
CVOUT switching
• Second byte
DA
0 to 7
7
6
5
Register
—
RN2
RN1
4
RN0
3
SN3
2
SN2
1
SN1
0
SN0
Contents
State
0
0
Notes
Function
Second byte identification bit
RN2
RN1
RN0
Number of times HSYNC detected
0
0
0
32 times
0
0
1
4 times
0
1
0
8 times
1
0
0
16 times
1
SN3
SN2
SN1
SN0
Number of times HSYNC detected
0
0
0
0
0
Not detected
1
0
0
0
1
32 times
0
0
0
1
0
64 times
1
0
1
0
0
128 times
0
1
0
0
0
256 times
1
0
1
0
1
External synchronizing signal detection control.
Signal absent → signal present transition
detection.
Sets the sampling period in which SYNC can be
detected continuously in the horizontal
synchronizing signal period (1H).
0
External synchronizing signal detection control.
Signal present → signal absent transition
detection.
Sets the sampling period in which SYNC cannot be
detected continuously in the horizontal
synchronizing signal period (1H).
1
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-14/32
LC74798, 74798M
COMMAND7 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
—
0
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 0 identification code
• Second byte
DA
0 to 7
7
Register
—
6
CINSEL
5
CINCTL
4
VNPSEL
3
VSPSEL
2
MSKERS
1
MSKSEL
0
EGL
Contents
State
Notes
Function
0
Second byte identification bit
0
Blank area (the logical OR of the character and frame signals)
1
Video signal display area
0
CVCR: off
1
CVCR: on
0
V falling edge detection
1
V rising edge detection
0
VSEP: about 8.9 µs (for NTSC)
1
VSEP: about 17.8 µs (for NTSC)
0
Mask valid
1
Mask invalid
0
3H (NTSC)
1
20H (NTSC)
0
Frame level 0 only (VBK0)
1
Two-stage frame level (VBK0 and VBK1)
CVCR on signal switching
CVCR on/off switching
Switches the V acquisition polarity in external
mode when internal V separation is used
Switches the internal V separation period
Clears the HSYNC and VSYNK masks
Switches the VSYNC mask
Switches the frame level.
(Only valid when BLK0 is 0 and BLK1 is 1.)
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-15/32
LC74798, 74798M
COMMAND8 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
0
0
—
1
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 1 identification code
• Second byte
DA
0 to 7
Register
7
—
6
LNA3
Contents
State
0
0
1
0
5
LNA2
1
0
4
LNA1
1
0
3
LNA0
1
0
2
LPA2
1
0
1
LPA1
1
0
0
LNA0
Notes
Function
Second byte identification bit
LNA3 LNA2 LNA1 LNA0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
LPA2
LPA1
LPA0
0
0
0
Cyan*
0
0
1
Yellow*
0
1
0
Red*
0
1
1
Blue*
1
0
0
Cyan blue
1
0
1
Green*
1
1
0
Orange
1
1
1
Specifies the line whose background is to be
changed.
(This specification is illegal for the same line as
LNA*, LNB*, and LNC*)
Background color (phase)
1
Specifies the background color
Magenta*
*: When 2fsc is used.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-16/32
LC74798, 74798M
COMMAND9 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
1
0
—
0
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 2 identification code
• Second byte
DA
0 to 7
Register
7
—
6
LNB3
Contents
State
0
0
1
0
5
LNB2
1
0
4
LNB1
1
0
3
LNB0
1
0
2
LPB2
1
0
1
LPB1
1
0
0
LNB0
Notes
Function
Second byte identification bit
LNB3 LNB2 LNB1 LNB0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
LPB2
LPB1
LPB0
0
0
0
Cyan*
0
0
1
Yellow*
0
1
0
Red*
0
1
1
Blue*
1
0
0
Cyan blue
1
0
1
Green*
1
1
0
Orange
1
1
1
Specifies the line whose background is to be
changed.
(This specification is illegal for the same line as
LNA*, LNB*, and LNC*)
Background color (phase)
1
Specifies the background color
Magenta*
*: When 2fsc is used.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-17/32
LC74798, 74798M
COMMAND10 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
0
1
—
1
0
—
1
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 3 identification code
• Second byte
DA
0 to 7
Register
7
—
6
LNC3
Contents
State
0
0
1
0
5
LNC2
1
0
4
LNC1
1
0
3
LNC0
1
0
2
LPC2
1
0
1
LPC1
1
0
0
LNC0
Notes
Function
Second byte identification bit
LNC3 LNC2 LNC1 LNC0
Specified line
0
0
0
0
Do not change the line background
0
0
0
1
Line 1
0
0
1
0
Line 2
0
0
1
1
Line 3
0
1
0
0
Line 4
0
1
0
1
Line 5
0
1
1
0
Line 6
0
1
1
1
Line 7
1
0
0
0
Line 8
1
0
0
1
Line 9
1
0
1
0
Line 10
1
0
1
1
Line 11
1
1
—
—
Line 12
LPC2
LPC1
LPC0
0
0
0
Cyan*
0
0
1
Yellow*
0
1
0
Red*
0
1
1
Blue*
1
0
0
Cyan blue
1
0
1
Green*
1
1
0
Orange
1
1
1
Specifies the line whose background is to be
changed.
(This specification is illegal for the same line as
LNA*, LNB*, and LNC*)
Background color (phase)
1
Specifies the background color
Magenta*
*: When 2fsc is used.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-18/32
LC74798, 74798M
COMMAND11 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
0
0
—
0
Function
Notes
Command 7 identification code.
Display control setup.
Extended command 4 identification code
• Second byte
DA
0 to 7
Register
Contents
State
7
—
0
6
—
0
5
VSPDCK
4
VSPSLC
3
LNCSEL
2
MOD3
1
LNBSEL
0
MOD2
Function
Notes
Second byte identification bit
0
Character display VCO operating
1
Character display VCO stopped
0
Data slice VCO operating
1
Data slice VCO stopped
0
Normal line background color operation
1
RV characters have the background color specified by PH* and the RV
character background color is white
Character display VCO control
Data slice VCO control
Switches the RV mode background color for the
line specified by LNB* for characters specified for
RV display
0
The LNCSEL = 1 setting specifications
Valid when LNCSEL is high
1
RV characters have the background color specified by PH* and
characters are white
0
Normal line background color operation
1
RV characters have the background color specified by PH* and the RV
character background color is white.
Switches the RV mode background color for the
line specified by LNB* for characters specified for
RV display
0
The LNBSEL = 1 setting specifications
1
RV characters have the background color specified by PH* and
characters are white
Valid when LNBSEL is high
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-19/32
LC74798, 74798M
COMMAND12 (Display control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
0
0
—
1
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 5 identification code
• Second byte
DA
0 to 7
7
Register
—
6
VINNP
5
VIN2
4
SEL22
Contents
State
Notes
Function
0
Second byte identification bit
0
Negative CSYNC input polarity
1
Positive CSYNC input polarity
0
Normal input
1
CSYNC input to the SEPIN pin
CSYNC input polarity selection
SEPIN pin input switching
0
1
0
3
HLFTON
1
0
2
SEL2
SEL22
SEL2
HLFTOM
Output
0
0
0
SYNCJDG
0
0
1
Halftone
0
1
0
O/E
0
1
1
LOCK
1
0
0
SYNDET2
1
0
1
SENDET
1
1
0
LOCK2
SYNCJDG pin (pin 8) output switching.
The halftone output line specification depends on
background color specification (the logical or of the
3-line specification)
SYNCDET2: Used for character display
LOCK2: Used for character display
1
1
SEL1
0
CTL3
0
Vertical synchronization signal input (external synchronization)
1
Frame signal input
0
Internal V separation used
1
Internal V separation not used (external V separation)
SEPIN (pin 27) input switching.
Only valid when CTL3 is high.
V separation switching
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-20/32
LC74798, 74798M
COMMAND13 (VPS/PDC control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
1
0
—
0
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 6 identification code
• Second byte
DA
0 to 7
Register
7
—
6
CPA1
Contents
State
0
Notes
Function
Second byte identification bit
0
CPA1
CPA0
Clock
0
0
No.4
0
1
No.3
1
0
No.2
1
1
No.1
1
0
5
CPA0
Data acquisition clock switching
1
4
—
3
VPM3
0
0
1
0
2
VPM2
1
0
1
VPM1
1
0
0
VPM0
1
VPM3 VPM2 VPM1 VPM0
Operating mode
0
0
0
0
VPS
0
0
0
1
8/30/2 (PDC)
0
0
1
0
Automatic PDC/VPS switching
0
0
1
1
8/30/1 (UDT)
0
1
0
0
Header time 1
0
1
0
1
Header time 2
0
1
1
0
Header time 3
0
1
1
1
Header time 4
1
0
0
0
Status display 1
1
0
0
1
Status display 2
1
0
1
0
Status display 3
1
0
1
1
Status display 4
1
1
0
0
PAL Pulse
1
1
0
1
Automatic PDC/VPS switching 2
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-21/32
LC74798, 74798M
COMMAND14 (VPS/PDC control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
0
2
—
1
1
—
1
0
—
1
Notes
Function
Command 7 identification code.
Display control setup.
Extended command 7 identification code
• Second byte
DA
0 to 7
7
Register
—
6
VMWSE2
5
VMWSEL
4
HBS2
3
HBS1
2
1
0
Contents
State
0
Second byte identification bit
0
V mask period start - From the retrace period
1
V mask period start - From 10H before the retrace period
0
The V mask period is the retrace period
1
The V mask period is 9H
0
Discrimination mode 1
1
Discrimination mode 2
0
Discrimination mode 1
1
Discrimination mode 2
0
Error check valid (Error checking can be turned on or off on a per-byte
basis.)
1
Error check invalid (Applications can select whether data for which an
error is detected is held or writing on a per-byte basis.)
BMS
EMS
0
Data hold
1
Data write
(When the error bit is 0 in VPS mode.)
0
Error checking enabled for unused data bytes.
VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21,
status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
DCE
1
Notes
Function
Error checking disabled for unused data bytes.
VPS: bytes 3, 4, and 6 to 10, PDCC (8/30/2): bytes 7 to 12, header 1:
bytes 14 to 37, header 2: bytes 14 to 29, header 3: bytes 14 to 21,
status 1 (3): bytes 7 to 25, status 2 (4): bytes 7 to 35
CPOUT pin (pin 13) V mask period switching 2
CPOUT pin (pin 13) V mask period switching
Clock line
Framing code
When set to 0, if there are no errors in bytes for
which error checking is turned on, those bytes are
written to P-S. When set to 1, all bytes are written
to P-S regardless of the error status.
Specifies handling of bytes for which error
checking is set to off but in which an error occurred
when error checking is turned on.
Error checking setting for unused data bytes.
Biphase (VPS), Hamming (PDC), and odd parity
(header).
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-22/32
LC74798, 74798M
COMMAND15 (VPS/PDC control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
0
0
—
0
Function
Notes
Command 7 identification code.
Display control setup.
Extended command 8 identification code
• Second byte
DA
0 to 7
Register
Contents
State
7
—
0
6
—
0
5
ECV15
4
3
2
1
0
Function
Notes
Second byte identification bit
0
Byte 15 biphase error check on (Data hold)
1
Byte 15 biphase error check off (Data write)
0
Byte 14 biphase error check on (Data hold)
1
Byte 14 biphase error check off (Data write)
0
Byte 13 biphase error check on (Data hold)
1
Byte 13 biphase error check off (Data write)
0
Byte 12 biphase error check on (Data hold)
1
Byte 12 biphase error check off (Data write)
0
Byte 11 biphase error check on (Data hold)
1
Byte 11 biphase error check off (Data write)
0
Byte 5 biphase error check on (Data hold)
1
Byte 5 biphase error check off (Data write)
Specification when the VPS data BMS bit is 0.
The item in parentheses is the specification when
the VPS data BMS bit is 1.
ECV14
ECV13
ECV12
ECV11
ECV5
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-23/32
LC74798, 74798M
COMMAND16 (VPS/PDC control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
0
0
—
1
Function
Notes
Command 7 identification code.
Display control setup.
Extended command 9 identification code
• Second byte
DA
0 to 7
7
6
5
4
3
2
1
0
Register
—
Contents
State
Function
0
Second byte identification bit
0
Byte 19 Hamming error check on (Data hold)
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
1
Byte 19 Hamming error check off (Data write)
{Bytes 44, 28, 36, 20, 32, 42, 32, and 42}
0
Byte 18 Hamming error check on (Data hold)
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
1
Byte 18 Hamming error check off (Data write)
{Bytes 43, 27, 35, 19, 31, 41, 31, and 41}
0
Byte 17 Hamming error check on (Data hold)
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
1
Byte 17 Hamming error check off (Data write)
{Bytes 42, 26, 34, 18, 30, 40, 30, and 40}
0
Byte 16 Hamming error check on (Data hold)
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
1
Byte 16 Hamming error check off (Data write)
{Bytes 41, 25, 33, 17, 29, 39, 29, and 39}
0
Byte 15 Hamming error check on (Data hold)
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
1
Byte 15 Hamming error check off (Data write)
{Bytes 40, 24, 32, 16, 28, 38, 28, and 38}
0
Byte 14 Hamming error check on (Data hold)
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
1
Byte 14 Hamming error check off (Data write)
{Bytes 39, 23, 31, 15, 27, 37, 27, and 37}
0
Byte 13 Hamming error check on (Data hold)
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
1
Byte 13 Hamming error check off (Data write)
{Bytes 38, 22, 30, 14, 26, 36, 26, and 36}
ECP19
ECP18
ECP17
ECP16
ECP15
ECP14
ECP13
Notes
Specification when the PDC data (8/30/2) BMS bit
is 0.
The item in parentheses is the specification when
the BMS bit is 1.
The item in curl braces lists the odd parity check
on/off bytes for header modes 1, 2, 3, and 4 and
status mode 1, 2, 3, and 4.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-24/32
LC74798, 74798M
COMMAND17 (VPS/PDC control setup command)
• First byte
DA
0 to 7
Register
Contents
State
7
—
1
6
—
1
5
—
1
4
—
1
3
—
1
2
—
0
1
—
1
0
—
0
Function
Notes
Command 7 identification code.
Display control setup.
Extended command A identification code
• Second byte
DA
0 to 7
Register
Contents
State
7
—
0
6
—
0
5
4
3
2
1
0
Function
Second byte identification bit
0
Byte 25 Hamming error check on (Data hold)
1
Byte 25 Hamming error check off (Data write)
0
Byte 24 Hamming error check on (Data hold)
1
Byte 24 Hamming error check off (Data write)
0
Byte 23 Hamming error check on (Data hold)
ECP25
ECP24
ECP23
1
Byte 23 Hamming error check off (Data write)
0
Byte 22 Hamming error check on (Data hold)
{Bytes -, -, -, -, 35, 45, 35, and 45}
1
Byte 22 Hamming error check off (Data write)
{Bytes -, -, -, -, 35, 45, 35, and 45}
0
Byte 21 Hamming error check on (Data hold)
{Bytes -, -, -, -, 34, 44, 34, and 44}
1
Byte 21 Hamming error check off (Data write)
{Bytes -, -, -, -, 34, 44, 34, and 44}
0
Byte 20 Hamming error check on (Data hold)
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
1
Byte 20 Hamming error check off (Data write)
{Bytes 45, 29, 37, 21, 33, 43, 33, and 43}
ECP22
ECP21
ECP20
Notes
Specification when the PDC data (8/30/2) BMS bit
is 0.
The item in parentheses is the specification when
the BMS bit is 1.
The item in curly braces lists the odd parity check
off bytes for header modes 1, 2, 3, and 4 and
status mode 1, 2, 3, and 4.
Note: All registers are set to 0 when the LC74798/M is reset by the RST pin.
No. 5833-25/32
LC74798, 74798M
PDC/VPS Output Data Format
Data is output in order starting with bit 7 of byte 1.
Output data
PDC 8/30 mode
Format 1
VPS mode
Format 2
Header time mode 1 (3)
Header time mode 2 (4)
Data update bits *: Set to 0 when data is updated, and set to 1 when not updated.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Bit 7
bit 0
byte 38
bit 0
byte 22
6
byte 15
bit 0
1
1
1
(30)
1
(14)
5
2
2
2
2
2
3
4
3
3
4
2
byte 16
bit 0
byte 11
bit 0
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
Bit 7
byte 16
bit 0
byte 17
byte 18
bit 0
byte 12
bit 0
byte 39
(31)
7
bit 0
byte 23
1
(15)
bit 0
6
1
1
1
5
2
2
2
2
2
3
4
3
3
4
2
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
Bit 7
byte 17
bit 0
byte 19
byte 20
bit 0
byte 13
bit 0
byte 40
(32)
7
bit 0
byte 24
1
(16)
bit 0
6
1
1
1
5
2
2
2
2
2
3
4
3
3
4
2
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
Bit 7
byte 18
bit 0
byte 21
byte 22
bit 0
byte 14
bit 0
byte 41
(33)
7
bit 0
byte 25
1
(17)
bit 0
6
1
1
1
5
2
2
2
2
2
3
4
3
3
4
2
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
Bit 7
byte 19
bit 0
byte 23
byte 14
bit 0
byte 5
bit 0
byte 42
(34)
7
bit 0
byte 26
1
(18)
bit 0
6
1
1
1
5
2
2
2
2
2
3
4
3
3
4
2
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
Bit 7
byte 20
bit 0
byte 15
byte 24
bit 0
byte 15
bit 0
byte 43
(35)
7
bit 0
byte 27
1
(19)
bit 0
6
1
1
1
5
2
2
2
2
2
3
4
3
3
4
2
1
3
3
3
bit 0
4
4
4
5
1
5
5
5
1
6
2
6
6
6
0
7
3
7
7
byte 25
7
Continued on next page.
No. 5833-26/32
LC74798, 74798M
Continued from preceding page.
Output data
Byte 7
Byte 8
Byte 9
Byte 10
Bit 7
PDC 8/30 mode
Format 1
bit 0
1
byte 44
bit 0
byte 28
bit 0
1
1
(36)
1
(20)
1
5
2
2
1
2
2
4
3
3
1
3
3
3
4
1
1
4
4
2
5
1
1
5
5
1
6
1
1
6
6
0
7
1
1
7
bit 0
byte 29
bit 0
(37)
1
(21)
1
13
2
2
4
3
19
14
3
3
3
4
20
5
4
4
2
5
21
15
5
5
1
6
22
0
6
6
0
7
23
0
7
bit 0
Error
12
14
Error
byte 38 (30) Error
15
information 2
7
byte 22 (14)
6
1
39 (31) information 2
23 (15)
5
2
24
40 (32)
24 (16)
4
3
25
41 (33)
25 (17)
3
4
13
42 (34)
26 (18)
2
5
0
43 (35)
27 (19)
1
6
0
44 (36)
28 (20)
0
7
0
45 (37)
29 (21)
Bit 7
byte 22
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
Bit 7
7
byte 23
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
Bit 7
7
byte 24
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
Bit 7
information 2
information 1
7
byte 45
18
byte 14
17
byte 11
2
Bit 7
information 1
Error
1
0
Byte 13
byte 16
5
0
Byte 12
Error
6
0
Byte 11
bit 0
byte 13
Header time mode 2 (4)
1
byte 13
bit 0
Header time mode 1 (3)
6
Bit 7
byte 21
VPS mode
Format 2
7
byte 25
bit 0
6
1
5
2
4
3
3
4
2
5
1
6
0
7
Bits for which data is not set are set to 1.
No. 5833-27/32
LC74798, 74798M
Data is output in order starting with bit 7 of byte 1.
1, 2 : 8/30/2 3, 4 : 8/30/1
Output data
Status display
Status display
mode 1 (3)
mode 2 (4)
PAL Puls
Data update bits *: Set to 0 when data is updated.
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Bit 7
byte 26
bit 0
byte 36
bit 0
bit 0
6
(26)
1
(36)
1
1
5
2
2
2
4
3
3
3
3
4
4
4
2
5
5
5
1
6
6
6
0
7
7
7
bit 8
Bit 7
byte 27
6
(27)
bit 0
byte 37
bit 0
1
(37)
1
9
5
2
2
10
4
3
3
11
3
4
4
12
2
5
5
13
1
6
6
0
0
7
7
0
Bit 7
byte 28
6
(28)
bit 0
byte 38
bit 0
1
(38)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 29
6
(29)
7
bit 0
byte 39
bit 0
1
(39)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 30
6
(30)
7
bit 0
byte 40
bit 0
1
(40)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 31
6
(31)
7
bit 0
byte 41
bit 0
1
(41)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
byte 32
6
(32)
7
bit 0
byte 42
bit 0
1
(42)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
7
Continued on next page.
No. 5833-28/32
LC74798, 74798M
Continued from preceding page.
Output data
Byte 8
Byte 9
Byte 10
Byte 11
mode 2 (4)
byte 33
bit 0
byte 43
bit 0
6
(33)
1
(43)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
byte 34
bit 0
byte 44
bit 0
6
(34)
1
(44)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
7
Bit 7
byte 35
bit 0
byte 45
bit 0
6
(35)
1
(45)
1
5
2
2
4
3
3
3
4
4
2
5
5
1
6
6
0
7
Bit 7
Error
7
byte 26 (26)
information 1
PAL Puls
7
Bit 7
27 (27)
Error
byte 36 (36)
information 1
37 (37)
5
28 (28)
38 (38)
4
29 (29)
39 (39)
3
30 (30)
40 (40)
2
31 (31)
41 (41)
1
32 (32)
42 (42)
0
33 (33)
Bit 7
6
Byte 13
Status display
mode 1 (3)
Bit 7
6
Byte 12
Status display
Error
byte 34 (34)
information 2
35 (35)
43 (43)
Error
byte 44 (44)
information 2
45 (45)
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Bit 7
6
5
4
3
2
1
0
No. 5833-29/32
LC74798, 74798M
Display Screen Structure
The display consists of 12 lines of 24 characters.
Up to 288 characters can be displayed.
The number of characters that can be displayed is reduced from the 288 maximum when enlarged characters are
displayed.
Display memory addresses are specified as row (0 to B hexadecimal) and column (0 to 17 hexadecimal) addresses.
Display Screen Structure (display memory addresses)
24 Characters
12 Rows
No. 5833-30/32
LC74798, 74798M
Composite Video Signal Output Levels (internally generated levels)
CVOUT output level waveform (VDD2 = 5.00 V)
Output level
VCHA
: Character
VRSH
: Background color high
VCBH
: Color burst high
VRSL
: Background color low
VBK1
VBK0
Output voltage (1) [V]
Output voltage (2) [V]
2.65
2.85
Output voltage (3) [V]
3.25
2.37 (2.01)
2.57 (2.21)
2.97 (2.61)
1.67
1.87
2.27
1.23 (1.16)
1.43 (1.36)
1.83 (1.76)
: Frame
2.08
2.28
2.68
: Frame
1.50
1.70
2.10
VPD
: Pedestal
1.37
1.57
1.97
VCBL
: Color burst low
1.07
1.27
1.67
VSN
: Sync
0.80
1.00
1.40
Note: VDD2 = 5.00V. The values in parentheses for VRSH and VRSL are the values for a blue background.
No. 5833-31/32
LC74798, 74798M
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of May, 1998. Specifications and information herein are subject to change
without notice.
PS No. 5833-32/32