SANYO LC78625E

Ordering number : EN5502
CMOS LSI
LC78625E
Compact Disc Player DSP
Overview
The LC78625E is a CMOS LSI that implements the signal
processing and servo control required by compact disc
players, laser discs, CD-V, CD-I and related products. The
LC78625E provides several types of signal processing,
including demodulation of the optical pickup EFM signal,
de-interleaving, error detection and correction, and digital
filters that can help reduce the cost of CD player units. It
also processes a rich set of servo system commands sent
from the control microprocessor. It also incorporates an
EFM-PLL circuit and a one-bit D/A converter.
This LSI is an improved version of the LC78620E. In
addition to supporting low-voltage operation, on/off
control of the de-emphasis function and use of the
bilingual function have been enabled in certain additional
modes.
Functions
• The LC78625E takes an HF signal as input, digitizes
(slices) that signal at a precise level, converts that signal
to an EFM signal, and generates a PLL clock with an
average frequency of 4.3218 MHz by comparing the
phases of that signal and an internal VCO.
• A precise reference clock and the necessary internal
timings are generated using an external 16.9344 MHz
crystal oscillator.
• Disc motor speed control using a frame phase difference
signal generated from the playback clock and the
reference clock
• Frame synchronization signal detection, protection, and
interpolation to assure stable data readout
• EFM signal demodulation and conversion to 8-bit
symbol data
• Subcode data separation from the EFM demodulated
signal and output of that data to an external
microprocessor
• Subcode Q signal output (LSB first) to a microprocessor
over the serial interface after performing a CRC error
check
• Demodulated EFM signal buffering in internal RAM to
handle up to ±4 frames of disc rotational jitter
• Demodulated EFM signal reordering in the prescribed
order for data unscrambling and de-interleaving
• Error detection, correction, and flag processing (error
correction scheme: dual C1 plus dual C2 correction)
• The LC78625E sets the C2 flags based on the C1 flags
and a C2 check, and then performs signal interpolation
or muting depending on the C2 flags. The interpolation
circuit uses a quadruple interpolation scheme. The
output value converges to the muting level when four or
more consecutive C2 flags occur.
Package Dimensions
unit: mm
3174-QFP80E
[LC78625E]
SANYO: QFP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
22897HA (OT) No. 5502-1/35
LC78625E
• Support for command input from a control microprocessor: commands include track jump, focus start, disk motor
start/stop, muting on/off and track count (8-bit serial input)
• Built-in digital output circuits.
• Arbitrary track counting to support high-speed data access
• D/A converter outputs with data continuity improved by 8× oversampling digital filters. (These filters function as 4×
oversampling filters during double-speed playback.)
• Built-in ∑∆ D/A converter implemented by a third-order noise shaper circuit (for PWM output)
• Built-in digital attenuator (8 bits - alpha, 239 steps)
• Built-in digital de-emphasis circuit that can be controlled externally in some modes
• Zero-cross muting
• Support for 2×-speed dubbing
• Support for bilingual applications
• General-purpose I/O ports: 4 pins (when the antishock mode is turned off)
Features
• 5 V single-voltage power supply
• Low-voltage operation: Can be operated at 3.3 V ±10% (at normal playback speed)
• 80-pin QFP package
Equivalent Circuit Block Diagram
No. 5502-2/35
LC78625E
Pin Assignment
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Maximum input voltage
Maximum output voltage
Allowable power dissipation
Symbol
Conditions
Ratings
VDD max
Unit
VSS – 0.3 to +7.0
V
VIN
VSS – 0.3 to VDD + 0.3
V
VOUT
VSS – 0.3 to VDD + 0.3
Pd max
300
V
mW
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Allowable Operating Ranges at Ta = 25°C, VSS = 0 V
Parameter
Symbol
Input low-level voltage
Data setup time
Ratings
min
typ
max
Unit
VDD (1)
VDD, XVDD, LVDD, RVDD, VVDD :
At normal playback speed
3.0
5.5
V
VDD (2)
VDD, XVDD, LVDD, RVDD, VVDD :
At 2× playback speed
4.5
5.5
V
VIH (1)
DEFI, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK, TAI, TEST1 to
TEST5, DEMO, CS
0.7 VDD
VDD
V
VIH (2)
EFMIN
0.6 VDD
VDD
V
VIL (1)
DEFI, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK, TAI, TEST1 to
TEST5, DEMO, CS
0
0.3 VDD
V
VIL (2)
EFMIN
0
0.4 VDD
Supply voltage
Input high-level voltage
Conditions
V
tSU
COIN, RWC : Figure 1
400
ns
Data hold time
tHD
COIN, RWC : Figure 1
400
ns
High-level clock pulse width
tWH
SBCK, CQCK : Figuires 1, 2 and 3
400
ns
Low-level clock pulse width
tWL
SBCK, CQCK : Figuires 1, 2 and 3
400
Data read access time
tRAC
SQOUT, PW : Figuires 2 and 3
0
ns
400
ns
Continued on next page.
No. 5502-3/35
LC78625E
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Command transfer time
tRWC
RWC : Figure 1
Subcode Q read enable time
tSQE
WRQ: Figure 2, with no RWC signal
typ
Unit
max
1000
ns
11.2
ms
Subcode read cycle
tSC
SFSY : Figure 3
Subcode read enable time
tSE
SFSY : Figure 3
400
ns
Port input data setup time
tPSU
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 4
400
ns
Port input data hold time
tPHD
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 4
400
ns
Port input clock setup time
tRCQ
CQCK, RWC : Figure 4
100
ns
tPDD
ASDACK/P0, ASFIN/P1, ASDEPC/P2,
ASLRCK/P3, RWC : Figure 5
Port output data delay time
136
1200
VIN (1)
EFMIN
1.0
VIN (2)
XIN : Capacitor coupled input
1.0
Operating frequency range
fOP (1)
EFMIN
Crystal oscillator frequency
fX
Input level
µs
Vp-p
Vp-p
10
XIN, XOUT : In 16M mode
ns
16.9344
MHz
MHz
Electrical Characteristics at Ta = 25°C, VDD = 5 V, VSS = 0 V
Parameter
Current drain
Symbol
min
typ
IDD
30
IIH (1)
DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK : VIN = 5 V
IIH (2)
TAI, TEST1 to TEST5, DEMO, CS :
VIN = VDD = 5.5 V
Input high-level current
Input low-level current
Ratings
Conditions
IIL
VOH (1)
DEFI, EFMIN, FZD, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, COIN, RES, HFL,
TES, SBCK, RWC, CQCK, TAI, TEST1 to
TEST5, DEMO, CS : VIN = 0 V
EFMO, EFMO, CLV+, CLV–, V/P, FOCS,
PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–,
25
Unit
max
45
mA
5
µA
75
µA
–5
µA
4
V
4
V
EMPH, EFLG, FSX : IOH = –1 mA
Output high-level voltage
VOH (2)
MUTEL, MUTER, LRCKO, DFORO, DFOLO,
DACKO, TST10, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, LRSY, CK2,
ROMXA, C2F, SBSY, PW, SFSY, WRQ,
SQOUT, TST11, 16M, 4.2M, CONT :
IOH = –0.5 mA
VOH (3)
LASER : IOH = –1 mA
4.6
V
VOH (4)
DOUT : IOH = –12 mA
4.5
V
VOH (5)
LCHP, RCHP, LCHN, RCHN : IOH = –1 mA
EFMO, EFMO, CLV+, CLV–, V/P, FOCS,
PCK, FSEQ, TOFF, TGL, THLD, JP+, JP–,
3.0
VOL (1)
4.5
V
1
V
0.4
V
EMPH, EFLG, FSX : IOL = 1 mA
Output low-level voltage
Output off leakage current
VOL (2)
MUTEL, MUTER, LRCKO, DFORO, DFOLO,
DACKO, TST10, ASDACK/P0, ASFIN/P1,
ASDEPC/P2, ASLRCK/P3, LRSY, CK2,
ROMXA, C2F, SBSY, PW, SFSY, WRQ,
SQOUT, TST11, 16M, 4.2M, CONT, LASER :
IOL = 2 mA
VOL (3)
DOUT : IOL = 12 mA
VOL (4)
FST : IOL = 5 mA
VOL (5)
LCHP, RCHP, LCHN, RCHN : IOL = 1 mA
PDO, CLV+, CLV–, JP+, JP–, FST :
IOFF (1)
IOFF (2)
Charge pump output current
VOUT = 5 V
PDO, CLV+, CLV–, JP+, JP– : V
OUT = 0 V
0.5
0.5
V
0.75
V
2.0
V
5
µA
–5
µA
IPDOH
PDO : RISET = 68 kΩ
100
125
150
µA
IPDOL
PDO : RISET = 68 kΩ
–150
–125
–100
µA
Note: For guaranteed operation, the VCO oscillator frequency range adjustment resistor FR must be a 1.20 kΩ ±5.0% tolerance resistor.
No. 5502-4/35
LC78625E
One-Bit D/A Converter Analog Characteristics at Ta = 25°C, VDD = LVDD = RVDD = 5 V, VSS = LVSS = RVSS = 0 V
Parameter
Total harmonic distortion
Symbol
THD + N
Conditions
Ratings
min
LCHP, RCHP, LCHN, RCHN;
1 kHz: 0 dB data input, using the 20 kHz
low-pass filter (AD725D built in)
typ
max
0.008
0.0010
Unit
%
Dynamic range
DR
LCHP, RCHP, LCHN, RCHN;
1 kHz: –60 dB data input, using the 20 kHz
low-pass filter and the A filter (AD725D built in)
84
88
dB
Signal-to-noise ratio
S/N
LCHP, RCHP, LCHN, RCHN;
1 kHz: 0 dB data input, using the 20 kHz
low-pass filter and the A filter (AD725D built in)
98
100
dB
Crosstalk
CT
LCHP, RCHP, LCHN, RCHN;
1 kHz: 0 dB data input, using the 20 kHz
low-pass filter (AD725D built in)
96
98
dB
Note: Measured with the normal-speed playback mode digital attenuator in the Sanyo one-bit D/A converter block reference circuit.
Figure 1 Command Input
Figure 2 Subcode Q Output
Figure 3 Subcode Output
No. 5502-5/35
LC78625E
Figure 4 General-Purpose Port Input Timing
Figure 5 General-Purpose Port Output Timing
No. 5502-6/35
LC78625E
One-Bit D/A Converter Output Block Reference Circuit
No. 5502-7/35
LC78625E
Pin Functions
Pin No.
Symbol
I/O
1
DEFI
I
2
TAI
I
3
PDO
O
4
VVSS
5
ISET
6
VVDD
7
FR
8
VSS
Function
Defect detection signal (DEF) input (This pin must be connected to 0 V if unused.)
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V in normal operation.)
External VCO control phase comparator output
Internal VCO ground. (This pin must be connected to 0 V.)
AI
PLL pins
PDO output current adjustment resistor connection
Internal VCO power supply.
AI
VCO frequency range adjustment
Digital system ground. (This pin must be connected to 0 V.)
9
EFMO
O
10
EFMO
O
EFM signal inverted output
11
EFMIN
I
12
I
Test input. A pull-down resistor is built in. This pin must be connected to 0 V in normal operation.
13
TEST2
CLV+
O
Spindle servo control output. Acceleration when CLV+ is high, deceleration when CLV- is high.
14
CLV–
O
Three-value output is also possible when specified by microprocessor command.
15
V/P
O
Rough servo/phase control automatic switching monitor output. Outputs a high level during rough servo and a low level during
phase control.
16
FOCS
O
Focus servo on/off output. Focus servo is on when the output is low.
17
FST
O
Focus start pulse output. This is an open-drain output.
18
FZD
I
Focus error zero cross signal input. (This pin must be connected to 0 V if unused.)
19
HFL
I
Track detection signal input. This is a Schmitt input.
20
TES
I
Tracking error signal input. This is a Schmitt input.
21
PCK
O
EFM data playback clock monitor. Outputs 4.3218 MHz when the phase is locked.
22
FSEQ
O
Synchronization signal detection output. Outputs a high level when the synchronization signal detected from the EFM signal and
the internally generated synchronization signal agree.
23
TOFF
O
Tracking off output
24
TGL
O
Tracking gain switching output. Increase the gain when low.
25
THLD
O
Tracking hold output
26
TEST3
I
27
VDD
28
JP+
O
Track jump output. A high level output from JP+ indicates acceleration during an outward jump or deceleration during an inward
jump.
29
JP–
O
A high level output from JP- indicates acceleration during an inward jump or deceleration during an outward jump.
Three-value output is also possible when specified by microprocessor command.
30
DEMO
I
Sound output function input used for end product adjustment manufacturing steps. A pull-down resistor is built in. (This pin must
be connected to 0 V.)
31
TEST4
I
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
32
EMPH
O
De-emphasis monitor pin. A high level indicates playback of a de-emphasis disk.
33
LRCKO
O
34
DFORO
O
35
DFOLO
O
36
DACKO
O
37
TST10
O
Slice level control
EFM signal output
EFM signal input
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
Digital system power supply.
Word clock output
Right channel data output
Digital filter outputs
Left channel data output
Bit clock output
Test output. Leave open. (Normally outputs a low level.)
Continued on next page.
No. 5502-8/35
LC78625E
Continued from preceding page.
Pin No.
Symbol
38
ASDACK/P0
39
ASDFIN/P1
40
ASDEPC/P2
I/O
Function
I/O • When antishock mode is not used,
these pins are used as generalI/O
purpose I/O ports (P0 to P3). They
must either be set to input mode and
I/O
connected to 0 V, or set to output
mode and left open, if unused.
I/O
The antishock inputs in
antishock mode.
Bit clock input
Left and right channel data input
Sets the built-in de-emphasis filter on or off.
(High: on, low: off)
41
ASLRCK/P3
42
LRSY
O
L/R clock output
43
CK2
O
Bit clock output
(after reset)
Inverted polarity clock output
(during CK2CON mode)
44
ROMXA
O
Interpolation data output
(after reset)
ROM data output (during ROMXA mode)
45
C2F
O
C2 flag output
46
MUTEL
O
47
LVDD
ROMXA application output signals
L/R clock input
Left channel mute output
Left channel power supply
48
LCHP
O
49
LCHN
O
50
LVSS
51
RVSS
52
RCHN
O
53
RCHP
O
54
RVDD
55
MUTER
O
56
DOUT
O
Digital output
57
SBSY
O
Subcode block synchronization signal output
58
EFLG
O
C1, C2, single and double error correction monitor pin
59
PW
O
Subcode P, Q, R, S, T, U and W output
60
SFSY
O
Subcode frame synchronization signal output. This signal falls when the subcodes are in the standby state.
61
SBCK
I
Subcode readout clock input. This is a Schmitt input. (This pin must be connected to 0 V if unused.)
62
FSX
O
Output for the 7.35 kHz synchronization signal divided from the crystal oscillator
63
WRQ
O
Subcode Q output standby output
64
RWC
I
Read/write control input. This is a Schmitt input.
65
SQOUT
O
Subcode Q output
66
COIN
I
Command input from the control microprocessor
67
CQCK
I
Input for the command input acquisition clock or the SQOUT pin subcode readout clock input. This is a Schmitt input.
68
RES
I
Reset input. This pin must be set low briefly after power is first applied.
69
TST11
O
Test output. Leave open. (Normally outputs a low level.)
70
LASER
O
Laser on/off output. Controlled by serial data commands from the control microprocessor.
71
16M
O
16.9344 MHz output
72
4.2M
O
4.2336 MHz output
73
CONT
O
Supplementary control output. Controlled by serial data commands from the control microprocessor.
74
TEST5
I
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
75
CS
I
76
XVSS
One-bit D/A converter signals
XIN
I
O
XVDD
Right channel N output
Right channel P output
Right channel mute output
Chip select input. A pull-down resistor is built in. This pin must be connected to 0 V if unused.
Crystal oscillator ground. Must be connected to 0 V.
XOUT
TEST1
Right channel ground. Must be connected to 0 V.
Right channel power supply
78
79
Left channel N output
Left channel ground. Must be connected to 0 V.
77
80
Left channel P output
Connections for a 16.9344 MHz crystal oscillator
Crystal oscillator power supply
I
Test input. A pull-down resistor is built in. (This pin must be connected to 0 V.)
Note: All power-supply pins (VDD, VVDD, LVDD, RVDD, and XVDD) must be connected to the same potential.
No. 5502-9/35
LC78625E
CD System Block Diagrams
Pin Applications
1. HF signal input circuit; Pin 11: EFMIN, pin 10: EFMO, pin 9: EFMO, pin 1: DEFI, pin 13: CLV+
An EFM signal (NRZ) sliced at an optimal level can be
acquired by inputting the HF signal to EFMIN.
The LC78625E handles defects as follows. When a high
level is input to the DEFI pin (pin 1), the EFMO (pin 9) and
EFMO (pin 10) pins (the slice level control outputs) go to the
high-impedance state, and the slice level is held. However,
note that this function is only valid in CLV phase control
mode, that is, when the V/P pin (pin 15) is low. This function
can be used in combination with the LA9230/40 series DEF
pin.
Note: If the EFMIN and CLV+ signal lines are too close to
each other, unwanted adiation can result in error rate
degradation. We recommend laying a ground or VDD
shield line between these two lines.
2. PLL clock generation circuit; Pin 3: PDO, pin 5: ISET, pin 7: FR, pin 21: PCK
Since the LC78625E includes a VCO circuit, a PLL circuit
can be formed by connecting an external RC circuit. ISET is
the charge pump reference current, PDO is the VCO circuit
loop filter, and FR is a resistor that determines the VCO
frequency range.
(Reference values)
R1 = 68 kΩ, C1 = 0.1 µF
R2 = 680 kΩ, C2 = 0.1 µF
R3 = 1.2 kΩ
Note: We recommend using a ±5.0% tolerance carbon film
resistor for R3.
No. 5502-10/35
LC78625E
3. VCO monitor; Pin 21: PCK
PCK is a monitor pin that outputs an average frequency of 4.3218 MHz, which is the VCO frequency divided by two.
4. Synchronization detection monitor; Pin 22: FSEQ
Pin 22 goes high when the frame synchronization (a positive polarity synchronization signal) from the EFM signal
read in by PCK and the timing generated by the counter (the interpolation synchronization signal) agree. This pin is
thus a synchronization detection monitor. (It is held high for a single frame.)
5. Servo command function; Pin 64: RWC, pin 66: COIN, pin 67: CQCK
Commands can be executed by setting RWC high and inputting commands to the COIN pin in synchronization with
the CQCK clock. Note that commands are executed on the falling edge of RWC.
Focus start
Track jump
Muting control
Disc motor control
Miscellaneous control
One byte commands
Track check
Two-byte command (RWC set twice)
Digital attenuator
General-purpose port I/O data setup
Two-byte commands (RWC set once)
• One-byte commands
• Two-byte commands (RWC set twice)
• Two-byte commands (RWC set once)
No. 5502-11/35
LC78625E
• Command noise rejection
Code
COMMAND
$EF
Command input noise reduction mode
$EE
Reset the above mode.
RES = L
●
This command reduces the noise on the CQCK clock signal. While this is effective for noise pulses shorter than 500
ns, the CQCK timings tWL, tWH, and tSU (see page 5, figures 1 and 2), must be set to be at least 1 µs.
6. Focus servo circuit; Pin 16: FOCS, pin 17: FST, pin 18: FZD, pin 70: LASER
Code
COMMAND
$08
FOCUS START #1
$A2
FOCUS START #2
$0A
LASER ON
$8A
LASER OFF
$FE
NOTHING
RES = L
●
The FOCS, FST, and FZD pins are not required when the LC78625E is used in combination with an LA9230/40
Series LSI. FZD should be connected to 0 V when these pins are not used. The LA9230/40 Series focus start
command is identical to the LC78625E FOCUS START #1 command.
• NOTHING
This command can be used to initialize the LC78625E by inputting FE (hexadecimal: Hexadecimal constants are
written with a dollar sign ($) prefix). Note that $00 is the reset command for the LA9230/40 Series, and should be
used with care since it clears the result of the automatic adjustment process and returns these chips to their initial
states.
• Laser control
The LASER pin can be use as an extended output port.
• Focus start
When the LC78625E is used in combination with an LA9230/40 Series LSI, the focus start operation is executed
completely on the servo side by commands from the control microprocessor. The following section describes this
operation when the LC78625E is used in combination with an LA9210M or LA9211M.
When a focus start instruction (either FOCUS START #1 or FOCUS START #2) is input as a servo command, first the
charge on capacitor C1 is discharged by FST and the objective lens is lowered. Next, the capacitor is charged by FOCS,
and the lens is slowly raised. FZD falls when the lens reaches the focus point. When this signal is received, FOCS is
reset and the focus servo turns on. After sending the command, the microprocessor should check the in-focus detection
signal (the LA9210 DRF signal) to confirm focus before proceeding to the next part of the program. If focus is not
achieved by the time C1 is fully charged, the microprocessor should issue another focus command and iterate the focus
servo operation.
No. 5502-12/35
LC78625E
Note:* Values in parentheses are for the FOCUS START #2 command. The only difference is in the FST low period.
* An FZD falling edge will not be accepted during the period that FST is low.
* After issuing a focus start command, initialization will be performed if RWC is set high. Therefore, do not issue the next command during focus start
until the focus coil drive S curve has completed.
* When focus cannot be achieved (i.e., when FZD does not go low) the FOCS signal will remain in the high state and the lens will remain raised, so the
microprocessor should initialize the system by issuing a NOTHING command.
* When the RES pin is set low, the LASER pin is set high directly.
* Focus start using the DEMO pin executes a mode #1 focus start.
No. 5502-13/35
LC78625E
7. CLV servo circuit; Pin 13: CLV+, pin 14: CLV–, pin 15: V/P
Code
COMMAND
$04
DISC MOTOR START (accelerate)
RES = L
$05
DISC MOTOR CLV (CLV)
$06
DISC MOTOR BRAKE (decelerate)
$07
DISC MOTOR STOP (stop)
●
The CLV+ pin provides the signal that accelerates the disk in the forward direction and the CLV– pin provides the
signal that decelerates the disk. Commands from the control microprocessor select one of the four modes accelerate,
decelerate, CLV and stop. The table below lists the CLV+ and CLV– outputs in each of these modes.
Mode
CLV+
CLV–
Accelerate
H
L
Decelerate
L
H
CLV
Pulse output
Pulse output
Stop
L
L
Note: * CLV servo control commands can set the TOFF pin low only in CLV mode. That pin will be at the high level at all other times. Control of the TOFF
pin by microprocessor command is only valid in CLV mode.
• CLV
mode
In CLV mode the LC78625E detects the disk speed from the HF signal and provides proper linear speed using several
different control schemes by switching the DSP internal modes. The PWM period corresponds to a frequency of 7.35
kHz. The V/P pin outputs a high level during rough servo and a low level during phase control.
CLV+
CLV–
V/P
Rough servo (When determined to be under speed)
H
L
H
Rough servo (When determined to be over speed)
L
H
H
PWM
PWM
L
Internal Mode
Phase control (PCK locked)
• Rough servo gain switching
Code
COMMAND
$A8
DISC 8 Set
$A9
DISC 12 Set
RES = L
●
For 8 cm discs, the rough servo mode CLV control gain can be set about 8.5 dB lower than the gain used for 12 cm
discs.
No. 5502-14/35
LC78625E
• Phase control gain switching
Code
COMMAND
$B1
CLV phase comparator divisor: 1/2
$B2
CLV phase comparator divisor: 1/4
$B3
CLV phase comparator divisor: 1/8
$B0
No CLV phase comparator divisor used
RES = L
●
The phase control gain can be changed by changing the divisor used by the dividers in the stage immediately preceding
the phase comparator.
• CLV three-value output
Code
COMMAND
$B4
CLV three-value output
$B5
CLV two-value output (the scheme used by previous products)
RES = L
●
The CLV three-value output command allows the CLV to be controlled by a single pin. However, the spindle gain is 6
dB lower when this pin is used, so applications must increase the gain in the servo system.
No. 5502-15/35
LC78625E
• Internal brake modes
Code
COMMAND
$C5
Internal brake on
$C4
Internal brake off
$A3
Internal brake CONT
$CB
Internal brake continuous mode
$CA
Reset continuous mode
$CD
TON mode during internal braking
$CC
Reset TON mode
RES = L
●
●
●
— Issuing the internal brake on command ($C5) sets the LC78625E to internal brake mode. In this mode, the disc
deceleration state can be monitored from the WRQ pin when a brake command ($06) is executed.
— In this mode the disc deceleration state is determined by counting the EFM signal density in a single frame, and
when the EFM signal count falls under four, the CLV– pin is dropped to low. At the same time the WRQ signal,
which functions as a brake completion monitor, goes high. When the microprocessor detects a high level on the
WRQ signal, it should issue a STOP command to fully stop the disc. In internal brake continuous mode, the CLV–
pin high-level output braking operation continues even after the WRQ brake completion monitor goes high.
Note that if errors occur in deceleration state determination due to noise in the EFM signal, the problem can be
rectified by changing the EFM signal count from four to eight with the internal brake control command ($A3).
— In internal braking TON mode, the TOFF pin is held low during internal brake operations. We recommend using
this feature, since it is effective at preventing incorrect detection at the disc mirror surface.
Note:
If focus is lost during the execution of an internal brake command, the pickup must first be refocussed and then the internal brake command must
be reissued.
Since incorrect deceleration state determination is possible depending on the EFM signal playback state (e.g., disc defects, access in progress), we
recommend using these functions in combination with a microprocessor.
8. Track jump circuit; Pin 19: HFL, pin 20: TES, pin 23: TOFF, pin 24: TGL, pin 25: THLD, pin 28: JP+, pin 29: JP–
• The LC78625E supports the two track count modes listed below.
Code
COMMAND
RES = L
$22
New track count mode (using the TES/HFL combination)
●
$23
Previous track count mode (directly counts the TES signal)
The earlier track count function uses the TES signal directly as the internal track counter clock.
To reduce counting errors resulting from noise on the rising and falling edges of the TES signal, the new track count
function prevents noise induced errors by using the combination of the TES and HFL signals, and implements a more
reliable track count function. However, dirt and scratches on the disc can result in HFL signal dropouts that may result
in missing track count pulses. Thus care is required when using this function.
No. 5502-16/35
LC78625E
• TJ commands
Code
COMMAND
RES = L
$A0
Previous track jump
●
$A1
New track jump
$11
1 TRACK JUMP IN #1
$12
1 TRACK JUMP IN #2
$31
1 TRACK JUMP IN #3
$52
1 TRACK JUMP IN #4
$10
2 TRACK JUMP IN
$13
4 TRACK JUMP IN
$14
16 TRACK JUMP IN
$30
32 TRACK JUMP IN
$15
64 TRACK JUMP IN
$17
128 TRACK JUMP IN
$19
1 TRACK JUMP OUT #1
$1A
1 TRACK JUMP OUT #2
$39
1 TRACK JUMP OUT #3
$5A
1 TRACK JUMP OUT #4
$18
2 TRACK JUMP OUT
$1B
4 TRACK JUMP OUT
$1C
16 TRACK JUMP OUT
$38
32 TRACK JUMP OUT
$1D
64 TRACK JUMP OUT
$1F
128 TRACK JUMP OUT
$16
256 TRACK CHECK
$0F
TOFF
$8F
TON
$8C
TRACK JUMP BRAKE
$21
THLD period TOFF output mode
$20
Reset THLD period TOFF output mode
●
●
When the LC78625E receives a track jump instruction as a servo command, it first generates accelerating pulses
(period a) and next generates deceleration pulses (period b). The passage of the braking period (period c) completes the
specified jump. During the braking period, the LC78625E detects the beam slip direction from the TES and HFL
inputs. TOFF is used to cut the components in the TE signal that aggravate slip. The jump destination track is captured
by increasing the servo gain with TGL. In THLD period TOFF output mode the TOFF signal is held high during the
period when THLD is high.
Note: Of the modes related to disc motor control, the TOFF pin only goes low in CLV mode, and will be high during
start, stop, and brake operations. Note that the TOFF pin can be turned on and off independently by
microprocessor issued commands. However, this function is only valid when disc motor control is in CLV mode.
No. 5502-17/35
LC78625E
• Track jump modes
The table lists the relationships between acceleration pulses, deceleration pulses, and the braking period.
Previous Track Jump Mode
Item
New Track Jump Mode
a
b
c
a
b
c
1 TRACK JUMP IN (OUT) #1
233 µs
233 µs
60 ms
233 µs
233 µs
60 ms
1 TRACK JUMP IN (OUT) #2
0.5 track jump
period
233 µs
60 ms
0.5 track jump
period
0.5 track jump
period
60 ms
1 TRACK JUMP IN (OUT) #3
0.5 track jump
period
233 µs
This period does
not exist.
0.5 track jump
period
0.5 track jump
period
This period does
not exist.
1 TRACK JUMP IN (OUT) #4
0.5 track jump
period
233 µs
60 ms; TOFF is low
during the C period.
0.5 track jump
period
0.5 track jump
period
60 ms; TOFF is low
during the C period.
1 track jump
period
1 track jump
period
See note.
2 TRACK JUMP IN (OUT)
None
4 TRACK JUMP IN (OUT)
2 track jump
period
466 µs
60 ms
2 track jump
period
2 track jump
period
60 ms
16 TRACK JUMP IN (OUT)
9 track jump
period
7 track jump
period
60 ms
9 track jump
period
9 track jump
period
60 ms
32 TRACK JUMP IN (OUT)
18 track jump
period
14 track jump
period
60 ms
18 track jump
period
14 track jump
period
60 ms
64 TRACK JUMP IN (OUT)
36 track jump
period
28 track jump
period
60 ms
36 track jump
period
28 track jump
period
60 ms
128 TRACK JUMP IN (OUT)
72 track jump
period
56 track jump
period
60 ms
72 track jump
period
56 track jump
period
60 ms
256 TRACK CHECK
TOFF goes high during the period
when 256 tracks are passed over.
The a and b pulses are not output.
60 ms
TOFF goes high during the period
when 256 tracks are passed over.
The a and b pulses are not output.
60 ms
There are no a and b periods.
60 ms
There are no a and b periods.
60 ms
TRACK JUMP BRAKE
Note:* Applications can select whether or not a braking period (period C) is present. Code $F6 selects operation without a braking period, and code $7F
selects operation with a 60-ms braking period. The LC78625E defaults to no braking period operation after a reset.
* As indicated in the table, actuator signals are not output during the 256 TRACK CHECK function. This is a mode in which the TES signal is counted in
the tracking loop off state. Therefore, feed motor forwarding is required.
* The servo command register is automatically reset after one cycle of the track jump sequence (a, b, c) completes.
* If another track jump command is issued during a track jump operation, the contents of that new command will be executed immediately.
* The 1 TRACK JUMP #3 and 2 TRACK JUMP modes (the earlier modes) do not have a braking period (the C period). Since brake mode must be
generated by an external circuit, care is required when using this mode.
When the LC78625E is used in combination with an LA9230/40 Series LSI, since the THLD signal is generated by the
LA9230/40, the THLD pin (pin 25) will be unused, and should be left open.
No. 5502-18/35
LC78625E
• Tracking brake
The chart shows the relationships between the TES, HFL, and TOFF signals during the track jump C period. The TOFF
signal is extracted from the HFL signal by TES signal edges. When the HFL signal is high, the pickup is over the
mirror surface, and when low, the pickup is over data bits. Thus braking is applied based on the TOFF signal being
high when the pickup is moving from a mirror region to a data region and being low when the pickup is moving from a
data region to a mirror region.
• JP three-value output
Code
COMMAND
$B6
JP three-value output
$B7
JP two-value output (earlier scheme)
RES = L
●
The JP three value output command allows the track jump operation to be controlled from a single pin. However, the
kick gain is 6 dB lower when this pin is used, so applications must increase the gain in the servo system.
• Track check mode
Code
COMMAND
$F0
Track check in
$F8
Track check out
$FF
Two-byte command reset
RES = L
●
The LC78625E will count the specified number of tracks when the microprocessor sends an arbitrary binary value in
the range 8 to 254 after issuing either a track check in or a track check out command.
No. 5502-19/35
LC78625E
Note:*When the desired track count has been input in binary, the track check operation is started by the fall of RWC.
* During a track check operation the TOFF pin goes high and the tracking loop is turned off. Therefore, feed motor forwarding is required.
* When a track check in/out command is issued the function of the WRQ signal switches from the normal mode subcode Q standby monitor function to
the track check monitor function. This signal goes high when the track check is half completed, and goes low when the check finishes. The control
microprocessor should monitor this signal for a low level to determine when the track check completes.
* If a two-byte reset command is not issued, the track check operation will repeat. That is, to skip over 20,000 tracks, issue a track check 201 command
once, and then count the WRQ signal 100 times. This will check 20,000 tracks.
* After performing a track check operation, use the brake command to have the pickup lock onto the track.
9. Error flag output; Pin 58: EFLG, pin 62: FSX
The FSX signal is generated by dividing the crystal oscillator clock, and is a 7.35 kHz frame synchronization signal.
The error correction state for each frame is output from EFLG. The playback OK/NG state can be easily determined
from the extent of the high level that appears here.
10. Subcode P, Q, and R to W output circuit; Pin 59: PW, pin 57: SBSY, pin 60: SFSY, pin 61: SBCK
PW is the subcode signal output pin, and all the codes, P, Q, and R to W can be read out by sending eight clocks to
the SBCK pin within 136 µs after the fall of SFSY. The signal that appears on the PW pin changes on the rising edge
of SBCK. If a clock is not applied to SBCK, the P code will be output from PW. SFSY is a signal that is output for
each subcode frame cycle, and the falling edge of this signal indicates standby for the output of the subcode symbol
(P to W). Subcode data P is output on the fall of this signal.
SBSY is a signal output for each subcode block. This signal goes high for the S0 and S1 synchronization signals. The
fall of this signal indicates the end of the subcode synchronization signals and the start of the data in the subcode
block. (EIAJ format)
No. 5502-20/35
LC78625E
11. Subcode Q output circuit; Pin 63: WRQ, pin 64: RWC, pin 65: SQOUT, pin 67: CQCK, pin 75: CS
Code
COMMAND
$09
ADDRESS FREE
$89
ADDRESS 1
RES = L
●
Subcode Q can be read from the SQOUT pin by applying a clock to the CQCK pin.
Of the eight bits in the subcode, the Q signal is used for song (track) access and display. WRQ will be high only if the
data passed the CRC error check and the subcode Q format internal address is 1 (Note 1). The control microprocessor
can read out data from SQOUT in the order shown below by detecting this high level and applying CQCK. When
CQCK is applied the DSP disables register update internally. The microprocessor should give update permission by
setting RWC high briefly after reading has completed. WRQ will fall to low at this time. Since WRQ falls to low 11.2
ms after going high, CQCK must be applied during the high period. Note that data is read out LSB first.
Note: 1. These conditions will be ignored if an address free command is sent. This is provided to handle CD-ROM applications.
CONT
ADR
TNO
INDEX (POINT)*
MIN
SEC
*: Items in parentheses refer to the read-in area.
FRAME
ZERO
AMIN (PMIN)* /PKMIN
ASEC (PSEC)* /PKSEC
AFRAME (PFRAME)* /PKFRAME
LVM/PKM
16-bit data
LVM data/PKM data
LVM data/PKM data
Note: Normally, the WRQ pin indicates the subcode Q standby state. However, it is used for a different monitoring purpose in track check mode and during
internal braking. (See the items on track counting and internal braking for details.)
The LC78625E becomes active when the CS pin is low, and subcode Q data is output from the SQOUT pin. When the CS pin is high, the SQOUT pin
goes to the high-impedance state.
No. 5502-21/35
LC78625E
12. Level meter (LVM) data and peak meter (PKM) data readout
Code
COMMAND
$2B
PKM Set (LVM Reset)
$2C
LVM Set (PKM Reset)
$2D
PKM mask set
$2E
PKM mask reset
RES = L
●
●
• Level meter (LVM)
— The LVM set command ($2C) sets the LC78625E to LVM mode.
— LVM data is a 16-bit word in which the MSB indicates the L/R polarity and the low-order 15 bits are absolute
value data. A one in the MSB indicates left channel data and a zero indicates right channel data.
— LVM data is appended after the 80 bits of subcode Q data, and can be read out by applying 96 clock cycles to the
CQCK pin. Each time LVM data is read out the left/right channel state is inverted. Data is held independently for
both the left and right channels. In particular, the largest value that occurs between readouts for each channel is
held.
• Peak meter (PKM)
— The PKM set command ($2B) sets the LC78625E to PKM mode.
— PKM data is a 16-bit word in which the MSB is always zero and the low-order 15 bits are absolute value data. This
functions detects the maximum value that occurs in the data, whichever channel that value occurs in.
— PKM data is read out in the same manner as LVM data. However, data is not updated as a result of the readout
operation.
— The absolute time for PKM mode subcode Q data is computed by holding the absolute time (ATIME) detected after
the maximum value occurred and sending that value. (Normal operation uses relative time.)
— It is possible to set the LC78625E to ignore values larger than the already recorded value by issuing the PKM mask
set command, even in PKM mode. This function is cleared by issuing a PKM mask reset command. (This is used in
PK search in a memory track.)
13. Mute control circuit
Code
COMMAND
$01
MUTE
0 dB
$02
MUTE
–12 dB
$03
MUTE
–∞ dB
RES = L
●
An attenuation of 12 dB (MUTE –12 dB) or full muting (MUTE ∞ dB) can be applied by issuing the appropriate
command from the table. Since zero cross muting is used, there is minimal noise associated with this function. Zero
cross is defined for this function as the top seven bits being all ones or all zeros.
14. Interpolation circuit
Outputting incorrect audio data that could not be corrected by the error detection and correction circuit would result
in loud noises being output. To minimize this noise, the LC78625E replaces the incorrect data with linearly
interpolated data based on the correct data on either side of the incorrect data. More precisely, the LC78625E uses
this technique if C2 flags occurred up to three times in a row. If C2 flags occurred four or more times in a row, the
LC78625E converges the output level to the muting level. However, when correct data is finally output following
four or more C2 flag occurrences, the LC78625E replaces the 3 data items between the data output four items
previously and the correct data with linearly interpolated data.
No. 5502-22/35
LC78625E
15. Bilingual function
Code
COMMAND
RES = L
$28
STO CONT
●
$29
Lch CONT
$2A
Rch CONT
• Following a reset or when a stereo command ($28) has been issued, the left and right channel data is output to the left
and right channels respectively.
• When an Lch set command ($29) is issued, the left and right channels both output the left channel data.
• When an Rch set command ($2A) is issued, the left and right channels both output the right channel data.
16. De-emphasis; Pin 32: EMPH
The pre-emphasis on/off bit in the subcode Q control information is output from the EMPH pin. When this pin is
high, the LC78625E internal de-emphasis circuit operates and the digital filters and the D/A converter output deemphasized data.
17. Digital attenuator
Digital attenuation can be applied to the audio data by setting the RWC pin high and inputting the corresponding twobyte command to the COIN pin in synchronization with the CQCK clock.
Code
COMMAND
RES = L
$81
ATT
DATA
SET
DATA 00H Set
$82
ATT
4STEP
UP
(MUTE –∞dB)
$83
ATT
4STEP
DOWN
$84
ATT
8STEP
UP
$85
ATT
8STEP
DOWN
$86
ATT
16STEP
UP
$87
ATT
16STEP
DOWN
• Attenuation setup
Since the attenuation level is set to the muted state (a muting of -∞ is specified by an attenuation coefficient of 00H)
after the LC78625E is reset, the attenuation coefficient must be directly set to EEH (using the ATT DATA SET
command) to output audio signals. Note that the attenuation level can be set to one of 239 values from 00H to EEH.
These two-byte commands differ from the two-byte commands used for track counting in that it is only necessary to set
RWC once and a two-byte command reset is not required. (See the item on two-byte commands (RWC set once) on
page 11.)
After inputting the target attenuation level as a value in the range 00H to EEH, sending an attenuator step up/down
command will cause the attenuation level to approach the target value in steps of 4, 8, or 16 units as specified in
synchronization with rising edges on the LRSY input. However, the ATT DATA SET command sets the target value
directly. If a new data value is input during the transition, the value begins to approach the new target value at that
point. Note that the UP/DOWN distinction is significant here.
No. 5502-23/35
LC78625E
ATT DATA
Audio output level = 20 log ———————
100H
[dB]
For example, the formula below calculates the time required for the attenuation level to increase from 00H to EEH
when a 4STEP UP command is executed. Note that the control microprocessor must provide enough of a time margin
for this operation to complete before issuing the next attenuation level set command.
238 levels × 4 steps
———————— ·=21.6
ms
44.1 kHz (LRSY) ·
Note: * Setting the attenuation level to values of EFH or higher is disallowed to prevent overflows in one-bit D/A converter calculations from causing noise.
• Mute output; Pin 46: MUTEL, pin 55: MUTER
These pins output a high level when the attenuator coefficient is set to 00H and the data in each channel has been zero
for a certain period. If data input occurs once again, these pins go low immediately.
18. Digital filter outputs; Pin 33: LRCKO, pin 34: DFORO, pin 35: DFOLO, pin 36: DACKO
Data for use with an external D/A converter is output MSB first from DFORO and DFOLO in synchronization with
the falling edge of DACKO. These pins are provided so that an external D/A converter can be used if desired.
• Although this output is from 8x oversampling filters for normal-speed playback, digital 4× oversampling filters are
used in double-speed playback.
No. 5502-24/35
LC78625E
19. One-bit D/A converter
The LC78625E PWM block outputs a single data value in the range –3 to +3 once every 64fs period. To reduce
carrier noise, this block adopts an output format in which each data switching block is adjusted so that the PWM
output level does not invert. Also, the attenuator block detects 0 data and enters muting mode so that only a 0 value (a
50% duty signal) is output.
This block outputs a positive phase signal to the LCHP (RCHP) pin and a negative phase signal to the LCHN
(RCHN) pin. High-quality analog signals can be acquired by taking the differences of these two output pairs using
external low-pass filters.
The LC78625E includes built-in extraneous radiation suppression resistors (1 kΩ) in each of the LCHP/N and
RCHP/N pins.
• PWM output format
• PWM output example
20. CD-ROM outputs; Pin 42: LRSY, pin 43: CK2, pin 44: ROMXA, pin 45: C2F
Although the LC78625E is initially setup to output audio data from the interpolation circuit MSB first from the
ROMXA pin in synchronization with the LRSY signal, the circuit can be switched to output CD-ROM data by
issuing a CD-ROM XA command. Since this data has not been processed by the interpolation, muting, and other
digital circuits, it is appropriate for input to a CD-ROM encoder LSI. CK2 is a 2.1168 MHz clock, and data is output
on the CK2 falling edge. However, this clock polarity can be inverted by issuing a CK2 polarity inversion command.
C2F is the flag information for the data in 8-bit units. Note that the CD-ROM XA reset command has the same
function as the CONT pin (pin 73). The one-bit D/A converter switches to muted mode when a CD-ROMXA
command is input.
Code
COMMAND
$88
CD-ROMXA
$8B
CONT and CD-ROM XA reset
$C9
CK2 polarity inversion
RES = L
●
LC78625E CD-ROM encoder LSI (LC895XX) interface
No. 5502-25/35
LC78625E
21. Digital output circuit; Pin 56: DOUT
This is an output pin for use with a digital audio interface. Data is output in the EIAJ format. This signal has been
processed by the interpolation and muting circuits. This pin has a built-in driver circuit and can directly drive a
transformer.
Code
COMMAND
RES = L
$42
DOUT ON
●
$43
DOUT
OFF
$40
UBIT ON
$41
UBIT OFF
●
• The DOUT pin can be locked at the low level by issuing a DOUT OFF command.
• The UBIT information in the DOUT data can be locked at zero by issuing a UBIT OFF command.
• The DOUT data can be switched to data for which interpolation and muting processing have not been performed by
issuing a CD-ROM XA command.
22. Antishock mode; Pin 38: ASDACK, pin 39: ASDFIN, pin 40: ASDEPC, pin 41: ADLRCK, pin 42: LRSY, pin 43:
CK2, pin 44: ROMXA, pin 45: C2F
• Antishock mode is a mode in which antishock processing is applied to data that has been output once. That data can
be returned and output once again as an audio playback signal. It is also possible to use only the audio playback
block (the attenuator, 8x oversampling digital filter, and one-bit D/A converter circuits) and thus share the audio
playback block with other systems by synchronizing the other system with this LSI's clock.
Note that de-emphasis on/off switching is controlled by the level applied to the ASDEPC pin. De-emphasis is
turned on by a high level.
• The ASDACK (pin 38), ASDFIN (pin 39), ASDEPC (pin 40), and ASLRCK (pin 41) pins can be used as generalpurpose ports (see page 23) if this mode is not used.
Code
COMMAND
$6C
ANTIC ON
$6B
ANTIC
OFF
$6F
DF normal speed on (only in antishock mode)
$6E
DF normal speed off (only in antishock mode)
RES = L
●
●
• It is possible to input the signals from the ROMXA (pin 44), C2F (pin 45), LRSY (pin 42), and CK2 (pin 43) pins
to an antishock LSI (the Sanyo LC89151) and re-input the signals output by the antishock LSI to the ASDFIN (pin
39), ASLRCK (pin 41), and ASDACK (pin 38) pins. These signals are then processed by the attenuator, 8x
oversampling digital filter, and one-bit D/A converter circuits and output as audio signals.
• In antishock systems, the signal-processing block must operate in double-speed playback mode for data output to
the antishock LSI, and the audio playback block (the attenuator, 8x oversampling digital filter, and one-bit D/A
converter circuits) must operate at normal speed. This means that the control microprocessor must issue both the
ANTIC on command ($6C) as well as the DF normal speed on command ($6F).
• The ANTIC off command ($6B) clears antishock mode.
No. 5502-26/35
LC78625E
Note that the LC78625E adds a general-purpose I/O port function that shares the ASDACK, ASDFIN, ASDEPC, and
ASLRCK pins. Applications that use the LC78625E with antishock mode turned on must set the P0 (ASDACK), P1
(ASDFIN), P2 (ASDEPC), and P3 (ASLRCK) pins to input mode by issuing a port I/O switching command
($DB0x). But in this case,Pins P0 to P3 cannot be used as input pins. In the default state following a reset, the pins P0
to P3 are set up to be input ports. The only data that can be handled by this circuit as a digital data input interface in
antishock mode is data that has a 48fs bit clock rate, a 16-bit data length, an MSB-first format, and a back-packed
format. The figure below shows the timing.
23. General-purpose I/O ports; Pin 38: P0, pin 39: P1, pin 40: P2, pin 41: P3
When antichock mode is not used, pins 38 to 41 can be used as the general-purpose I/O ports P0 to P3. After a reset,
all these pins are set up as input ports. Unused ports must be either left set up as input ports and connected to 0 V or
set up as output ports and left open.
Code
COMMAND
$DD
PORT READ
$DB
PORT I/O SET
$DC
PORT OUTPUT
RES = L
PORT I SET
The port data can be read out in the order P0, P1, P2, and then P3 from the SQOUT pin is synchronization with
falling edges on the CQCK pin by issuing a PORT READ command. This command has the one-byte command
format.
Another point here is that these pins can be independently set to be used as control output pins with the PORT I/O set
command. The ports are selected with the lower 4 bits of the one byte of data. The one byte of data corresponds to
P0, P1, P2, and P3 starting with the low order bit. This command has the two-byte command format (RWC set once).
One byte data + $DB
PORT I/O SET
dn = 1 ... Sets Pn to be an output pin.
dn = 0 ... Sets Pn to be an input pin.
n = 0 to 3
Ports set up to be output pins can be independently set to output either a high or low level. The low order 4 bits of the
one byte of data correspond to those ports. The one byte of data corresponds to P0, P1, P2, and P3 starting with the
low-order bit. This command has the two-byte command format (RWC set once).
One byte data + $DC
PORT I/O SET
dn = 1 ... Outputs a high level from Pn, which is set up for output.
dn = 0 ... Outputs a low level from Pn, which is set up for output.
No. 5502-27/35
LC78625E
24. CONT pin; Pin 73: CONT
Code
COMMAND
$0E
CONT Set
RES = L
L
$8B
CONT and CD-ROM XA reset
●
The CONT pin goes high when a CONT SET command is issued.
25. Clock oscillator; Pin 77: XIN, pin 78: XOUT
Code
COMMAND
RES = L
$8E
OSC ON
●
$8D
OSC OFF
$CE
XTAL 16M
●
$C2
Normal-speed playback
●
$C1
Double-speed playback
The clock that is used as the time base is generated by connecting a 16.9344 MHz oscillator element between these
pins. The OSC OFF command turns off both the VCO and crystal oscillators. Double-speed playback can be
specified by microprocessor command.
• Connect a 16.9344 MHz oscillator element between the XIN (pin 77) and XOUT (pin 78) pins for double-speed
systems. The playback speed can be set by the normal-speed playback and double-speed playback commands.
• Recommended crystal and ceramic oscillator elements
Manufacturer
Product No.
Load capacitance
Cin/Cout (Cin = Cout)
Damping resistor
Rd
Citizen Watch Co., Ltd.
(crystal oscillator elements)
CSA-309 (16.9344 MHz)
6 pF to 10 pF (±10%)
0Ω
FCR 16.93M2G (16.93 MHz)
15 pF (±10%)
100 Ω (±10%)
FCR 16.93MCG (16.93 MHz)
30 pF (Built-in capacitor type)
47 Ω (±10%)
TDK, Ltd.
(ceramic oscillator elements)
Since the conditions for the load capacitors Cin and Cout used vary with the printed circuit board, this circuit must be
tested on the printed circuit board actually used.
26. 16M and 4.2M pins; Pin 71: 16M, pin 72: 4.2M
In normal- and double-speed playback modes, the 16M pin buffer outputs the 16.9344 MHz external crystal oscillator
16.9344 MHz signal. The 4.2M pin supplies an LA9230/40 Series LSI system clock, continuously outputting a
4.2336 MHz signal. When the oscillator is turned off both these pins will be fixed at either high or low.
No. 5502-28/35
LC78625E
27. Reset circuit; Pin 68: RES
When power is first applied, this pin should be briefly set low and then set high. This will set the muting to –∞ dB
and stop the disc motor.
CLV servo related
START
STOP
BRAKE
0 dB
–12 dB
–∞
Address 1
Address Free
ON (L)
OFF (H)
H
L
Track jump mode
Previous
New
Track count mode
Previous
New
Digital attenuator
DATA 0
DATA 00H to EEH
ON
OFF
Playback speed
Normal speed
Double speed
Antishock mode
ON
OFF
Digital filter normal speed
ON
OFF
Muting control
Subcode Q address condition
Laser control
CONT
OSC
Note:
CLV
Setting the RES pin low sets the LC78625E to the settings enclosed in boxes in the table.
28. Sound output function for set adjustment during manufacturing; Pin 30: DEMO
The DEMO pin can be used when the LC78625E is used in combination with an LA9210M or LA9211M.
By setting this pin high, muting can be set to 0 dB, the disc motor can be set to CLV, and a focus start operation can
be performed, even without issuing any commands from the control microprocessor. Also, since the LASER pin
becomes active, if the mechanism and servo systems are complete, an EFM signal can be acquired with only this
equipment, and an audio signal can be produced without the presence of a microprocessor. However, since the digital
attenuation is set to 100H, this technique is not appropriate for evaluating audio quality.
No. 5502-29/35
LC78625E
29. Other pins; Pin 2:TAI, pin 80: TEST1, pin 12: TEST2, pin 26: TEST3, pin 31: TEST4, pin 74: TEST5
These pins are used for testing the LSI's internal circuits. Although the pins TAI and TEST1 to TEST5 have built-in
pull-down resistors, they should be connected to ground (0 V) for safety.
30. Circuit Block Operating Descriptions
• RAM address control
The LC78625E incorporates an 8-bit × 2k-word RAM on chip. This RAM has an EFM demodulated data jitter
handling capacity of ±4 frames implemented using address control. The LC78625E continuously checks the remaining
buffer capacity and controls the data write address to fall in the center of the buffer capacity by making fine
adjustments to the frequency divisor in the PCK side of the CLV servo circuit. If the ±4 frame buffer capacity is
exceeded, the LC78625E forcibly sets the write address to the ±0 position. However, since the errors that occur due to
this operation cannot be handled with error flag processing, the IC applies muting to the output for a 128 frame period.
Position
–4 or lower
Divisor or Handling
Forcibly moves to ±0
–3
589
–2
589
–1
589
±0
588
+1
587
+2
587
+3
587
+4 or greater
Advancing divisors
Standard divisor
Decreasing divisors
Forcibly moves to ±0
• C1 and C2 error correction
The LC78625E writes EFM demodulated data to internal RAM to compensate for jitter and then performs the
following processing with uniform timing based on the crystal oscillator clock. First, the LC78625E performs C1 error
checking and correction in the C1 block, determines the C1 flags, and writes the C1 flag register. Next, the LC78625E
performs C2 error checking and correction in the C2 block, determines the C2 flags, and writes data to internal RAM.
C1 Check
Correction and Flag Processing
No errors
Correction not required · flags cleared
Single error
Correction performed · flags cleared
Dual errors
Correction performed · flags set
Three or more errors
Correction not possible · flags set
C2 Check
Correction and Flag Processing
No errors
Correction not required · flags cleared
Single error
Correction performed · flags cleared
Dual errors
C1 flags referenced. Note 1
Three or more errors
C1 flags referenced. Note 2
Note: 1. If the positions of the errors determined by the C2 check agree with the those specified by the C1 flags, the correction is performed and the flags
are cleared. However, if the number of C1 flags is 7 or higher, C2 correction may fail. In this case correction is not performed and the C1 flags are
taken as the C2 flags without change. Error correction is not possible if one error position agrees and the other does not. Furthermore, if the
number of C1 flags is 5 or under, the C1 check result can be seen as unreliable. Accordingly, the flags will be set in this case. Cases where the
number of C1 flags is 6 or more are handled in the same way, and the C1 flags are taken as the C2 flags without change. When there is not even
one agreement between the error positions, error correction is, of course, impossible. Here, if the number of C1 flags was 2 or under, data that
was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases, the C1 flags are taken as the
C2 flags without change.
2. When data is determined to have three or more errors and be uncorrectable, correction is, of course, impossible. Here, if the number of C1 flags
was 2 or under, data that was seen as correct after C1 correction is now seen as incorrect data. The flags are set in this case. In other cases the
C1 flags are taken as the C2 flags without change.
No. 5502-30/35
LC78625E
Command Summary Table
Blank entry: Illegal command, #: Command added since or changed from the LC78620/1E specifications,
★: Latching commands (mode setting commands), ●: Commands shared with an ASP (LA9230M/31M or other
processor),
Items in parentheses are ASP commands (provided for reference purposes)
$00
(ADJ. RESET)
$20
★TJ TOFF “L”
$40
★UBIT ON
$60
$01
★MUTE 0 dB
$21
★TJ TOFF “H”
$41
★UBIT OFF
$61
$02
★MUTE –12 dB
$22
★New TRACK COUNT
$42
★DOUT ON
$62
$03
★MUTE –∞dB
$23
★Old TRACK COUNT
$43
★DOUT OFF
$63
$04
★DISC MTR START
$24
$44
$64
$05
★DISC MTR CLV
$25
$45
$65
$06
★DISC MTR BRAKE
$26
$46
$66
$07
★DISC MTR STOP
$27
$47
$67
$08
● FOCUS START #1
$28
★STO CONT
$48
$68
$09
★ADDRESS FREE
$29
★LCH CONT
$49
$69
$0A
★LASER ON
$2A
★RCH CONT
$4A
$6A
$0B
$2B
★PKM SET
$4B
$6B
★ANTIC “OFF”
$0C
$2C
★LVM SET
$4C
$6C
★ANTIC “ON”
$0D
$2D
★PKM MSK SET
$4D
$6D
★PKM MSK RESET
$4E
$6E
★DF normal speed off
$4F
$6F
★DF normal speed on
$50
$70
$0E
★CONT SET
$2E
$0F
★TRACKING OFF
$2F
$10
2TJ IN
$30
32TJ IN
$11
1TJ IN
#1
$31
1TJ IN
$12
1TJ IN
#2
$32
$52
$13
4TJ IN
$33
$53
$73
$14
16TJ IN
$34
$54
$74
$15
64TJ IN
$35
$55
$75
$56
$76
$57
$77
$58
$78
$16
256TC
$36
$17
128TJ IN
$37
$18
2TJ OUT
$38
$19
1TJ OUT #1
$39
$1A
1TJ OUT #2
$3A
#3
32TJ OUT
1TJ OUT #3
$51
$71
1TJ IN
#4
$59
$5A
$72
$79
1TJ OUT #4
$7A
$1B
4TJ OUT
$3B
$5B
$7B
$1C
16TJ OUT
$3C
$5C
$7C
$1D
64TJ OUT
$3D
$5D
$7D
$3E
$5E
$7E
$3F
$5F
$7F
$1E
$1F
128TJ OUT
Continued on next page.
No. 5502-31/35
LC78625E
Continued from preceding page.
$80
*
$A0
★Old TRACK JMP
$C0
$81
★ATT DATA SET
$A1
★New TRACK JMP
$C1
★Double speed
$E1
$82
★ATT 4STP UP
$A2
FOCS START #2
$C2
★Normal speed
$E2
$83
★ATT 4STP DWN
$A3
$84
★ATT 8STP UP
$A4
$C4
★Internal BRK OFF
$E4
$85
★ATT 8STP DWN
$A5
$C5
★Internal BRK ON
$E5
$86
★ATT 16STP UP
$A6
$C6
$87
★ATT 16STP DWN
$A7
$C7
$88
★CDROMXA
$A8
★DISC 8 SET
$C8
*
$89
★ADDRESS “1”
$A9
★DISC 12 SET
$C9
★CK2 polarity inverted
$E9
$8A
★LASER OFF
$AA
$CA
★Internal BRK-DMC “L”
$EA
$8B
★CONT, ROMXA RST
$AB
$CB
★Internal BRK-DMC “H”
$EB
$8C
TRACK JMP BRK
$AC
*PLL DIV OFF
$CC
★Internal BRK TOFF
$EC
*PLL DIV ON
★Internal BRKE CONT
$E0
$C3
$E3
$E6
$E7
$E8
$8D
★OSC OFF
$AD
$CD
★Internal BRK TON
$ED
$8E
★OSC ON
$AE
$CE
★XTAL
$EE
★Command noise off
$8F
★TRACKING ON
$AF
$CF
*
$EF
★Command noise on
$90
(★F. OFF. ADJ. ST)
$B0
★CLV-PH 1/1 mode
$D0
$F0
★●
● TRACK CHECK IN
(2BYTE DETECT)
$91
(★F. OFF. ADJ. OFF)
$B1
★CLV-PH 1/2 mode
$D1
$F1
$92
(★T. OFF. ADJ. ST)
$B2
★CLV-PH 1/4 mode
$D2
$F2
$93
(★T. OFF. ADj. OFF)
$B3
★CLV-PH 1/8 mode
$D3
$F3
$94
(★LSR. ON)
$B4
★CLV3ST output ON
$D4
$F4
$95
(★LSR. OF/F. SV. ON)
$B5
★CLV3ST output OFF
$D5
$F5
$96
(★LSR. OF/F. SV. OF)
$B6
★JP3ST output ON
$D6
$F6
*No C period set for 2TJ mode
$97
(★SP. 8CM)
$B7
★JP3ST output OFF
$D7
$F7
*C period present set for 2TJ mode
$98
(★SP. 12CM)
$B8
$D8
$F8
★●
● TRACK CHECK OUT
(2BYTE DETECT)
$99
(★SP. OFF)
$B9
$D9
$F9
$9A
(★SLED. ON)
$BA
$DA
$FA
$9B
(★SLED. OFF)
$BB
$DB
*PORT OP-ED SET
$FB
$9C
(★EF. BAL. START)
$BC
$DC
*PORT DATA SET
$FC
$9D
(★T. SERVO. OFF)
$BD
$DD
$FD
$9E
(★T. SERVO. ON)
$BE
$DE
$FE
● NOTHING
$BF
$DF
$FF
★●
● 2BYTE CMD RST
$9F
Note: $AC is a supplementary command for low-voltage operation.
No. 5502-32/35
LC78625E
Sample Application Circuit
No. 5502-33/35
LC78625E
Differences between the LC78625E and the LC78620E
LC78625E
Item
Content of change
Bilingual processing for antishock input data is now possible in
antishock mode. The same bilingual control commands as those used in
the LC78620E are used.
Bilingual function
(Command code)
(Command mode)
$28:
Stereo output (Initial state after a reset)
$29:
Both left and right are output to the left channel
$2A:
Both left and right are output to the right channel
LC78620E
A bilingual processing function is not
provided for antishock input data in antishock
mode.
The de-emphasis filters are turned on or off by the input level on the
ASDEPC/P2 pin in antishock mode.
De-emphasis function
(ASDEPC/P2)
(De-emphasis filter)
High level applied: On
The on/off state of the de-emphasis filter
cannot be controlled from an external pin.
Low level applied: Off
A command was added that allows the presence or absence of a
braking period (the C period) to be selected during two-track jumps
(new track jump mode only).
Track jump function
(Command code)
(C period)
$F6:
None (Initial state after a reset)
$F7:
Present (60 ms)
There is no C period during two-track jumps
(in new track jump mode).
When antishock mode is not used, the antishock input pins can be used
as general-purpose I/O pins. To support this functionality, the pin names
were changed and commands were added. (These command codes are
identical to those on the LC78622E.)
· Pin name changes:
(LC78625E)
ASDACK/P0
ASDFIN/P1
ASDEPC/P2
ADLRCK/P3
General-purpose ports added
←
←
←
←
(LC78620E)
ASDACK
ASDFIN
ASDFIR
ASLRCK
· Added commands:
There are no general-purpose ports.
$DB0X: I/O switching command (2 bytes)
$DC0Y: Port output data setup command (2 bytes)
$DD: Port input command (1 byte)
Here X and Y represent 4-bit data items that control P0, P1, P2, and P3
in order starting with the low order bit.
X: A zero specifies input and a one specifies output.
(These pins default to input after a reset.)
Y: A zero specifies a low-level output, and a one specifies a high-level
output.
VCO circuit
The frequency range was increased over that supported by the
LC78620E. (The range is identical to that of the LC78622E)
This resulted in a change in the value of the resistor used on the FR pin:
1.2 kΩ.
A 5.1 kΩ resistor is connected to the FR pin.
Addition of a supplementary command for low-voltage operation.
PLL circuit
$AC: PLL DIVIDER OFF (Low-voltage operation supplementary
command)
No such commands are supported.
$AD: PLL DIVIDER ON (Initial state after a reset)
No. 5502-34/35
LC78625E
CD Digital Signal Processor LSI Functional Comparison
Type No.
LC7860KA
Function
EFM-PLL
LC7861NE→
LC7861KE
LC7867E
LC7868E→
LC7868KE
LC7869E
LC78681E→
LC78681KE
When used along When used along When used along When used along When used along When used along
with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP. with an analog ASP.
LC78620E
LC78621E
LC78625E
Built-in VCO
External
●
●
●
●
●
●
Digital outputs
×
●
●
●
●
●
●
Interpolation
2
4
4
4
4
4
4
Zero cross muting
×
●
●
●
●
●
●
Level meter peak search
×
×
×
●
●
●
●
Bilingual function
×
×
×
●
●
●
●
Digital attenuator
×
×
×
×
×
×
●
2 fs
●
●
—
—
—
—
—
4 fs
—
—
—
●
—
—
—
8 fs
—
—
—
—
●
—
●
Digital de-emphasis
×
×
×
●
●
×
●
One-bit D/A converter
×
×
×
×
×
×
●
16KRAM
■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
■ Anyone purchasing any products described or contained herein for an above-mentioned use shall:
➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of February, 1997. Specifications and information herein are subject to
change without notice.
No. 5502-35/35