STMICROELECTRONICS 74LVX594MTR

74LVX594
LOW VOLTAGE CMOS 8 BIT SHIFT REGISTER
WITH OUTPUT REGISTER (5V TOLERANT INPUTS)
■
■
■
■
■
■
■
■
■
■
■
HIGH SPEED:
tPD = 5.5ns (TYP.) at VCC = 3.3V
5V TOLERANT INPUTS
INPUT VOLTAGE LEVEL:
VIL=0.8V, VIH=2V at VCC=3V
LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 594
IMPROVED LATCH-UP IMMUNITY
POWER DOWN PROTECTION ON INPUTS
DESCRIPTION
The 74LVX594 is a low voltage CMOS 8 BIT
SHIFT REGISTER WITH OUTPUT REGISTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power, battery operated and low
noise 3.3V applications.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding
clear (SCLR, RCLR) are provided for both the shift
SOP
TSSOP
Table 1: Order Codes
PACKAGE
T&R
SOP
TSSOP
74LVX594MTR
74LVX594TTR
register and the storage register. A serial (QH’)
output is provided for cascading purposes. Both
the shift register and storage register use
positive-edge triggered clocks. If the clocks are
connected together, the shift register state will
always be one clock pulse ahead of the storage
register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V system. It combines
high speed performance with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
August 2004
Rev. 5
1/14
74LVX594
Figure 2: Input Equivalent Circuit
Table 2: Pin Description
PIN N°
SYMBOL
1, 2, 3, 4, 5,
6, 7, 15
9
10
11
13
QA to QH
14
12
SI
RCK
8
16
GND
VCC
QH’
SCLR
SCK
RCLR
NAME AND FUNCTION
Data Outputs
Serial Data Output
Shift Register Clear Input
Shift Register Clock Input
Storage Register Clear
Input
Serial Data Input
Storage Register Clock
Input
Ground (0V)
Positive Supply Voltage
Table 3: Truth Table
INPUTS
OUTPUTS
SI
SCK
SCLR
RCK
RCLR
X
X
L
X
X
L
H
X
X
H
H
X
X
L
H
X
X
SHIFT REGISTER STATE IS NOT CHANGED
X
X
X
X
L
X
X
X
H
STORAGE REGISTER IS CLEARED
SHIFT REGISTER DATA IS STORED IN THE
STORAGE REGISTER
X
X
X
H
X : Don’t Care
2/14
SHIFT REGISTER IS CLEAR
FIRST STAGE OF SHIFT REGISTER GOES LOW
OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
FIRST STAGE OF SHIFT REGISTER GOES HIGH
OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY
STORAGE REGISTER STATE IS NOT CHANGED
74LVX594
Figure 3: Logic Diagram
This logic diagram has not be used to estimate propagation delays
3/14
74LVX594
Figure 4: Timing Chart
Table 4: Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
- 20
mA
IOK
DC Output Diode Current
± 20
mA
IO
DC Output Current
ICC or IGND DC VCC or Ground Current
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 25
mA
± 50
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
4/14
74LVX594
Table 5: Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage (note 1)
Value
Unit
2 to 3.6
V
VI
Input Voltage
0 to 5.5
V
VO
Output Voltage
0 to VCC
V
Top
Operating Temperature
dt/dv
Input Rise and Fall Time (note 2) (VCC = 3.3V)
-55 to 125
°C
0 to 100
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) VIN from 0.8V to 2.0V
Table 6: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
VOL
II
Ioff
ICC
Parameter
TA = 25°C
VCC
(V)
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage
Current
Power Off Leakage
Current
Quiescent Supply
Current
Value
Min.
2.0
3.0
3.6
2.0
3.0
3.6
Typ.
Max.
1.5
2.0
2.4
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
1.5
2.0
2.4
0.5
0.8
0.8
2.0
IO=-50 µA
1.9
2.0
1.9
1.9
IO=-50 µA
2.9
3.0
2.9
2.9
3.0
IO=-4 mA
2.58
2.0
IO=50 µA
0.0
0.0
2.48
V
0.5
0.8
0.8
3.0
0.1
Max.
1.5
2.0
2.4
0.5
0.8
0.8
Unit
V
V
2.4
0.1
0.1
3.0
IO=50 µA
0.1
0.1
0.1
3.0
IO=4 mA
0.36
0.44
0.55
3.6
VI = 5V or GND
± 0.1
±1
±1
µA
0
VI = 0 to 5V
± 0.1
±5
±5
µA
3.6
VI = VCC or GND
4
40
40
µA
V
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
VOLP
VOLV
VIHD
VILD
Parameter
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
TA = 25°C
VCC
(V)
3.3
3.3
3.3
Value
CL = 50 pF
Min.
Typ.
Max.
0.3
0.5
-0.5
-0.3
2
-40 to 85°C
-55 to 125°C
Min.
Min.
Max.
Unit
Max.
V
0.8
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n-1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold
(VIHD), f=1MHz.
5/14
74LVX594
Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
(RCK - Qn)
tPLH tPHL Propagation Delay
Time
(SCK - QH’)
tPHL
Propagation Delay
Time
(RCLR - Qn)
tPLH tPHL Propagation Delay
Time
(SCLR - QH’)
fMAX
Maximum Clock
Frequency
tW(H)
Minimum Pulse
Width (SCK, RCK)
tW(L)
Minimum Pulse
Width
(SCLR,RCLR)
VCC
(V)
CL
(pF)
2.7
2.7
Max.
Min.
Max.
15
50
5.5
9.0
9.5
13.0
1.0
1.0
10.0
14.5
1.0
1.0
10.0
14.5
3.3(*)
15
4.9
8.2
1.0
8.8
1.0
8.8
3.3(*)
2.7
2.7
50
8.1
11.9
1.0
13.1
1.0
13.1
15
50
6.5
9.2
11.0
14.0
1.0
1.0
12.5
16.0
1.0
1.0
12.5
16.0
3.3(*)
15
5.5
9.2
1.0
9.9
1.0
9.9
3.3(*)
2.7
2.7
50
8.4
12.5
1.0
13.9
1.0
13.9
15
50
7.3
10.5
11.0
14.5
1.0
1.0
13.0
16.0
1.0
1.0
13.0
16.0
3.3(*)
15
6.0
9.8
1.0
10.6
1.0
10.6
3.3(*)
2.7
2.7
50
9.0
13.1
1.0
14.4
1.0
14.4
15
50
6.3
9.0
10.5
13.5
1.0
1.0
12.0
15.5
1.0
1.0
12.0
15.5
3.3(*)
15
5.6
9.2
1.0
10.0
1.0
10.0
3.3(*)
2.7
2.7
8.5
12.4
1.0
14.0
1.0
14.0
15
50
70
40
110
90
60
35
60
35
3.3(*)
15
80
120
70
70
3.3(*)
2.7
50
55
105
50
50
50
6.5
6.5
6.5
3.3(*)
2.7
50
5.5
5.5
5.5
50
5.0
5.0
5.0
3.3(*)
50
5.0
5.0
5.0
50
3.5
3.5
3.5
3.3
2.7
50
3.0
3.0
3.0
50
9.0
9.0
9.0
3.3(*)
2.7
50
85.
8.5
8.5
Minimum Set - Up
Time (SCK, RCK)
ts
Minimum Set - Up
Time (SCRL - RCK) 3.3(*)
2.7
Minimum Hold
Time
3.3(*)
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
50
(*)
ts
Minimum Clear
Removal Time
-55 to 125°C
Min.
2.7
Min.
-40 to 85°C
Max.
Minimum Set-Up
Time (SI - CCK)
tREM
TA = 25°C
Typ.
ts
th
Value
50
8.0
8.0
8.0
50
7.5
7.5
7.5
50
1.5
1.5
1.5
50
1.5
1.5
1.5
2.7
50
3.0
3.0
3.0
3.3(*)
50
3.0
3.0
3.0
2.7
50
(*)
3.3
50
0.5
0.5
1.0
1.0
1.5
1.5
Unit
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
1.5
1.5
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
6/14
74LVX594
Table 9: Capacitive Characteristics
Test Condition
Symbol
Parameter
CIN
Input Capacitance
COUT
Output
Capacitance
Power Dissipation
Capacitance
(note 1)
CPD
Value
TA = 25°C
VCC
(V)
-55 to 125°C
Min.
Min.
Max.
3.3
7
10
3.3
9
pF
55
pF
fIN = 10MHz
Max.
Unit
Typ.
3.3
Min.
-40 to 85°C
10
Max.
10
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
Figure 5: Test Circuit
CL =15/50pF or equivalent (includes jig and probe capacitance)
RT = ZOUT of pulse generator (typically 50Ω)
Figure 6: Waveform - Minimum Pulse Width (f=1MHz; 50% duty cycle)
7/14
74LVX594
Figure 7: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
8/14
74LVX594
SO-16 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
MIN.
TYP.
1.75
0.1
0.068
0.25
a2
MAX.
0.004
0.010
1.64
0.063
b
0.35
0.46
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.5
0.019
c1
45° (typ.)
D
9.8
10
0.385
0.393
E
5.8
6.2
0.228
0.244
e
1.27
e3
0.050
8.89
0.350
F
3.8
4.0
0.149
0.157
G
4.6
5.3
0.181
0.208
L
0.5
1.27
0.019
0.050
M
S
0.62
0.024
8° (max.)
0016020D
9/14
74LVX594
TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
A
MAX.
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
4.9
5
5.1
0.193
0.197
0.201
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.60
0.0256 BSC
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
10/14
74LVX594
Tape & Reel SO-16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
22.4
0.519
0.882
Ao
6.45
6.65
0.254
0.262
Bo
10.3
10.5
0.406
0.414
Ko
2.1
2.3
0.082
0.090
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
11/14
74LVX594
Tape & Reel TSSOP16 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
12/14
TYP
0.504
22.4
0.519
0.882
Ao
6.7
6.9
0.264
0.272
Bo
5.3
5.5
0.209
0.217
Ko
1.6
1.8
0.063
0.071
Po
3.9
4.1
0.153
0.161
P
7.9
8.1
0.311
0.319
74LVX594
Table 10: Revision History
Date
Revision
27-Aug-2004
5
Description of Changes
Ordering Codes Revision - pag. 1.
13/14
74LVX594
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners
© 2004 STMicroelectronics - All Rights Reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
14/14