M54HC595 RAD-HARD 8 BIT SHIFT REGISTER WITH OUTPUT LATCHES (3 STATE) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: fMAX = 59MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 6mA (MIN.) FOR QA to QH |IOH| = IOL = 4mA (MIN.) FOR QH’ BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 54 SERIES 595 SPACE GRADE-1: ESA SCC QUALIFIED 50 krad QUALIFIED, 100 krad AVAILABLE ON REQUEST NO SEL UNDER HIGH LET HEAVY IONS IRRADIATION DEVICE FULLY COMPLIANT WITH SCC-9306-051 DESCRIPTION The M54HC595 is an high speed CMOS 8-BIT SHIFT REGISTERS/OUTPUT LATCHES (3-STATE) fabricated with silicon gate C2MOS technology. DILC-16 FPC-16 ORDER CODES PACKAGE FM EM DILC FPC M54HC595D M54HC595K M54HC595D1 M54HC595K1 This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has 8 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. All inputs are equipped with protection circuits against static discharge and transient excess voltage. PIN CONNECTION June 2004 Rev. 1 1/15 M54HC595 Figure 1: IEC Logic Symbols Figure 2: Input And Output Equivalent Circuit Table 1: Pin Description PIN N° SYMBOL 1, 2, 3, 4, 5, 6, 7, 15 9 10 11 13 14 12 QA to QH 8 16 GND VCC QH’ SCLR SCK G SI RCK NAME AND FUNCTION Data Outputs Serial Data Outputs Shift Register Clear Input Shift Register Clock Input Output Enable Input Serial Data Input Storage Register Clock Input Ground (0V) Positive Supply Voltage Table 2: Truth Table INPUTS OUTPUTS SI SCK SCLR RCK G X X X X X X X X L X X X H L X L H X X H H X X X H X X STATE OF S.R. IS NOT CHANGED X X X X S.R. DATA IS STORED INTO STORAGE REGISTER X X X X STORAGE REGISTER STATE IS NOT CHANGED X: Don’t Care 2/15 QA THRU QH OUTPUTS DISABLE QA THRU QH OUTPUTS ENABLE SHIFT REGISTER IS CLEARED FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY M54HC595 Figure 3: Logic Diagram This logic diagram has not be used to estimate propagation delays Figure 4: Logic Diagram Table 5: This logic diagram has not be used to estimate propagation delays 3/15 M54HC595 Figure 6: Timing Chart Table 3: Absolute Maximum Ratings Symbol VCC Parameter Supply Voltage Value Unit -0.5 to +7 V VI DC Input Voltage -0.5 to VCC + 0.5 V VO DC Output Voltage -0.5 to VCC + 0.5 ± 20 V mA IIK DC Input Diode Current IOK DC Output Diode Current ± 20 mA IO DC Output Current ± 35 mA ± 70 mA 420 mW -65 to +150 °C 265 °C ICC or IGND DC VCC or Ground Current PD Power Dissipation Tstg Storage Temperature TL Lead Temperature (10 sec) Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 4/15 M54HC595 Table 4: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage Value Unit 2 to 6 V VI Input Voltage 0 to VCC V VO Output Voltage 0 to VCC V Top Operating Temperature Input Rise and Fall Time tr, tf -55 to 125 °C VCC = 2.0V 0 to 1000 ns VCC = 4.5V 0 to 500 ns VCC = 6.0V 0 to 400 ns Table 5: DC Specifications Test Condition Symbol VIH VIL VOH VOH VOL VOL II IOZ Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage (for QH’ outputs) High Level Output Voltage (for QA to QH outputs) Low Level Output Voltage (for QH’ outputs) Low Level Output Voltage (for QA to QH outputs) Input Leakage Current High Impedance Output Leakage Current Value TA = 25°C VCC (V) Min. 2.0 4.5 6.0 2.0 4.5 6.0 Typ. Max. 1.5 3.15 4.2 -40 to 85°C -55 to 125°C Min. Min. Max. 1.5 3.15 4.2 0.5 1.35 1.8 Max. 1.5 3.15 4.2 0.5 1.35 1.8 V 0.5 1.35 1.8 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-4.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-7.8 mA 5.68 5.8 5.63 5.60 2.0 IO=-20 µA 1.9 2.0 1.9 1.9 4.5 IO=-20 µA 4.4 4.5 4.4 4.4 6.0 IO=-20 µA 5.9 6.0 5.9 5.9 4.5 IO=-6.0 mA 4.18 4.31 4.13 4.10 6.0 IO=-7.8 mA 5.68 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=4.0 mA 0.17 0.26 0.33 0.40 6.0 IO=7.8 mA 0.18 0.26 0.33 0.40 2.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=20 µA 0.0 0.1 0.1 0.1 5.8 5.63 Unit V V V 5.60 V 6.0 IO=20 µA 0.0 0.1 0.1 0.1 4.5 IO=6.0 mA 0.17 0.26 0.33 0.40 6.0 IO=7.8 mA 0.18 0.26 0.33 0.40 6.0 VI = VCC or GND ± 0.1 ±1 ±1 µA 6.0 VI = VIH or VIL VO = VCC or GND ± 0.5 ±5 ± 10 µA V 5/15 M54HC595 Test Condition Symbol ICC Parameter Quiescent Supply Current TA = 25°C VCC (V) 6.0 Value Min. Typ. Max. VI = VCC or GND -40 to 85°C -55 to 125°C Min. Min. 4 Max. 40 Unit Max. 80 µA Table 6: AC Electrical Characteristics (CL = 50 pF, Input tr = tf = 6ns) Test Condition Symbol Parameter tTLH tTHL Output Transition Time (Qn) tTLH tTHL Output Transition Time (QH’) tPLH tPHL Propagation Delay Time (SCK - QH’) tPLH tPHL Propagation Delay Time (SCLR - QH’) tPLH tPHL Propagation Delay Time (RCK - Qn) tPZL tPZH High Impedance Output Enable Time tPLZ tPHZ High Impedance Output Disable Time fMAX tW(H) 6/15 Maximum Clock Frequency Minimum Pulse Width (SCK, RCK) VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Value TA = 25°C CL (pF) Min. 50 50 50 50 50 150 50 RL = 1 KΩ 150 RL = 1 KΩ 50 RL = 1 KΩ 50 150 50 6.0 30 35 5.2 26 31 Typ. Max. 25 7 6 30 8 7 45 15 13 60 18 15 60 20 17 75 25 22 45 15 13 60 20 17 30 15 14 17 50 59 14 40 45 17 6 6 60 12 10 75 15 13 125 25 21 175 35 30 150 30 26 190 38 32 135 27 23 175 35 30 150 30 26 -40 to 85°C -55 to 125°C Min. Min. Max. 75 15 13 95 19 16 155 31 26 220 44 37 190 38 32 240 48 41 170 34 29 220 44 37 190 38 32 4.8 24 28 4.2 21 25 75 15 13 Max. 90 18 15 115 23 20 190 38 32 265 53 45 225 45 38 285 57 48 205 41 35 265 53 45 225 45 38 4 20 24 3.4 17 20 95 19 16 Unit ns ns ns ns ns ns ns ns ns MHz MHz 110 22 19 ns M54HC595 Test Condition Symbol tW(L) ts ts ts th tREM Parameter Minimum Pulse Width (SCLR) Minimum Set-up Time (SI - CCK) Minimum Set-up Time (SCK - RCK) Minimum Set-up Time (SCRL - RCK) Minimum Hold Time Minimum Clear Removal Time VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 CL (pF) Value TA = 25°C Min. 50 50 50 50 Typ. Max. 20 6 6 25 5 4 35 8 6 40 10 7 75 15 13 50 10 9 75 15 13 100 20 17 0 0 0 50 10 9 50 15 3 3 50 -40 to 85°C -55 to 125°C Min. Min. Max. 95 19 16 65 13 11 95 19 16 125 25 21 0 0 0 65 13 11 Unit Max. 110 22 19 75 15 13 110 22 19 145 29 25 0 0 0 75 15 13 ns ns ns ns ns ns Table 7: Capacitive Characteristics Test Condition Symbol Parameter VCC (V) Value TA = 25°C Min. Typ. Max. 10 CIN Input Capacitance 5 CPD Power Dissipation Capacitance (note 1) 184 -40 to 85°C -55 to 125°C Min. Min. Max. 10 Unit Max. 10 pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC 7/15 M54HC595 Figure 7: Test Circuit TEST tPLH, tPHL SWITCH Open tPZL, tPLZ VCC tPZH, tPHZ GND CL = 50pF/150pF or equivalent (includes jig and probe capacitance) R1 = 1KΩ or equivalent RT = ZOUT of pulse generator (typically 50Ω) Figure 8: Waveform - SCK To QH’ Propagation Delay Times, SCK Minimum Pulse Width (f=1MHz; 50% duty cycle) 8/15 M54HC595 Figure 9: Waveform - RCK To Qn Propagation Delay Times (f=1MHz; 50% duty cycle) Figure 10: Waveform - SI To SCK Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 11: Waveform - SCK To RCK Setup And Hold Times (f=1MHz; 50% duty cycle) 9/15 M54HC595 Figure 12: Waveform - SCLR Minimum Pulse Width, Minimum Removal Time (f=1MHz; 50% duty cycle) Figure 13: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 10/15 M54HC595 Figure 14: Waveform - Input Waveform (f=1MHz; 50% duty cycle) 11/15 M54HC595 DILC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 2.1 2.71 0.083 0.107 a1 3.00 3.70 0.118 0.146 a2 0.63 1.14 0.025 B 1.82 2.39 0.072 b 0.40 0.45 0.50 0.016 0.018 0.020 b1 0.20 0.254 0.30 0.008 0.010 0.012 D 20.06 20.32 20.58 0.790 0.800 0.810 E 7.36 7.62 7.87 0.290 0.300 0.310 e 0.88 2.54 0.035 0.045 0.094 0.100 e1 17.65 17.78 17.90 0.695 0.700 0.705 e2 7.62 7.87 8.12 0.300 0.310 0.320 F 7.29 7.49 7.70 0.287 0.295 0.303 I 3.83 0.151 K 10.90 12.1 0.429 0.476 L 1.14 1.5 0.045 0.059 0056437F 12/15 M54HC595 FPC-16 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. MIN. TYP. MAX. A 6.75 6.91 7.06 0.266 0.272 0.278 B 9.76 9.94 10.14 0.384 0.392 0.399 C 1.49 1.95 0.059 D 0.102 0.127 0.152 0.004 0.005 0.006 E 8.76 8.89 9.01 0.345 0.350 0.355 F 0.077 1.27 G 0.38 H 6.0 L 18.75 M 0.33 0.050 0.43 0.48 0.015 0.017 0.019 0.237 0.38 N 22.0 0.738 0.43 0.013 0.867 0.015 4.31 0.017 0.170 G F D H 9 16 A N L 8 1 H E B M C 0016030E 13/15 M54HC595 Table 8: Revision History Date Revision 01-Jun-2004 1 14/15 Description of Changes First Release M54HC595 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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