CM17699 COLOR PDP DRIVER MODULE PRODUCT PREVIEW CM17699 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 CM17699 CONNECTORS DEFINITION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 2.2 SIGNAL CONNECTOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . POWER SUPPLY CONNECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 3 CM17699 SCHEMATIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3.1 DETAILS OF DIE BONDING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 PCB MECHANICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 FPC MECHANICAL SPECIFICATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 STV7699 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.1 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 6.3 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PAD DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 6.4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.5 6.6 6.6.1 6.6.2 6.6.3 6.6.4 6.7 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timings Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timings Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 8 8 9 9 11 CM17699.TIF 1 January 1999 This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/11 CM17699 The CM17699 is plasma Display Panel (PDP) data driver board implementing 5 data drivers referenced STV7699. This module addresses 320 column electrodes of a plasma panel. The monoblock structure of this module and the output Flexible Printed Circuit (FPC) realizes a high density package for data drivers ICs. This module is adapted to standard definition large size PDPs. The bidirectional feature of this module allows its implementation on the top side and/or bottom side of the panel without any modification in the data bit stream. 1 - CM17699 MAIN FEATURES - Equiped with five STV7699 devices - 4 x 16-bit bidirectional shift register - Mounted connectors/capacitors - Configurable for AC/DC power supply - FPC compatible with narrow pitches of column electrodes - Compatible with custom designs. Output Count Output Pitch Logic Power Supply Power Supply Voltage Power Output Current Clock Frequency Dimension 320 320mm 4.5V to 5.5V 30V to 160V ±40mA 20MHz COB - 92 x 33 FPC - 101.4 x 50 2 - CM17699 CONNECTORS DEFINITION 2.1 - Signal Connector Input signal connector is a 50 nodes high density connector defined as follow : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2/11 A14 A13 A12 A11 B11 B12 B13 B14 A24 A23 A22 A21 B21 B22 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 B23 B24 A34 A33 A32 A31 B31 B32 B33 B34 BLK VSS POL VSS F/R VSS STB VSS CLK VSS A44 A43 A42 A41 B41 B42 B43 B44 A54 A53 A52 A51 B51 B53 B53 B54 2.2 - Power Supply Connector Power supplies come from 2 connectors of 3 nodes each (VPP, VDD, VSS). The use of both connectors is not necessary as all the supplies are connected together on the board. The use of both connectors spread the currents on the PC borad and reduce the EMI radiations. Depending on the application, the data module can be configured either for DC supplies or for AC supplies of the data drivers by the implementation of surface mounted devices. CM17699 3 - CM17699 SCHEMATIC Decoupling capacitors must be located as close as possible to the drivers. If the damping and protection resistor in VPP line of each driver is different to 0Ω, the decoupling capacitor should not be mounted. 01-7 01-6 01-5 01-4 01-3 01-2 01-1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT7 OUT6 OUT5 VSSP OUT4 OUT3 OUT2 OUT1 VPP 01-8 15 OUT8 01-9 16 OUT9 01-10 17 OUT10 01-11 18 OUT11 01-12 19 OUT12 01-13 01-14 20 VSSP 01-15 21 OUT13 01-16 01-17 22 OUT14 VPP1 04-25 31 OUT25 VCC 100 01-25 31 OUT25 VCC 100 04-26 32 OUT26 A41 A1 99 01-26 32 OUT26 A11 A1 99 04-27 33 OUT27 A42 A2 98 01-27 33 OUT27 A12 A2 98 04-28 34 OUT28 A43 A3 97 01-28 34 OUT28 A13 A3 97 35 VCC A44 A4 96 VSSP 35 CLK 95 01-29 36 OUT29 CLK 95 04-30 37 OUT30 ST STB 94 01-30 37 OUT30 ST STB 94 04-32 39 OUT32 40 VSSP 41 VSSSUB STV7699 (Die) VSSLOG 93 01-31 38 OUT31 VSSLOG 92 01-32 39 OUT32 VSSLOG 91 40 VSSP VSSLOG 90 41 VSSSUB VSSLOG 93 STV7699 (Die) VSSLOG 92 VSSLOG 91 VSSLOG 90 F/R F/R 89 01-33 42 OUT33 04-34 43 OUT34 BL BLK 88 01-34 43 OUT34 BL BLK 88 04-35 44 OUT35 PO POL 87 01-35 44 OUT35 PO POL 87 04-33 42 OUT33 04-36 45 OUT36 HIZ 86 VCC B44 B4 85 VSSP 04-38 48 OUT38 04-39 49 OUT39 04-40 50 OUT40 F/R F/R 89 01-36 45 OUT36 46 HIZ 86 01-37 47 OUT37 B42 B2 83 01-38 48 OUT38 B41 B1 82 01-39 49 OUT39 B13 B3 84 B12 B2 83 B11 B1 82 01-40 50 OUT40 OUT60 VSSP OUT61 OUT62 OUT63 OUT64 VPP 01-61 01-62 01-63 01-64 02-4 02-3 02-2 02-1 20 19 18 17 16 15 14 13 12 11 10 6 5 4 3 2 1 OUT5 VSSP OUT4 OUT3 OUT2 OUT1 VPP 01-60 OUT59 02-5 OUT58 01-59 OUT21 02-6 OUT22 21 OUT6 OUT23 22 OUT7 VPP VPP 01-58 VPP 02-7 OUT57 OUT1 23 OUT8 OUT2 01-57 OUT56 OUT3 24 OUT9 OUT4 02-8 OUT55 VSSP 25 01-56 OUT54 OUT5 26 02-9 OUT53 OUT6 27 01-55 OUT7 28 01-54 OUT8 29 02-10 OUT9 30 02-11 OUT10 VPP2 IC2 VPP5 OUT10 OUT11 TP5-1 OUT11 1 OUT12 2 01-53 VSSP 3 VSSP 4 OUT12 7 02-12 OUT52 5 VSSP 8 01-52 6 OUT13 9 OUT13 10 02-13 OUT51 11 OUT14 12 01-51 OUT50 13 02-14 OUT49 14 OUT15 15 OUT16 16 OUT17 17 OUT18 04-64 05-1 18 OUT19 04-63 05-2 19 TP4-2 VSSP 04-62 05-3 20 VPP1 OUT20 04-61 05-4 21 OUT14 OUT21 22 OUT15 OUT22 23 OUT16 OUT23 24 OUT17 25 OUT18 26 OUT19 27 VSSP 28 OUT20 29 VPP VPP 30 OUT24 VPP5 IC5 VPP4 01-50 80 02-15 79 01-49 OUT48 78 02-16 OUT47 77 01-48 OUT46 76 02-17 OUT45 75 01-47 VSSP 74 01-46 OUT44 73 02-18 OUT43 72 02-19 OUT42 71 01-45 OUT41 70 02-20 VPP 69 01-44 VPP 68 02-21 VPP 67 01-43 OUT64 66 01-42 OUT63 65 02-22 OUT62 64 02-23 OUT61 63 01-41 VSSP 62 02-24 OUT60 61 04-60 OUT59 60 05-5 OUT58 59 04-59 58 05-6 57 04-58 56 05-7 OUT57 55 04-57 OUT56 54 05-8 OUT55 53 04-56 OUT54 52 05-9 OUT53 51 04-55 80 04-54 79 05-10 78 05-11 77 04-53 VSSP 76 05-12 OUT52 75 04-52 74 05-13 OUT51 73 04-51 OUT50 72 05-14 OUT49 71 04-50 70 05-15 69 04-49 68 05-16 OUT48 67 04-48 OUT47 66 05-17 OUT46 65 04-47 64 04-46 63 05-18 OUT45 62 05-19 VSSP 61 04-45 60 05-20 OUT44 59 04-44 OUT43 58 05-21 OUT42 57 04-43 56 04-42 55 05-22 OUT41 54 05-23 VPP 53 04-41 52 05-24 51 VPP4 9 8 7 F/R ST VPP1 TP2-1 VPP2 VCC 100 02-25 31 OUT25 VCC 100 05-26 32 OUT26 A51 A1 99 02-26 32 OUT26 A21 A1 99 05-27 33 OUT27 A52 A2 98 02-27 33 OUT27 A22 A2 98 A53 A3 97 02-28 34 OUT28 05-28 34 OUT28 35 A54 A4 96 VSSP 35 A24 A4 96 CLK 95 02-29 36 OUT29 CLK 95 05-30 37 OUT30 ST STB 94 02-30 37 OUT30 ST STB 94 05-32 39 OUT32 40 VSSP 41 VSSSUB STV7699 (Die) VSSLOG 93 02-31 38 OUT31 VSSLOG 92 02-32 39 OUT32 VSSLOG 91 VSSLOG 90 40 VSSP 41 VSSSUB STV7699 (Die) F/R F/R 89 02-34 43 OUT34 BL BLK 88 05-35 44 OUT35 PO POL 87 02-35 44 OUT35 PO POL 87 B52 B2 83 02-38 48 OUT38 B51 B1 82 02-39 49 OUT39 VPP VPP2 C1-2 68nF OUT60 VSSP OUT61 OUT62 OUT63 OUT64 VPP 02-61 02-62 02-63 02-64 03-4 03-3 03-2 03-1 18 17 16 15 14 13 12 11 10 6 5 4 3 2 1 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 VSSP OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 VSSP OUT4 OUT3 OUT2 OUT1 VPP 02-60 OUT59 19 VSSP 03-5 OUT58 20 9 8 7 TP3-1 VPP3 VCC 100 03-26 32 OUT26 A31 A1 99 03-27 33 OUT27 A32 A2 98 A34 A4 96 CLK 95 03-30 37 OUT30 ST STB 94 40 VSSP 41 VSSSUB (not connect if R = 22W ) VSSLOG 93 VSSLOG 92 STV7699 (Die) VSSLOG 91 VSSLOG 90 F/R F/R 89 03-34 43 OUT34 BL BLK 88 03-35 44 OUT35 PO POL 87 03-36 45 OUT36 46 HIZ 86 B33 B3 84 03-38 48 OUT38 B32 B2 83 03-39 49 OUT39 B31 B1 82 03-40 50 OUT40 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 VSSP OUT61 OUT62 OUT63 OUT64 VPP 68 69 70 71 72 73 74 75 76 77 78 79 80 03-64 OUT53 67 03-63 VSSP 66 03-62 OUT52 65 03-61 OUT51 64 03-60 OUT50 63 03-59 OUT49 62 03-58 OUT48 61 03-57 OUT47 60 03-56 OUT46 59 03-55 OUT45 58 03-54 VSSP 57 03-53 OUT44 56 03-52 OUT43 55 03-51 OUT42 54 03-50 OUT41 53 03-49 VPP 52 03-48 VPP 51 03-47 VPP3 03-46 C5 100nF 03-45 C4 100nF 03-44 C3 100nF 03-43 C2 100nF 03-42 C1 100nF VSSSUB 81 03-41 VCC VCC B34 B4 85 VSSP 03-37 47 OUT37 (not connect if R = 22W ) VCC A33 A3 97 VSSP 03-29 36 OUT29 03-33 42 OUT33 VPP5 C1-5 68nF 21 03-32 39 OUT32 R5 0 or 22W VPP 22 03-31 38 OUT31 (not connect if R = 22W ) VPP4 C1-4 68nF 23 03-25 31 OUT25 35 R4 0 or 22W VPP 24 03-28 34 OUT28 VPP3 C1-3 68nF 25 VPP2 TP2-2 (not connect if R = 22W ) R3 0 or 22W VPP 26 OUT21 (not connect if R = 22W ) 27 OUT22 C1-1 68nF R2 0 or 22W 28 OUT23 VPP1 29 VPP VPP VPP 30 OUT24 VPP3 IC3 R1 0 or 22W 02-59 80 03-6 79 02-58 78 03-7 OUT57 77 02-57 OUT56 76 03-8 OUT55 75 02-56 OUT54 74 03-9 OUT53 73 02-55 72 02-54 71 03-10 70 03-11 69 02-53 VSSP 68 03-12 OUT52 67 02-52 66 03-13 OUT51 65 02-51 OUT50 64 03-14 OUT49 63 02-50 62 03-15 61 02-49 60 03-16 OUT48 59 02-48 OUT47 58 03-17 OUT46 57 02-47 56 02-46 55 03-18 OUT45 54 03-19 VSSP 53 02-45 52 03-20 OUT44 51 VPP2 OUT20 VPP5 TP5-2 02-44 80 03-21 VPP 79 OUT43 OUT64 78 B21 B1 82 OUT42 OUT63 77 VCC VSSSUB 81 02-43 OUT62 76 1 2 3 CON3 B22 B2 83 02-40 50 OUT40 02-42 OUT61 75 VPP B23 B3 84 03-22 VSSP 74 05-64 OUT60 73 05-63 OUT59 72 05-62 OUT58 71 05-61 OUT57 70 05-60 OUT56 69 05-59 OUT55 68 05-58 OUT54 67 05-57 OUT53 66 05-56 VSSP 65 05-55 OUT52 64 05-54 OUT51 63 05-53 OUT50 62 05-52 OUT49 61 05-51 OUT48 60 05-50 OUT47 59 05-49 OUT46 58 05-48 OUT45 57 05-47 VSSP 56 05-46 OUT44 55 05-45 OUT43 54 05-44 OUT42 53 05-43 OUT41 52 VPP4 05-42 VPP 51 05-41 VPP VSSSUB 81 VCC B24 B4 85 OUT41 05-40 50 OUT40 HIZ 86 VSSP VPP 05-39 49 OUT39 46 02-37 47 OUT37 VPP 05-38 48 OUT38 02-36 45 OUT36 B53 B3 84 03-23 VCC B54 B4 85 02-41 HIZ 86 VSSP 03-24 46 05-37 47 OUT37 J3 VSSLOG 90 BL BLK 88 1 2 3 CON3 VSSLOG 91 05-34 43 OUT34 05-36 45 OUT36 J2 VPP VSSLOG 92 02-33 42 OUT33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CON50 VCC VSSLOG 93 F/R F/R 89 05-33 42 OUT33 VCC A23 A3 97 VSSP 05-29 36 OUT29 05-31 38 OUT31 A44 A43 A42 A41 B41 B42 B43 B44 A54 A53 A52 A51 B51 B52 B53 B54 TP1-2 05-25 31 OUT25 VCC PO VSSSUB 81 VPP VSSSUB 81 VCC B14 B4 85 VSSP B43 B3 84 OUT24 46 04-37 47 OUT37 J1 A14 A13 A12 A11 B11 B12 B13 B14 A24 A23 A22 A21 B21 B22 B23 B24 A34 A33 A32 A31 B31 B32 B33 B34 BL A14 A4 96 VSSP 04-29 36 OUT29 04-31 38 OUT31 VCC 7699C-01.EPS VPP 23 OUT15 VPP TP1-1 24 OUT16 OUT1 25 01-18 OUT2 26 01-19 OUT3 27 OUT17 OUT4 28 01-20 VSSP 29 OUT18 OUT5 30 OUT19 OUT6 VPP1 IC1 VPP4 01-21 1 VSSP 2 OUT20 3 01-22 4 01-23 04-1 5 OUT21 04-2 6 01-24 04-3 7 OUT22 04-4 8 VPP 04-5 9 OUT23 04-6 10 OUT24 04-7 11 OUT7 04-8 12 OUT8 04-9 13 OUT9 04-10 14 OUT10 04-11 15 OUT11 04-12 16 OUT12 04-13 17 VSSP 04-14 18 OUT13 04-15 19 OUT14 04-16 20 OUT15 04-17 21 OUT16 04-18 04-19 22 OUT17 04-20 23 OUT18 OUT21 TP4-1 24 OUT19 25 OUT22 04-21 26 VSSP 27 OUT20 28 VPP 04-22 29 OUT23 VPP 30 OUT24 VPP4 IC4 04-23 04-24 Figure 1 VPP3 TP3-2 3/11 CM17699 3 - CM17699 SCHEMATIC (continued) 3.1 - Details of Die Bonding Figure 2 VCC Test Point Test Point VSS VPP VSSSUB B1 B2 B3 B4 HIZ POL BLK F/R VSSLOG VSSLOG STB CLK A4 A3 A2 A1 VCC VPP VPP OUT1 OUT64 OUT2 OUT63 OUT3 OUT62 OUT4 OUT61 VSS VSS OUT5 OUT60 OUT6 OUT59 OUT7 OUT58 OUT8 OUT57 OUT9 OUT56 OUT10 OUT55 OUT11 OUT54 OUT12 OUT53 VSS VSS OUT13 OUT52 OUT14 OUT51 STV7699 OUT15 OUT50 OUT16 OUT49 OUT17 OUT48 OUT18 OUT47 OUT19 OUT46 OUT20 OUT45 VSS VSS OUT21 OUT44 OUT22 OUT43 OUT23 OUT42 OUT24 OUT41 VPP VPP 7699C-02.EPS OUT40 OUT39 OUT38 OUT37 VSS OUT36 OUT35 OUT34 OUT33 VSSSUB VSS OUT32 OUT31 OUT30 OUT29 VSS OUT28 OUT27 OUT26 OUT25 4/11 CM17699 4 - PCB MECHANICAL SPECIFICATIONS The rigid board is 92mm long by 30mm wide. The rigid board can be mounted on the mechanical chassis of the plasma panel or on a heat sinker by clips and/or screws. The recommended size of the heat sinker depends on the final application if data drivers are powered with a DC or an AC supply. Power supplies (VPP, VSS) are dispatched by large copper surface in order to spread the current on the board and reduce voltage drops and EMI. Figure 3 92.0mm CN1 & CN2 : JAE IL-3PL-SMTY-E1500 3.3mm 33.0mm 4mm 3 CN2 1 5mm 50 CN3 1 3 CN1 35.1mm 7699C-03.EPS 9.60mm 9.60mm CN3 : JAE IL-FHR-50S-HF-E3000 5mm 10.9mm 10.9mm 5 - FPC MECHANICAL SPECIFICATIONS Figure 4 LCD Bonding 2.0 15.0mm 6mm 10.0mm Ø 0.5mm 0.15 2.25 0.4 0.4 0.4 101.4mm P 0.3 x (324-1) x 0.9991 = 96.81279 W = 0.15 5mm 50.0mm 1.15 1.25mm 1.2mm 0.4 0.4 0.4 4.7mm 3.75 Design values : Conductor width = 0.15 ± 0.04 Gap width = 0.15 ± 0.04 7699C-04.EPS FPC specifications (UPILEX otherwise thermal expansion specified) Cu Foil : 35m m Ni Plating : > 1m m Au Plating : > 0.1m m PCB Bonding 3 P 0.25961 x (326-1) = 84.37325 W = 0.1 1.4 3mm 1.4 6 - STV7699 SPECIFICATIONS 6.1 - Features - 64 outputs plasma display driver - 170V absolute maximum supply - 5V supply for logic - 50/40mA source / sink output - 60/60mA source / sink output diode - 64-bit shift register (20MHz) - BLK, polarity and HIZ control - BCD technology 6.2 - General Description The STV7699 is a Plasma Display Panel (PDP) data driver implemented in ST’s proprietary BCD technology. Using a 4-bit wide cascadable shift register, it drives 64 high current & high voltage outputs. By serialy connecting several STV7699, any horizontal pixel definition can be performed. The 20MHz shift clock gives an equivalent 80MHz shift register. The STV7699 is supplied with a separated 170V power output supply and a 5V logic supply. All command inputs are CMOS compatible. 5/11 CM17699 6 - STV7699 SPECIFICATIONS (continued) 6.3 - Pad Dimensions (in µm) The reference is the center of the die (x = 0, y = 0). LEFT SIDE from top to bottom Name VPP OUT1 OUT2 OUT3 OUT4 VSSP OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 VSSP OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 VSSP OUT21 OUT22 OUT23 OUT24 VPP Center : X Center : Y Size : x -1738.0 2867.5 90.0 -1738.0 2703.0 90.0 -1738.0 2570.5 90.0 -1738.0 2411.0 90.0 -1738.0 2228.5 90.0 -1738.0 2093.0 90.0 -1738.0 1952.0 90.0 -1738.0 1813.5 90.0 -1738.0 1631.0 90.0 -1738.0 1453.0 90.0 -1738.0 1235.5 90.0 -1738.0 1046.5 90.0 -1738.0 862.0 90.0 -1738.0 712.5 90.0 -1738.0 566.0 90.0 -1738.0 431.0 90.0 -1738.0 293.0 90.0 -1738.0 82.5 90.0 -1738.0 -109.5 90.0 -1738.0 -277.0 90.0 -1738.0 -471.0 90.0 -1738.0 -691.5 90.0 -1738.0 -822.5 90.0 -1738.0 -953.0 90.0 -1738.0 -1096.0 90.0 -1738.0 -1335.5 90.0 -1738.0 -1569.0 90.0 -1738.0 -1697.5 90.0 -1715.0 -2045.0 90.0 Size : y 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 200.0 BOTTOM SIDE from left to right Name OUT25 OUT26 OUT27 OUT28 VSSP OUT29 OUT30 OUT31 OUT32 VSSP VSSSUB OUT33 OUT34 OUT35 OUT36 VSSP OUT37 OUT38 OUT39 OUT40 6/11 Center : X Center : Y Size : x -1443.5 -3077.0 75.0 -1249.0 -3077.0 75.0 -1049.5 -3077.0 75.0 -889.0 -3077.0 5.0 -753.0 -3077.0 75.0 -614.0 -3077.0 75.0 -467.5 -3077.0 75.0 -332.0 -3077.0 75.0 -186.5 -3077.0 75.0 -54.0 -3077.0 75.0 78.0 -3077.0 75.0 209.5 -3077.0 75.0 342.5 -3077.0 75.0 467.5 -3077.0 75.0 607.5 -3077.0 75.0 752.0 -3077.0 75.0 892.5 -3077.0 75.0 1045.5 -3077.0 75.0 1252.0 -3077.0 75.0 1433.5 -3077.0 75.0 Right SIDE from bottom to top Name VPP OUT41 OUT42 OUT43 OUT44 VSSP OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 VSSP OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 VSSP OUT61 OUT62 OUT63 OUT64 VPP Center : X Center : Y Size : x 1600.5 -2087.0 90.0 1737.5 -1646.0 90.0 1737.5 -1507.0 90.0 1737.5 -1328.0 90.0 1737.5 -1096.0 90.0 1737.5 -953.0 90.0 1737.5 -822.5 90.0 1737.5 -691.5 90.0 1737.5 -471.0 90.0 1737.5 -277.0 90.0 1737.5 -109.5 90.0 1737.5 82.5 90.0 1737.5 293.0 90.0 1737.5 431.0 90.0 1737.5 566.0 90.0 1737.5 712.5 90.0 1737.5 862.0 90.0 1737.5 1046.5 90.0 1737.5 1235.5 90.0 1737.5 1453.0 90.0 1737.5 1631.0 90.0 1737.5 1813.5 90.0 1737.5 1952.0 90.0 1737.5 2093.0 90.0 1737.5 2228.5 90.0 1737.5 2411.0 90.0 1737.5 2570.5 90.0 1737.5 2703.0 90.0 1737.5 2873.5 90.0 Size : y 200.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 75.0 TOP SIDE from right to left Size : y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 Name VSSSUB B1 B2 B3 B4 HIZ POL BLK F/R VSSLOG VSSLOG STB CLK A4 A3 A2 A1 VCC Center : X Center : Y Size : x 1628.5 3073.5 75.0 1478.5 3073.5 75.0 1228.5 3077.0 75.0 978.5 3077.0 75.0 847.5 3077.0 75.0 716.5 3077.0 75.0 486.5 3077.0 75.0 355.5 3077.0 75.0 224.5 3077.0 75.0 31.0 3077.0 200.0 -354.5 3077.0 200.0 -582.0 3077.0 75.0 -713.0 3077.0 75.0 -844.0 3077.0 75.0 -975.0 3077.0 75.0 -1106.0 3077.0 75.0 -1471.5 3077.0 75.0 -1629.0 3077.0 75.0 Size : y 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 90.0 CM17699 6 - STV7699 SPECIFICATIONS (continued) 6.4 - Block Diagram CLK F/R 16-BIT SHIFT REGISTER A1 P1 B1 P61 16-BIT SHIFT REGISTER A2 P2 B2 P62 16-BIT SHIFT REGISTER A3 P3 B3 P63 16-BIT SHIFT REGISTER A4 P4 P1 B4 P64 P4 P63 P64 VCC Q63Q64 VSSLOG Pins 90 to 93 LATCH STB Q1 Q2 BLK VSSSUB Pins 41-81 POL VSSP Pins 6-15-24-35 40-46-57-66-75 STV7699 2 79 OUT1 OUT64 7699C-05.EPS VPP Pins 1-29-30 51-52-80 HIZ 6.5 - Circuit Description STV7699 contains all the logic and the power circuits necessary to drive the colums of a Plasma Display Panel (P.D.P.). Data are shifted at each low to high transition of the (CLK) shift clock. Data are input in a 4-bit wide data bus to A1 - A4 input (case of forward shift mode ; F/R = low). After 16 shifts, the first nibble is available at the serial outputs B1 - B4. These outputs can be used to cascade several drivers to perform any horizontal resolution. CLK, Ai and Bi inputs are Smith trigger inputs to improve the noise margin. The Forward/Reverse (F/R) input is used to select the direction of the shift register. The maximum frequency of the shift clock is 20MHz. All the output data are held and memorized into the latch stage when the Latch input (STB) is high. When it is at low level, data are transferred from the shift register to the latch and to the output power stage. Output state can be forced to high impedance by pulling low HIZ input. When BLK is Low, all the outputs are forced to low level or high level according to POL signal value. Output state copy data that was input, with the same polarity, when BLK, HIZ and POL are High. VSSLOG, VSSSUB and VSSP are not internally connected. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Table 1 : Power Output Truth Table Driver Data STB POL BLK HIZ Output x x x x L HIZ x x L x H L x x H L H H x H H H H Qn (1) L L H H H L H L H H H H Comments High impedance Forced to low Forced to high Latched data Copy data Copy data Note 1 : Qn is the value memorised in the latch stage ; it is the value of the parallel shift register output stage after n Clock pulses. A data loaded in the shift register is read on the output power stage without inversion of its polarity. Table 2 : Control Table F/R L H Ai Input Output Bi Output Input Comments Forward shift Reverse shift 7/11 CM17699 6 - STV7699 SPECIFICATIONS (continued) 6.6 - Characteristics 6.6.1 - Absolute Maximum Ratings Symbol VCC VIN VOUT VPOUT VPP IPOUT IDOUT Tjmax Toper Tstg Parameter Value -0.3, +7 -0.3, VCC + 0.3 -0.3, VCC + 0.3 -0.3, +170 -0.3, +170 ±60 +40/-50 +150 -20, +85 -50, +150 Logic Supply Logic Input Voltage Logic Output Voltage Driver Output Voltage Driver Power Supply Driver Output Current (1) Diode Output Current (1) Junction Temperature Operating Temperature Storage Temperature Unit V V V V V mA mA °C °C °C Note : 1. Through all power outputs : with power dissipation lower or equal than Ptot and junction temperature lower or equal than Tjmax. 6.6.2 - Electrical Characteristics (VCC = 5V, VPP = 160V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, fCLK = 20MHz, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit 4.5 5 5.5 - 12 - 100 TBD 160 - - 100 V µA mA V µA 55 TBD - 60 2 12 - 5 TBD 3 V V V V V - - -3 ±10 V µA 4 - 0.1 0.3 V V 0.8 VCC - - 0.2 VCC 1 -1 V V µA µA SUPPLY VCC Logic Supply Voltage ICCH ICCL Logic Supply Current Logic Supply Current Power Output Supply Voltage VPP IPPH fCLK = 20MHz Power Output Supply Current (steady outputs) OUTPUT OUT1-OUT64 VPOUTH Power Output High Level IPOUTH = - 10mA, VPP = 65V IPOUTH = - 40mA, VPP = 65V VPOUTL Power Output Low Level VDOUTH VDOUTL IOUTHIZ Output Diode High Level IPOUTL = + 10mA IPOUTL = + 30mA IDOUTH = + 25mA (2)(3) Output Diode Low Level IDOUTL = - 25mA (2)(3) Output Stage Leakage Current on HIZ State SHIFT REGISTER OUTPUT (Ai or Bi according to F/R Status) VOH Logic Output High Level IOH = - 0.5mA VOL Logic Output Low Level IOL = + 0.5mA INPUT (CLK, STB, BLK, HIZ, Ai, Bi) VIH VIL IIH IIL Input High Level Input Low Level High Level Input Current Low Level Input Current Notes : 2. Compatible with power dissipation and Tjoper ≤ 125°C. 3. See test diagram. 8/11 VIH = VCC VIL = 0V CM17699 6 - STV7699 SPECIFICATIONS (continued) 6.6.3 - AC Timings Requirements (VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns) Symbol Parameter Min. Typ. Max. Unit Data Clock Period 50 - - ns tWHCLK Duration of clock (CLK) pulse at high level 15 - - ns tWLCLK Duration of clock (CLK) pulse at low level 15 - - ns tSDAT Set-up Time of data input before clock (low to high) transition 0 - - ns tHDAT Hold Time of data input after clock (low to high) transition 15 - - ns tDSTB Minimum Delay to latch (STB) after clock (low to high) transition 20 - - ns tSTB Latch (STB) Low Level Pulse Duration 10 - - ns tCLK tBLK Blanking (BLK) Pulse Duration 100 - - ns tPOL Polarity (POL) Pulse Duration 100 - - ns tHIZ High Impedance (HIZ) Pulse Duration 100 - - ns tSFR Set-up Time of Forward/Reverse Signal before Clock (low to high) transition 100 - - ns 6.6.4 - AC Timings Characteristics (VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified) Symbol Parameter tCLK Data Clock Period tRDAT Min. Typ. Max. Unit 50 - - ns Logical Data Output Rise Time - TBD 30 ns tFDAT Logical Data Output Fall Time - TBD 30 ns tPHL1 tPLH1 Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition - 40 40 TBD TBD ns ns tPHL2 tPLH2 Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition - TBD TBD 120 120 ns ns tPHL3 tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition - TBD TBD 110 110 ns ns tPHL4 Delay of power output change (high to low transition) to Blank (BLK) or Polarity (POL) transition Delay of power output change (low to high transition) to Blank (BLK) or Polarity (POL) transition - TBD 100 ns - TBD 100 ns tPHZ5 tPLZ5 Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5) - TBD TBD 100 100 ns ns tPZH5 tPZL5 Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5) - TBD TBD 100 100 ns ns tROUT Power Output Rise Time (6) - - 150 ns tFOUT Power Output Fall Time (6) - - 150 ns tPLH4 Notes : 5. See test diagram. 6. One output among 64, loading capacitor COUT = 50pF, other outputs at low level. 9/11 CM17699 6 - STV7699 SPECIFICATIONS (continued) Figure 5 : AC Characteristics Waveform tCLK tWHCLK tWLCLK "1" CLK 50% 50% 50% tSDAT "0" tHDAT "1" 50% SIN 50% "0" tPHL1 tFDAT "1" 90% SOUT 50% 10% "0" tRDAT tSTB tPLH1 tDSTB "1" 50% STB 50% "0" tSFR "1" F/R 50% tPHL3 "0" tPHL2 "1" 90% 10% OUTn 90% 10% 90% 10% "0" tPLH3 tPLH2 tPOL "1" POL 50% 50% tPLH4 "0" tPHL4 "1" 90% OUTn 10% "0" "1" tHIZ 50% tROUT OUTn 90% 10% 90% 10% 50% tPHZ5 tPZH5 90% 10% 90% tPLZ5 tPZL5 "0" "1" 10% "0" tFOUT 10/11 7699C-06.EPS HIZ CM17699 6 - STV7699 SPECIFICATIONS (continued) 6.7 - Input/output Schematics Figure 6 : F/R, BLK, POL, HIZ Figure 7 : CLK, STB VCC (Pin 100) VCC (Pin 100) F/R, BLK, POL, HIZ (Pins 89, 88, 87, 86) CLK, STB (Pins 95, 94) 7699C-07.EPS VSSSUB (Pins 41-81) Figure 8 : Ai, Bi VSSLOG (Pins 90 to 93) VSSSUB (Pins 41-81) 7699C-08.EPS VSSLOG (Pins 90 to 93) Figure 9 : Power Output VCC (Pin 100) VPP (Pins 1, 29, 30, 51, 52, 80) A4 to A1 (Pins 96 to 99) B1 to B4 (Pins 82 to 85) VSSP (Pins 6, 15, 24, 35, 40, 46, 57, 66, 75) 7699C-10.EPS VSSLOG (Pins 90 to 93) VSSLOG (Pins 90 to 93) 7699C-09.EPS VSSSUB (Pins 41-81) OUTi (Pins 2 to 5, 7 to 14, 16 to 23, 25 to 28, 31 to 34, 36 to 39, 42 to 45, 47 to 50, 53 to 56, 58 to 65, 67 to 74, 76 to 79) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics © 1999 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. 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