STV7697A PLASMA DISPLAY PANEL SCAN DRIVER FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ . 64 OUTPUTS PLASMA DISPLAY DRIVER 170V ABSOLUTE MAXIMUM SUPPLY 5V SUPPLY FOR LOGIC 100/400 mA SOURCE / SINK OUTPUT 700 mA SOURCE / SINK OUTPUT DIODE 64-BIT SHIFT REGISTER (20 MHz) BLANK CONTROL COMPLEMENTARY OUTPUT CONTROL BCD TECHNOLOGY 100 PINS PQFP PACKAGE OR DICE. DESCRIPTION The STV7697A is a scan driver for Plasma Display Panel (PDP) implemented in ST’s proprietary BCD technology. Using a 64-bit cascadable 20 MHz shift register, it drives 64 high current & high voltage outputs. By serially connecting several STV7697A, any vertical pixel definition can be performed. The STV7697A is supplied with a separated 160V power output supply and a 5V logic supply.All command inputs are CMOS compatible. The STV769 7A package is a 100 pins PQFP. PQFP100 (14 x 20 x 2.80 mm) (Full Plastic Quad Flat Pack) ORDER CODE: STV7697A ORDER CODE: STV7697A/WAF (1) (1): Unsawn Tested Wafer Version 4.2 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/15 1 TABLE OF CONTENTS PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Note 1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Note 1 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Note 5 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Note 6 AC TIMINGS REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Note 6 AC TIMINGS CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. INPUT/OUTPUT SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6. PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2 2/15 2 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUT35 OUT36 OUT37 OUT38 OUT39 OUT40 OUT41 OUT42 OUT43 OUT44 OUT45 OUT46 OUT47 OUT48 OUT49 OUT50 OUT51 OUT52 OUT53 OUT54 OUT55 OUT56 OUT57 OUT58 OUT59 OUT60 OUT61 OUT62 OUT63 OUT64 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OUT34 31 100 VPP OUT33 32 99 VSSP VPP 33 98 VSSP VSSP 34 97 VPP VSSP 35 96 NC VSSP 36 95 NC VPP 37 94 VSSLOG VSSSUB 38 93 CLK VSSLOG 39 92 STB VSSLOG VCC 40 91 SOUT(SIN) 90 VCC VSSLOG 42 89 SIN(SOUT) VSSSUB 43 88 NC VPP 44 87 F/R VSSP 45 86 BLK VSSP 46 85 POL VSSP 47 84 VPP VPP 48 83 VSSP OUT32 49 82 VSSP OUT31 50 81 VPP 41 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 y (0,0) OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 VSSLOG VCC OUT18 VSSP VSSP x VSSSUB VSSLOG OUT19 VPP OUT20 VSSP OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27 OUT28 OUT29 OUT30 OUT64 OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT53 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39 OUT38 OUT37 OUT36 OUT35 STV7697A PIN CONNECTIONS (Die pinout) OUT34 OUT33 VPP VSSP VPP VSSP VSSP VSSP VPP STV7697A VSSLOG CLK Bare Die STB SOUT(SIN) VCC VSSLOG SIN(SOUT) F/R VSSSUB VPP BLK POL VSSP VPP VPP OUT32 OUT31 VSSP VSSP VPP PIN CONNECTIONS (TQFP pinout) STV7697A PQFP100 3/15 3 STV7697A PIN ASSIGNMENT (TQFP100) Pin Number Symbol Type Function 33-37-44-48-81-84-97-100 V PP Supply High Voltage Supply of power outputs 41 - 90 VCC Supply 5 V Logic Supply 34-35-36-45-46-47-82-83-98-99 VSSP Ground Ground of power outputs 38-43 V SSSUB Ground Substrate Ground 39-40-42-94 VSSLOG Ground Logic Ground 1 to 32, 49 to 80 OUT 64 to OUT 1 Output Power Output 91 SOUT (SIN) Output Shift Register Data Output (forward) 85 POL Input Polarity Selection 86 BLK Input Output Blanking Command 87 F/ R Input Selection of shift direction 89 SIN (SOUT) Input Shift Register Data Input (forward) 92 ST B Input Latch of data to outputs 93 CLK Input Clock of data shift register 88-95-96 NC - PIN ASSIGNMENT (Power Outputs) Output N° Pin N° Output N° Pin N° Output N° Pin N° Output N° Pin N° 1 80 17 64 33 32 49 16 2 79 18 63 34 31 50 15 3 78 19 62 35 30 51 14 4 77 20 61 36 29 52 13 5 76 21 60 37 28 53 12 6 75 22 59 38 27 54 11 7 74 23 58 39 26 55 10 8 73 24 57 40 25 56 9 9 72 25 56 41 24 57 8 10 71 26 55 42 23 58 7 11 70 27 54 43 22 59 6 12 69 28 53 44 21 60 5 13 68 29 52 45 20 61 4 14 67 30 51 46 19 62 3 15 66 31 50 47 18 63 2 16 65 32 49 48 17 64 1 4/15 3 STV7697A PADS DIMENSIONS (in µm)/ PADS POSITIONS The reference is the centre of the die (x=0, y=0) TOP SIDE from left to right Name Centre:X Centre:Y BOTTOM SIDE from left to right (continued) Name Centre:X Centre:Y Size:x SIze: y Size:x SIze: y VPP 1438.5 -4087.5 75.0 90.0 VPP -2468.5 4135.0 75.0 90.0 VSSP 1797.5 -4093.5 75.0 90.0 VSSP -2313.5 4135.0 75.0 90.0 VSSP 1932.5 -4093.5 75.0 90.0 VSSP -2188.5 4135.0 75.0 90.0 VSSP 2067.5 -4093.5 75.0 90.0 VPP -2063.5 4134.5 75.0 90.0 VPP 2193.0 -4093.5 75.0 90.0 VSSLOG -1620.0 4135.0 75.0 90.0 OUT32 2318.0 -4093.5 75.0 90.0 CLK -1430.0 4135.0 75.0 90.0 OUT31 2468.5 -4093.5 75.0 90.0 STB -781.0 4135.0 75.0 90.0 SOUT -612.5 4135.0 75.0 90.0 VCC -335.5 4144.5 75.0 90.0 SIN 379.5 4135.0 75.0 90.0 OUT1 2647.0 F/R 548.0 4135.0 75.0 90.0 OUT2 BLK 1082.0 4135.0 75.0 90.0 POL 1853.0 4135.0 75.0 VPP 2021.5 4140.0 VSSP 2156.5 VSSP VPP Size:x SIze: y 3697.0 90.0 75.0 2647.0 3484.0 90.0 75.0 OUT3 2647.0 3238.5 90.0 75.0 90.0 OUT4 2647.0 2992.5 90.0 75.0 75.0 90.0 OUT5 2647.0 2743.0 90.0 75.0 4140.0 75.0 90.0 OUT6 2647.0 2506.5 90.0 75.0 2291.5 4140.0 75.0 90.0 OUT7 2647.0 2264.0 90.0 75.0 2454.5 4129.5 75.0 90.0 OUT8 2647.0 2018.0 90.0 75.0 OUT9 2647.0 1774.5 90.0 75.0 OUT10 2647.0 1529.0 90.0 75.0 BOTTOM SIDE from left to right Name RIGHT SIDE from top to bottom Centre:X Centre:Y Name Centre:X Centre:Y Size:x SIze: y OUT11 2647.0 1285.5 90.0 75.0 OUT34 -2468.0 -4087.5 75.0 90.0 OUT12 2647.0 1040.0 90.0 75.0 OUT33 -2318.0 -4089.5 75.0 90.0 OUT13 2647.0 796.5 90.0 75.0 VPP -2182.0 -4089.5 75.0 90.0 OUT14 2647.0 551.0 90.0 75.0 VSSP -2047.0 -4093.0 75.0 90.0 OUT15 2647.0 307.5 90.0 75.0 VSSP -1912.0 -4093.0 75.0 90.0 OUT16 2647.0 62.0 90.0 75.0 VSSP -1777.0 -4093.0 75.0 90.0 OUT17 2647.0 -181.5 90.0 75.0 VPP -1642.0 -4089.5 75.0 90.0 OUT18 2647.0 -427.0 90.0 75.0 VSSSUB -683.0 -4088.0 75.0 90.0 OUT19 2647.0 -670.5 90.0 75.0 VSSLOG -382.5 -4088.0 75.0 90.0 OUT20 2647.0 -916.0 90.0 75.0 VSSLOG 419.5 -4087.5 75.0 90.0 OUT21 2647.0 -1159.5 90.0 75.0 VCC 618.5 -4087.5 75.0 90.0 OUT22 2647.0 -1405.0 90.0 75.0 VSSLOG 951.0 -4087.5 75.0 90.0 OUT23 2647.0 -1648.5 90.0 75.0 VSSSUB 1308.0 -4087.5 75.0 90.0 OUT24 2647.0 -1894.0 90.0 75.0 5/15 3 STV7697A RIGHT SIDE from top to bottom (continued) Name Centre:X Centre:Y Size:x SIze: y Name Centre:X Centre:Y Size:x SIze: y OUT25 2647.0 -2137.5 90.0 75.0 OUT61 -2646.5 2949.5 90.0 75.0 OUT26 2647.0 -2383.5 90.0 75.0 OUT62 -2646.5 3228.5 90.0 75.0 OUT27 2647.0 -2627.0 90.0 75.0 OUT63 -2646.5 3487.0 90.0 75.0 OUT28 2647.0 -2872.5 90.0 75.0 OUT64 -2646.5 3763.0 90.0 75.0 OUT29 2647.0 -3116.0 90.0 75.0 OUT30 2647.0 -3363.0 90.0 75.0 Size:x SIze: y LEFT SIDE from bottom to top Name Centre:X Centre:Y OUT35 -2646.5 -3363.0 90.0 75.0 OUT36 -2646.5 -3116.0 90.0 75.0 OUT37 -2646.5 -2872.5 90.0 75.0 OUT38 -2646.5 -2627.0 90.0 75.0 OUT39 -2646.5 -2383.5 90.0 75.0 OUT40 -2646.5 -2137.5 90.0 75.0 OUT41 -2646.5 -1894.0 90.0 75.0 OUT42 -2646.5 -1648.5 90.0 75.0 OUT43 -2646.5 -1405.0 90.0 75.0 OUT44 -2646.5 -1159.5 90.0 75.0 OUT45 -2646.5 -916.0 90.0 75.0 OUT46 -2646.5 -670.5 90.0 75.0 OUT47 -2646.5 -427.0 90.0 75.0 OUT48 -2646.5 -181.5 90.0 75.0 OUT49 -2646.5 62.0 90.0 75.0 OUT50 -2646.5 307.5 90.0 75.0 OUT51 -2646.5 551.0 90.0 75.0 OUT52 -2646.5 796.5 90.0 75.0 OUT53 -2646.5 1040.0 90.0 75.0 OUT54 -2646.5 1285.5 90.0 75.0 OUT55 -2646.5 1529.0 90.0 75.0 OUT56 -2646.5 1774.5 90.0 75.0 OUT57 -2646.5 2018.0 90.0 75.0 OUT58 -2646.5 2264.0 90.0 75.0 OUT59 -2646.5 2506.5 90.0 75.0 OUT60 -2646.5 2743.0 90.0 75.0 6/15 3 LEFT SIDE from bottom to top (continued) STV7697A BLOCK DIAGRAM VCC CLK 93 87 F/R 64-BIT SHIFT REGISTER SIN (SOUT) 89 P1 91 SOUT (SIN) P64 S1 VSSSUB Pins 38-43 S64 LATCH STB 92 Q1 Q2 Q63Q64 VSSLOG Pins 39-40-42-94 VCC BLK 86 VCC Pins 41-90 VCC POL 85 --- --- STV7697A VSSP VSSP Pins 34-35-36-45-46 47-82-83-98-99 VPP VSSP VPP Pins 33-37-44-48 81-84-97-100 VPP 80 1 OUT1 OUT64 CIRCUIT DESCRIPTION The STV7697A contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (P. D. P.). The state of the displayed line is loaded into the shift register. Data are shifted at each low to high transition of the (CLK) shift clock. After 64 shifts the first bit is available at the serial output. This output can be used to cascade several drivers to perform any vertical resolution. The forward / reverse (F/R) input is used to select the direction of the shift register, data input/output status is set according to the selected direction. SIN, CLK, STB inputs are Smith trigger inputs . If not used on the application, F/R, BLK, POL logical inputs are internaly pulled to level ”1”. The maximum frequency of the shift clock is 20 MHz. All the data are memorized into the latch stage when the strobe input (STB) is pulled high. Blanking input (BLK) forces the power outputs to high level when pulled high with polarity input (POL) at high level and forced to low level with POL at low level. The level of the power output is inverted when the polarity command (POL) is pulled high. Sustain current must not be sunk in the power output to VPP when the power supply is applied. VSSLOG and VSSSUB must be connected as close as possible to the logical reference ground of the application. Shift Register Truth Table Input F/R Input /Outp ut Shift Register Function CLK SIN SOUT Output Q H Rise IN OUT Forward Shift H H or L IN OUT Steady L Rise OUT IN Reverse Shift L H or L OUT IN Steady 7/15 3 STV7697A Power Output Truth Table Qn (1) STB BLK POL Driver Output Comments X X H H All H Forced to High X X H L All L Forced to Low H L L L H Copy Data L L L L L Copy Data H L L H L Copy Inverted Data L L L H H Copy Inverted Data X H L L Qn Data Latched X H L H Qn Inverted Data Latched Note 1 Qn is the parallel output of the shift register (n = 1 to 64). Qn takes the value of serial input (SIN) after ”n” shift clock periods. ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit -0.3, +7 V -0.3, +170 V -0.3, VCC +0.3 V VCC Logic Supply Range VPP Driver Supply Range VIN Logic Input Voltage Range V OUT Logic Output Voltage Range -0.3, VCC + 0.3 V VPOUT Driver Output Voltage Range -0.3, VPP V +100/-400 mA IPOUT Driver Output Current (3) (5) IDOUT Diode Output Current (4) (5) Tjmax Operating Temperature Toper Junction Temperature (2) Tstg Storage Temperature ±700 mA -20, +85 °C +125 °C -50,+150 °C Value Unit THERMAL DATA Symbol Parameter Rth(j-a) Junction-ambient Thermal Resistance (2) Max 50 °C/W P oper Operating Power Dissipation (Tamb = 25°C) Max 2 W Tjoper Operating Junction Temperature (2) Max +125 °C Note 2 For PQFP100 packaging. Note 3 Through one power output. Note 4 Through one power output with VPP = VSSP (see test diagram) . Note 5 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. 8/15 3 STV7697A ELECTRICAL CHARACTERISTICS (VCC = 5 V, V PP = 160 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, unless otherwise specified) Symbol Parameter Test Condition s Min. Typ. Max. Unit 4.5 5 5.5 V - - 100 µA - 5.3 - mA SUPPLY VCC Logic Supply Voltage I CCH Logic Supply Current (all inputs high) ICCL Logic Supply Current VPP Power Output Supply Voltage 15 - 160 V IPPH Power Output Supply Current (steady outputs) - - 100 µA fCLK = 8 MHz, SIN = 1010 OUTPUT OUT1-OUT64 Power Output High Level (voltage drop versus VPP) IPOUTH = - 10 mA IPOUTH = - 40 mA 10 - 5 - V V V POUTL Power Output Low Level IPOUTL = 200 mA - 3.1 10 V VDOUTH Output Diode High Level IDOUTH = +400 mA (5) - 2.3 10 V VDOUTL Output Diode Low Level IDOUTL = - 400 mA (5) -10 -2.2 - V VOH Logic Output High Level IOH = 1 mA 4 - - V VOL Logic Output Low Level IOL = -1 mA - - 0.4 V VPOUTH SOUT INPUT (CLK, F/ R , ST B, POL, BLK, SIN, ) V IH Input High Level 0.8 VCC - - V VIL Input Low Level - - 0.2V CC V IIH High Level Input Current VIH = VCC - - 10 µA IIL Low Level Input Current CLK, SIN, ST B , F/ R , BLK, POL VIL = 0 V - 70 10 100 µA µA Note 6 Compatible with power dissipation (see test diagram). 9/15 3 STV7697A AC TIMINGS REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns) Symbol Min. Typ. Max. Unit Data Clock Period 50 - - ns tWHCLK Duration of clock (CLK) pulse at high level 15 - - ns tWHCLK Duration of clock (CLK) pulse at low level 15 - - ns tSDAT Set-up Time of data input before clock low to high transition 10 - - ns tHDAT Hold Time of data input after clock low to high transition 10 - - ns tSFR Forward/reverse (F/R) Set-up Time before low to high transition 100 - - ns tDSTB Minimum Delay to latch STB after clock low to high transition 10 - - ns tSTB Strobe STB Pulse Duration 20 - - ns tBLK Blank (BLK) Pulse Duration 500 - - ns tPOL Polarity (POL) Pulse Duration 500 - - ns tCLK Parameter AC TIMINGS CHARACTERISTICS (VCC = 5 V, V PP = 90 V, VSSP = 0 V, VSSLOG = VSSSUB = 0 V, Tamb = 25°C, fCLK = 20 MHz, VILMax. = 0.2 Vcc, VIHMin. = 0.8 VCC, VOH = 4.0 V, VOL = 0.4 V, CL = 15pF, unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit 50 - - ns tCLK Data Clock Period tRDAT tFDAT Logical Data Output Rise Time Logical Data Output Fall Time - 20 11 - ns ns tPHL1 tPLH1 Delay of logic data output after clock (CLK) high to low transition Delay of logic data output after clock (CLK) low to high transition - 45 48 80 80 ns ns tPHL2 tPLH2 Delay of power output change after clock (CLK) high to low transition Delay of power output change after clock (CLK) low to high transition - 120 120 180 180 ns ns tPHL3 tPLH3 Delay of power output change after blanking (BLK) high to low transition Delay of power output change after blanking (BLK) low to high transition - 110 110 165 165 ns ns tPHL4 tPLH4 Delay of power output change after polarity (POL) high to low transition Delay of power output change after polarity (POL) low to high transition - - 160 160 ns ns tROUT tFOUT Power Output Rise Time (7) Power Output Fall Time (7) - 100 60 200 200 ns ns Note 7 One output among 64, loading capacitor COUT = 100pF, other outputs at low level. 10/15 3 STV7697A Figure 1. AC Characteristics Waveform tCLK tWLCLK tWHCLK ”1” 50% CLK 50% 50% ”0” tSDAT tHDAT ”1” SIN 50% 50% ”0” tPLH1 tFDAT 10% 10% SOUT ”1” 90% 90% 50% ”0” tSTB tRDAT ”1” tDSTB 50% STB 50% ”0” tSFR ”1” 50% F/R ”0” tPHL2 ”1” 90% OUTn 10% ”0” tPLH2 tBLK ”1” 50% BLK 50% ”0” tPLH3 tPHL3 ”1” 90% OUTn 10% ”0” tPOL ”1” 50% POL 50% ”0” tROUT OUTn 90% 10% 90% 10% tPHL4 tPLH4 ”1” 90% 10% ”0” tFOUT 11/15 STV7697A Figure 2. Test Configuration VPP VDOUTH VPP IDOUTL OUTI OUTI VDOUTL VSSP VSSP Output sinking current as positive value, sourcing current as negative value 12/15 IDOUTL STV7697A INPUT/OUTPUT SCHEMATICS Figure 3. F/R, BLK, POL, HIZ Figure 5. SIN, SOUT Input VCC (Pins 41, 90) VCC (Pins 41, 90) SIN, SOUT (Pins 89, 91) F/R, BLK, POL (Pins 87, 86, 85) VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) Figure 4. CLK, STB VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) VSSLOG (Pins 39, 40, 42, 94) Figure 6. Power Output VCC (Pins 41, 90) VPP (Pins 33, 37, 44, 48, 81, 84, 97, 100) OUTi (Pins 1 to 32, 49 to 80) CLK, STB (Pins 93, 92) VSSSUB (Pins 38, 43) VSSLOG (Pins 39, 40, 42, 94) VSSP (Pins 34, 35, 36, 45, 46, 47, 82, 83, 98, 99) 13/15 STV7697A PACKAGE MECHANICAL DATA 100 PINS - THIN PLASTIC QUAD FLAT PACK (PQFP100) A A2 A1 e 80 51 0,10 mm .004 inch SEATING PLANE 50 100 31 E c 30 L1 D3 D1 D L 1 E1 E3 B 81 K Millimeters Inches Dimensions Min. Typ. A Min. Typ. 3.40 A1 0.25 A2 2.55 B Max. 0.134 0.010 3.05 0.100 0.22 0.38 0.0087 0.015 C 0.13 0.23 0.005 0.009 D 22.95 23.20 23.45 0.903 0.913 0.923 D1 19.90 20.00 20.10 0.783 0.787 0.791 2.80 0.110 D3 18.85 0.742 e 0.65 0.026 0.120 E 16.95 17.20 17.45 0.667 0.677 0.687 E1 13.90 14.00 14.10 0.547 0.551 0.555 E3 L L1 K 14/15 Max. 12.35 0.65 0.80 0.486 0.95 0.026 1.60 0.031 0.063 0° (Min.), 7° (Max.) 0.037 STV7697A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. 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