STV7617, STV7617D, STV7617U PLASMA DISPLAY PANEL SCAN DRIVER FEATURE ■ ■ ■ ■ ■ ■ ■ ■ ■ 64/65 SELECTABLE OUTPUT PLASMA DISPLAY DRIVER 100 V ABSOLUTE MAXIMUM SUPPLY 5 V SUPPLY FOR LOGIC 100/850 mA SOURCE/SINK OUTPUT 700 mA SOURCE/SINK OUTPUT DIODE 65-bit BIDIRECTIONAL SHIFT REGISTER (8 MHz) HIGH IMPEDANCE OUTPUT CONTROL BCD TECHNOLOGY 100-PIN TQFP PACKAGE WITH INTEGRATED HEATSINK TQFP100 (14 x 14 x 1.4 mm Slug-down) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617D TQFP100 (14 x 14 x 1.4 mm) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617 DESCRIPTION The STV7617 is a scan driver for Plasma Display Panel (PDP) implemented in ST’s proprietary BCD technology. Using a 65-bit cascadable 8 MHz shift register, it drives 65 high current & high voltage outputs. The STV7617 can be configured either in 64 or 65 outputs depending on the SEL input Pin. By serially connecting several STV7617, any vertical pixel definition can be performed. The STV7617 is supplied with a separated 90V power output supply and a 5 V logic supply. All command inputs are CMOS compatible. The STV7617 package is a 100-pin TQFP with integrated heatsink located on the bottom (STV7617D) or top (STV7617U) of the package. It is also available without heatsink (STV7617). TQFP100 (14 x 14 x 1.4 mm Slug-up) (Thin Plastic Quad Flat Pack) ORDER CODE: STV7617U Version 4.1 June 2000 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/17 1 TABLE OF CONTENTS PIN CONNECTIONS (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN CONNECTIONS (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PIN CONNECTIONS (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 AC TIMING REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 AC TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 INPUT/OUTPUT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PACKAGE MECHANICAL DATA (SLUG-DOWN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PACKAGE MECHANICAL DATA (SLUG-UP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PACKAGE MECHANICAL DATA (NO SLUG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2 2/17 2 STV7617, STV7617D, STV7617U PIN CONNECTIONS (SLUG-UP) OUT64 OUT65 VPP VPP NC VSSP VSSP VSSLOG F/R SOUT CLK STB VCC BLK HIZ SIN SEL VSSLOG VSSP VSSP NC VPP VPP OUT1 OUT2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TQFP100 Slug-up) OUT63 1 75 OUT3 OUT62 2 74 OUT4 OUT61 3 73 OUT5 OUT60 4 72 OUT6 OUT59 5 71 OUT7 OUT58 6 70 OUT8 OUT57 7 69 OUT9 OUT56 8 68 OUT10 OUT55 9 67 OUT11 OUT54 10 66 OUT12 OUT33 11 65 OUT13 OUT52 12 64 OUT14 OUT51 13 63 OUT15 OUT50 14 62 OUT16 OUT49 15 61 OUT17 OUT48 16 60 OUT18 OUT47 17 59 OUT19 OUT46 18 58 OUT20 OUT45 19 57 OUT21 OUT44 20 56 OUT22 OUT43 21 55 OUT23 OUT42 22 54 OUT24 OUT41 23 53 OUT25 OUT40 24 52 OUT26 OUT39 25 51 OUT27 STV7617U 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OUT38 OUT37 OUT36 NC VSSP VSSP VSSSUB NC VPP VPP OUT35 OUT34 OUT33 OUT32 OUT31 VPP VPP NC VSSP VSSP VSSP NC OUT30 OUT29 OUT28 TQFP100 (Top View) 3/17 3 STV7617, STV7617D, STV7617U PIN CONNECTIONS (SLUG-DOWN) SEL SIN HIZ BLK VCC STB CLK SOUT F/R VSSLOG VSSP VSSP NC 92 91 90 89 88 87 86 85 84 83 82 81 80 OUT64 VSSLOG 93 OUT65 VSSP 94 76 VSSP 95 77 NC 96 VPP VPP VPP VPP 97 78 OUT1 98 79 OUT2 99 OUT3 1 75 OUT63 OUT4 2 74 OUT62 OUT5 3 73 OUT61 OUT6 4 72 OUT60 OUT7 5 71 OUT59 OUT8 6 70 OUT58 OUT9 7 69 OUT57 OUT10 8 68 OUT56 OUT11 9 67 OUT55 OUT12 10 66 OUT54 OUT13 11 65 OUT33 OUT14 12 64 OUT52 OUT15 13 63 OUT51 OUT16 14 62 OUT50 OUT17 15 61 OUT49 OUT18 16 60 OUT48 OUT19 17 59 OUT47 OUT20 18 58 OUT46 OUT21 19 57 OUT45 OUT22 20 56 OUT44 OUT23 21 55 OUT43 OUT24 22 54 OUT42 OUT25 23 53 OUT41 OUT26 24 52 OUT40 OUT27 25 51 OUT39 4/17 3 100 (TQFP100 Slug-down) STV7617D 43 44 45 46 47 48 49 50 NC VSSSUB VSSP VSSP NC OUT36 OUT37 OUT38 40 OUT35 42 39 OUT34 41 38 OUT33 VPP 37 OUT32 VPP 36 34 VPP 35 33 NC VPP 32 VSSP OUT31 31 29 NC 30 28 OUT30 VSSP 27 OUT29 VSSP 26 OUT28 TQFP100 (Top View) STV7617, STV7617D, STV7617U PIN CONNECTIONS (NO SLUG) OUT2 OUT1 VPP VPP NC VSSP VSSP VSSLOG SEL SIN HIZ BLK VCC STB CLK SOUT F/R VSSLOG VSSP VSSP NC VPP VPP OUT65 OUT64 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (TQFP100) OUT3 1 75 OUT63 OUT4 2 74 OUT62 OUT5 3 73 OUT61 OUT6 4 72 OUT60 OUT7 5 71 OUT59 OUT8 6 70 OUT58 OUT9 7 69 OUT57 OUT10 8 68 OUT56 OUT11 9 67 OUT55 OUT12 10 66 OUT54 OUT13 11 65 OUT33 OUT14 12 64 OUT52 OUT15 13 63 OUT51 OUT16 14 62 OUT50 OUT17 15 61 OUT49 OUT18 16 60 OUT48 OUT19 17 59 OUT47 OUT20 18 58 OUT46 OUT21 19 57 OUT45 OUT22 20 56 OUT44 OUT23 21 55 OUT43 OUT24 22 54 OUT42 OUT25 23 53 OUT41 OUT26 24 52 OUT40 OUT27 25 51 OUT39 STV7617 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 OUT28 OUT29 OUT30 NC VSSP VSSP VSSP NC VPP VPP OUT31 OUT32 OUT33 OUT34 OUT35 VPP VPP NC VSSSUB VSSP VSSP NC OUT36 OUT37 OUT38 TQFP100 (Top View) 5/17 3 STV7617, STV7617D, STV7617U PIN ASSIGNMENT (TQFP100) Pin Number TQFP100 Slug-dow n/ TQFP100 Slug-up TQFP100 No slug 88 88 34-35-41-42 34-35-41-42 Symbol Type Function VCC VPP Supply Supply 5 V Logic Supply High Voltage Supply of power outputs 78-79-97-98 30-31-44-45 78-79-97-98 30-31-32-45 VSSP Ground Ground of power outputs 46-81-82-94-95 83-93 32 77 to 48, 40 to 36, 46-81-82-94-95 83-93 44 99-100, 1 to 28, VSSLOG VSSSUB OUT1 to OUT 65 Ground Ground Output Logic Ground Substrate Ground Power Output 28 to 1, 100-99 91 90 89 87 86 85 84 92 29-33-43-47-80-96 36 to 40, 48 to 77 85 86 87 89 90 91 92 84 29-33-43-47-80-96 SOUT (SIN) CLK ST B BLK HIZ SIN (SOUT) SEL F/ R NC Output Input Input Input Input Input Input Input - Shift Register Data Output Clock of data shift register Latch of data to outputs Power Output Blanking Control Power Output High Impedance Control Shift Register Data Input Selection of number of power outputs Selection of shift direction Not connected PIN ASSIGNMENT (Power Outputs) Output Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 6/17 3 Pin Number Slug-dow n/ No slug 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 Output Slug-u p Number 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 18 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Number Slug-do wn/ No slug 55 54 53 52 51 50 49 48 40 39 38 37 36 28 27 26 25 24 23 22 21 20 Output Slug-up Number 21 22 23 24 25 26 27 28 36 37 38 39 40 48 49 50 51 52 53 54 55 56 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Pin Number Slug-down/ No slug 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 Slug-up 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 STV7617, STV7617D, STV7617U BLOCK DIAGRAM F/R SWITCH SEL CLK 65-BIT SHIFT REGISTER SIN (SOUT) P1 SOUT (SIN) P65 S1 S65 LATCH STB Q1 Q2 Q64Q65 VCC VCC BLK VSSS UB VCC VSSP HIZ VSSL OG VPP VSSP STV7617 VSSP VPP OUT1 OUT64 VPP OUT65 CIRCUIT DESCRIPTION The STV7617 contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (PDP). Data is shifted at each low to high transition of the (CLK) shift clock. After 64 or 65 shifts (depending on SEL) the first bit presented at (SIN) is available at the serial output (SOUT). This output can be used to cascade several drivers to perform any vertical resolution. CLK, STB, SIN and SOUT inputs are Smith trigger inputs. BLK and HIZ logical inputs are internally pulled to level ”1”. The maximum frequency of the shift clock is 8 MHz. Shift register outputs (P1, ... P65) are transferred from the shift register into the latch stage when the latch input (STB) is at low level. Table 1 : Output State Configuration STB * BLK L HIZ L L L H H * * L H H H L H Output State High impedance Inverted copy of input data Data latched Low level High Level Sustain current must not be sunk in the power outputs to VPP when the power supply is applied and output state is in HIZ or at high state. VSSSUB and VSSLOG must be connected as close as possible to the logical reference ground of the application. Table 2 : Shift Register Truth Table F/R H H L L CLK Rise L or H Rise L or H SIN In In Out Out SOUT Out Out In In Comments Forward Shift Steady Reverse Shift Steady Table 3 : Power Output Configuration SEL F/R Number of Outpu ts L L 64 L H 64 H H L H 65 65 Comments Out 1 is in Hi-Z mode (outputs 65 to 2 powered) Out 65 is in Hi-Z mode (outputs 1 to 64 powered) Out 65 to Out 1 powered Out 1 to Out 65 powered 7/17 3 STV7617, STV7617D, STV7617U ABSOLUTE MAXIMUM RATINGS Symbol VCC OUTi VIN V OUT VPOUT IPOUT IDOUT Tjmax Toper Tstg Parameter Logic Supply (Pin 88)* Output Pins (1 to 28, 36 to 40, 48 to 77, 99, 100) Logic Input Voltage (Pins 84, 86, 87, 89, 90, 91, 92)* Logic Output Voltage (Pin 85)* Driver Output Voltage (scanning mode) Driver Output Current (1) (4) Diode Output Current (3) (4) Junction Temperature Operating Temperature Storage Temperature Value -0.3, +7 -0.3, +100 -0.3, VCC +0.3 -0.3, VCC + 0.3 -0.3, +100 -100, +1 A ±700 +150 -20, +85 -20, +150 Unit V V V V V mA mA °C °C °C * In case of STV7617D THERMAL DATA Symbol Rth(j-a) Tjoper Rth(j-a) Parameter Junction-ambient Thermal Resistance (1) Maximum Operating Junction (1) Junction-ambient Thermal Resistance (5) Value 20 125 40 Unit °C/W °C °C/W Note 1 For TQFP100 packaging and slug soldered on printed circuit board. Note 2 Through one power output. Note 3 Through all power outputs (see test diagram): with Power dissipation lower or equal than Ptot and Junction temperature lower or equal than Tjmax and VPP = VSSP. Note 4 These parameters are measured during ST’s internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts. Note 5 TQFP soldered on 4 layers Printed Circuit Board. 8/17 3 STV7617, STV7617D, STV7617U ELECTRICAL CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, V SSSUB = 0 V, Tamb = 25°C, fCLK = 8 MHz, unless otherwise specified) Symbol SUPPLY VCC Parameter Min. Typ. ICCH Logic Supply Voltage 4.5 5 5.5 V Logic Supply Current - - 100 µA ICCL Logic Supply Current VPP Power Output Supply Voltage - 5 - mA 20 - 90 V IPPH Power Output Supply Current (steady outputs) - - 100 µA OUTPUT OUT1-OUT65 VPOUTH Power Output High Level Unit IPOUTH = - 20 mA 83 86 - V 30 33 - V - 2.5 5 V IPOUTL-P = 850 mA (6) - - 15 V Output Diode High Level IDOUTH = +400 mA (7) (8) - 1.7 5 V - -1.2 -5 V Power Output High Level VPOUTL Power Output Low Level VDOUTH fCLK = 8 MHz Max. I POUTH = - 15mA, V PP = 40 V IPOUTL = + 400 mA VPOUTH VPOUTL-P Test Condi tions Power Output Low Level-pulsed mode Output Diode Low Level IDOUTL = - 400 mA (7)(8) SOUT VOH Logic Output High Level I OH = -1 mA 4 4.2 - V VOL Logic Output Low Level IOL = +1 mA - 0.1 0.4 V 0.8 VCC - - V VDOUTL INPUT (CLK, STB, BLK, HIZ, SIN, SEL) VIH Input High Level VIL Input Low Level IIH High Level Input Current IIL Low Level Input Current CLK, SIN, STB, SEL, BLK, HIZ VIH = VCC VIL = 0 V - - 0.2VCC V - - 10 µA - - -10 -40 µA µA Note 6 Peak current - Pulse mode 720 Hz - 0.2%. Duty cycle - VCC = 5.5 V ± 0.2 V. Note 7 Compatible with power dissipation and Tjoper ≤ 125°C. Note 8 See test diagram page 12. 9/17 3 STV7617, STV7617D, STV7617U AC TIMING REQUIREMENTS (VCC = 4.5 V to 5.5 V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10 ns) Symbol Parameter Min. Typ. Max. Unit tWHCLK Duration of clock (CLK) pulse at high level 40 - - ns tWLCLK Duration of clock (CLK) pulse at low level 40 - - ns tSDAT Set-up Time of data input before clock (low to high) transition 10 - - ns tHDAT Hold Time of data input after clock (low to high) transition 20 - - ns tDSTB Minimum Delay to latch STB after clock (low to high) transition 25 - - ns tSSTB Set-up Time STB before clock (low to high) transition 10 - - ns tSTB Latch STB Low Level Pulse Duration 20 - - ns tBLK Blanking (BLK) Pulse Duration 500 - - ns tHIZ High Impedance HIZ Pulse Duration 500 - - ns AC TIMING CHARACTERISTICS (VCC = 5 V, VPP = 90 V, VSSP = 0 V, VSSLOG = 0 V, VSSSUB = 0 V, Tamb = 25°C, VILMax. = 0.2 Vcc, VIHMin. = 0.8 VCC, VOH = 4.0 V, VOL = 0.4 V, unless otherwise specified) Symbol Parameter tCLK Data Clock Period tRDAT tFDAT tPHL1 125 - - ns Logical Data Output Rise Time - 12 20 ns Logical Data Output Fall Time - 10 20 ns Delay of logic data output (high to low transition) after clock (CLK) transition (CL=10pF) Delay of logic data output (low to high transition) after clock (CLK) transition (CL=10 pF) - 37 50 ns - 42 60 ns tPHL2 tPLH2 Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition - 110 115 180 180 ns ns tPHL3 tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition - 80 95 165 165 ns ns tPHL4 tPLH4 Delay of power output change (high to low transition) to blank (BLK) transition Delay of power output change (low to high transition) to blank (BLK) transition - 75 75 160 160 ns ns tPHZ5 tPLZ5 Delay of power output change (high to Hi-Z transition) after high impedance (HIZ)(9) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ)(9) - 40 80 160 160 ns ns tPZH5 tPZL5 Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (9) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (9) - 75 40 160 160 ns ns tROUT Power Output Rise Time (10) - 175 350 ns tFOUT Power Output Fall Time (10) - 35 150 ns tPLH1 Note 9 See test diagram page 12. Note 10 One output among 64, loading capacitor COUT = 200pF, other outputs at low level. 10/17 3 Min. Typ. Max. Unit STV7617, STV7617D, STV7617U Figure 1: AC Characteristics Waveform tCLK tWHCLK tWLCLK ”1” CLK 50% 50% 50% ”0” tSDAT tHDAT ”1” SIN 50% 50% ”0” tFDAT tPHL1 ”1” 90% SOUT 90% 10% 10% ”0” tRDAT tPLH1 tSSTB tSTB tDSTB ”1” STB 50% 50% ”0” tPHL2 tPHL3 ”1” 90% OUTn 90% 10% 10% ”0” tPLH2 tPLH3 tBLK/POL ”1” HIZ (BLK = H) 50% 50% ”0” tPLH4 tPHL4 ”1” 90% OUTn 10% ”0” tHIZ ”1” HIZ (BLK = L) 50% 50% ”0” tROUT OUTn 90% 10% 90% 10% tFOUT tPHZ5 tPZH5 90% 10% 60% tPLZ5 tPZL5 40% ”1” ”0” 11/17 3 STV7617, STV7617D, STV7617U Figure 2: Test Configuration VPP=VSSP VPP=VSSP VDOUTH IDOUTH VDOUTL VSSP V SSP Output sinking current as positive value, sourcing current as negative value VPP OUT R VDOUT 12/17 3 VPP/2 IDOUTL STV7617, STV7617D, STV7617U INPUT/OUTPUT CHARACTERISTICS Figure 3: BLK, HIZ Input Figure 5: SIN, SOUT Input VCC VCC VCC VCC SIN, SOUT VCC BLK, HIZ GNDLOG GNDLOG GNDSUB GNDSUB Figure 4: F/R, SEL, CLK, STB Input Figure 6: Power Output VCC VCC VPP F/R, SEL CLK, STB OUT1 to OUT 65 GNDLOG GNDSUB VSSP 13/17 3 STV7617, STV7617D, STV7617U PACKAGE MECHANICAL DATA (SLUG-DOWN) 100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 S1 e 100 A1 76 0,075 mm 0.03 inch SEATING PLANE 75 B 1 S E3 E1 E H 51 25 c 50 L D3 D1 D L1 26 K Dimensions Min. Millimeters Typ. Max. 1.60 0.15 1.45 0.27 0.20 Min. A A1 0.05 0.002 A2 1.35 1.40 0.053 B 0.17 0.22 0.007 C 0.09 0.004 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 L 0.45 0.60 0.75 0.018 L1 1.00 K 0° (Min.), 7° (Max.) Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm H 9.85 S 8.80 0.346 S1 8.80 0.346 14/17 3 0,25 mm .010 inch GAGE PLANE Inches Typ. 0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039 0.388 Max. 0.063 0.006 0.057 0.011 0.008 0.030 STV7617, STV7617D, STV7617U PACKAGE MECHANICAL DATA (SLUG-UP) 100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 S1 e 100 A1 76 SEATING PLANE 75 B 1 0,075 mm 0.03 inch S E3 E1 E H 25 51 c 50 L D3 D1 D L1 26 0,25 mm .010 inch GAGE PLANE K Dimensions Millimeters Min. Typ. A Inches Max. Min. Typ. 1.60 Max. 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.055 0.006 0.057 B 0.17 0.22 0.27 0.007 0.009 0.011 C 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 D3 12.00 0.472 e 0.50 0.20 E 16.00 0.630 E1 14.00 0.551 E3 L 12.00 0.45 L1 0.60 0.472 0.75 0.018 1.00 K 0.024 0.030 0.039 0° (Min.), 7° (Max.) Slug Dimension For L/Frame Pad Size 10.00 x 10.00 mm H 9.85 0.388 S 8.80 0.346 S1 8.80 0.346 15/17 3 STV7617, STV7617D, STV7617U PACKAGE MECHANICAL DATA (NO SLUG) 100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) A A2 e 100 A1 76 0,075 mm 0.03 inch 75 25 51 SEATING PLANE E3 E1 E B 1 c 50 L D3 D1 D L1 26 0,25 mm .010 inch GAGE PLANE K Dimensions Millimeters Min. Typ. A Min. Typ. 1.60 Max. 0.063 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.17 0.22 0.27 0.007 0.009 0.011 C 0.006 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 D3 12.00 0.472 e 0.50 0.20 E 16.00 0.630 E1 14.00 0.551 E3 L L1 K 16/17 Inches Max. 12.00 0.45 0.60 0.472 0.75 0.018 1.00 0.024 0.039 0° (Min.), 7° (Max.) 0.030 STV7617, STV7617D, STV7617U Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change witho ut notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. 2000 STMicroelectronics - All Rights Reserved Purchase of I2C Components of STMicroelectronics, conveys a license under the Philip s I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philip s. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www .st.com 17/17 4