EMIF02-USB03F2 ® 2 LINES EMI FILTER INCLUDING ESD PROTECTION IPAD™ PRODUCT CHARACTERISTICS ESD protection and EMI filtering for: ■ USB OTG port DESCRIPTION The EMIF02-USB03F2 is a highly integrated array designed to suppress EMI / RFI noise for USB OTG (On The Go). The EMIF02-USB03F2 Flip-Chip packaging means the package size is equal to the die size. Additionally, this filter includes an ESD protection circuitry which prevents the protected device from destruction when subjected to ESD surges up to 15 kV on external contacts. Flip-Chip (11 Bumps) Figure 1: Pin Configuration (ball side) BENEFITS ■ 2 lines low-pass-filter + 2 lines ESD protection ■ High efficiency in EMI filtering ■ Lead Free package ■ Very low PCB space consuming: < 3.25 mm2 ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression (IEC61000-4-2 level 4) ■ High reliability offered by monolithic integration ■ High reducing of parasitic elements through ■ integration and wafer level packaging. COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2 Level 4 on external pins 15kV (air discharge) 8kV (contact discharge) Level 1 on internal pins 3 2 1 ID Dz Vbus Pup Pd1 B D+ out Pd2 D+ in C Dout GND Din D A Figure 2: Schematic 2kV (air and contact discharge) Pup Dz ID Vbus EMIF02-USB03F2 R3=1.3kΩ D+OUT D-OUT C R2=33Ω D+IN R1=33Ω D-IN C R5=15kΩ Table 1: Order Code Part Number EMIF02-USB03F2 R4=17kΩ Pd2 Marking FU Pd1 Cline = 20 pF max. TM: IPAD is a trademark of STMicroelectronics. October 2004 REV. 3 1/7 EMIF02-USB03F2 Table 2: Absolute Ratings (Tamb = 25°C)) Symbol Parameter and test conditions External pins (D1, C1, A2, A3, B3) ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge Value Unit 15 8 kV 2 2 125 - 40 to + 85 - 55 to + 150 °C °C °C VPP Internal pins (D3, C3, C2, B2, B1) ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharg Maximum junction temperature Operating temperature range Storage temperature range Tj Top Tstg Table 3: Electrical Characteristics (Tamb = 25°C) Symbol Parameter VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current Cline Input line capacitance per line Symbol VBR IRM Cline R1,R2 R3 R4 R5 Test conditions Min. 14 IR = 1 mA VRM = 3V @ 0V Tolerance ± 5% Tolerance ± 5% Tolerance ± 5% Tolerance ± 5% Typ. Max. 0.1 0.5 20 33 1.30 17 15 Figure 3: Application Schematic Vbus Vbus ID ID USB OTG Xceiver Pup ID Vbus EMIF02-USB03F2 R3=1.3kΩ D+ D- D+OUT R2=33Ω D+IN D-OUT R1=33Ω D-IN D+ C D- C R5=15kΩ R4=17kΩ GND GND Pd2 Pd1 R1 = R2 = 33 Ω Cline = 20 pF max. 2/7 Dz USB OTG connector 3.3V Unit V µA pF Ω kΩ kΩ kΩ EMIF02-USB03F2 Figure 4: Filtering measurements Figure 5: Analog crosstalk measurements EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004 0.00 0.00 dB dB -10.00 -10.00 -20.00 EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004 -30.00 -40.00 -20.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 -50.00 -100.00 -90.00 100.0k 1.0M 10.0M 100.0M 1.0G 100.0k f/Hz C1/C3 Line D1/D3 Line 1.0M C1/D3 Line Figure 6: ESD response to IEC61000-4-2 (+15kV air discharge) on one input V(in) and on one output (Vout) 10.0M 100.0M f/Hz 1.0G A2/A3 Line Figure 7: ESD response to IEC61000-4-2 (-15kV air discharge) on one input V(in) and on one output (Vout) Figure 8: Junction capacitance versus reverse voltage applied (typical values) C(pF) 20 18 16 14 12 10 8 6 4 2 V R (V) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 3/7 EMIF02-USB03F2 Figure 9: Aplac model C1 C3 Ls Rs Rbump Lbump Lbump Rbump Rs Ls Port2 Port1 50 50 A3 A2 B3 B2 B1 C2 D2 MODEL = D02_usb03_gnd MODEL = D02_usb03 bulk bulk bulk bulk bulk bulk bulk B2 B1 R_1k3 C3 C2 R_17k R_33R C1 D2 R_15k D3 R_33R Lbump D1 Rbump MODEL = D02_usb03 MODEL = D02_usb03 Cgnd Lgnd bulk bulk bulk Cbump Rsubump A2 B1 bulk C1 bulk D3 bulk Cbump Rsubump bulk bulk D1 Cbump Rsubump B3 bulk Cbump Rsubump Cbump Rsubump C3 bulk Cbump Rsubump Cbump Rsubump C2 Rgnd Cbump Rsubump bulk Cbump Rsubump B2 bulk Cbump Rsubump bulk A3 bulk Figure 10: Aplac parameters Ls 950pH Rs 150m R_33R 33 R_1k3 1.3k R_15k 15k R_17k 17k Cz_usb03 11pF Rs_usb03 1 Cz_usb03_gnd 220pF 4/7 Rs_usb03_gnd 0.9 Lgnd 50pH Rgnd 100m Cgnd 0.15pF Lbump 50pH Rbump 20m Cbump 2.4pF Rsubump 100m EMIF02-USB03F2 Figure 11: Order Code EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip-Chip x = 1: 500µm, Bump = 315µm = 2: Leadfree Pitch = 500µm, Bump = 315µm Figure 12: FLIP-CHIP Package Mechanical Data 650µm ± 65 315µm ± 50 2.07mm ± 50µm 500µm ± 50 500µm ± 50 1.57mm ± 50µm Figure 14: Foot Print Recommendations Figure 15: Marking 565 545 Copper pad Diameter : 250µm recommended, 300µm max. Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) E Solder stencil opening : 330µm recommended x x z y ww 100 230 Solder mask opening recommendation : 340µm min. for 300µm copper pad diameter 400 All dimensions in µm 5/7 EMIF02-USB03F2 Figure 14: Packing Dot identifying Pin A1 location 1.75 +/- 0.1 Ø 1.5 +/- 0.1 4 +/- 0.1 3.5 +/- 0.1 ST E xxz yww ST E xxz yww ST E xxz yww 8 +/- 0.3 0.73 +/- 0.05 4 +/- 0.1 User direction of unreeling All dimensions in mm Table 4: Ordering Information Ordering code Marking Package Weight Base qty Delivery mode EMIF02-USB03F2 FU Flip-Chip 4.5 mg 5000 Tape & reel 7” Note: More packing informations are available in the application note AN1235: “Flip-Chip: Package description and recommendations for use” AN1751: "EMI Filters: Recommendations and measurements" Table 5: Revision History 6/7 Date Revision 14-Oct-2004 1 First issue. Description of Changes 25-Oct-2004 2 Figure 13 on page 5: Flip-Chip marking dimensions updated. 27-Oct-2004 3 Minor layout update. No content change. EMIF02-USB03F2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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