STMICROELECTRONICS L4921

L4920
L4921

VERY LOW DROP ADJUSTABLE REGULATORS
..
..
..
.
.
VERY LOW DROP VOLTAGE
ADJUSTABLE OUTPUT VOLTAGE FROM
1.25V TO 20V
400mA OUTPUT CURRENT
LOW QUIESCENT CURRENT
REVERSE VOLTAGE PROTECTION
+ 60/ − 60V TRANSIENT PEAK VOLTAGE
PROTECTION
SHORT CIRCUIT PROTECTION WITH FOLDBACK CHARACTERISTICS
THERMAL SHUT-DOWN
DESCRIPTION
The L4920 and L4921 are adjustable voltage regulators with a verylow voltage drop (0.4V typ. at 0.4A
Tj = 25°C), low quiescent current and comprehensive on-chip protection.
Thesedevices are protectedagainst load dump and
field decay transients, polarity reversal and over
heating.
A foldbackcurrent limiter protectsagainstload short
circuits.
The outputvoltage is adjustablethrough an external
divider from 1.25V to 20V. The minimum operating
input voltage is 5.2V (TJ = 25°C).
Pentaw att
Minidip (4 + 4)
ORDERING NUMBERS : L4920 (Pentawatt)
L4921 (Minidip)
These regulators are designed for automotive, industrial and consumer applications where low consumption is particularly important.
In battery backup and standby applications the low
consumption of these devices extends battery life.
BLOCK DIAGRAM
June 2000
1/7
L4920/L4921
ABSOLUTE MAXIMUM RATINGS
Symbol
Vi
Parameter
DC Input Operating Voltage
DC Reverse Input Voltage
Transient Input Overvoltages:
Load Dump:
5ms ≤ trise ≤ 10ms
τf Fall time constant = 100ms
R SOURCE ≥ 0.5Ω
Field Decay:
5ms ≤ tfall ≤ 10ms, RSOURCE ≥ 10Ω
τf Rise time constant = 33ms
TJ, TSTG Junction and Storage Temperature Range
Value
Unit
35
V
– 55 to 150
°C
PIN CONNECTIONS (top view)
TEST AND APPLICATION CIRCUIT
C = 100µF is required for stability (ESR ≤ 3Ω over T range)
R2 = 6.2KΩ.
THERMAL DATA
Symbol
R th j-amb
Rth j-pins
Rth j-case
2/7
Parameter
Thermal Resistance Junction-ambient
Thermal Resistance Junction-pins
Thermal Resistance Junction-case
Max
Max
Max
Minidip
(4 + 4)
Pentawatt
80 °C/W
15 °C/W
–
60 °C/W
–
3.5 °C/W
L4920/L4921
ELECTRICAL CHARACTERISTICS (forVI =14.4V,TJ = 25°C, VO = 5V,CO = 100µF, unlessOtherwiseSpecified)
Symbol
Parameter
Test Condition
Operating Input Voltage
VO ≥ 4.5V, IO = 400mA
VREF
Reference Voltage
VREF ≤ VO < 4.5V, IO = 400mA
5.2V < VI < 26V
5mA ≤ IO ≤ 400mA (*)
∆V O
Line Regulation
VO + 1V < VI < 26V, VO ≥ 4.5V
IO = 5mA
∆V O
Load Regulation
5mA ≤ IO ≤ 400mA (*) VO ≥ 4.5V
VI
VD
IQ
IO
IOSC
Dropout Voltage
Quiescent Current
Max.
Unit
VO + 0.7
Min.
26
V
5.2
26
V
1.25
1.30
V
1
10
mV/V
1.20
Typ.
3
15
mV/V
IO = 10mA
IO = 150mA
IO = 400mA
0.05
0.2
0.4
0.4
0.7
V
V
V
IO = 0mA
VO + 1V < VI <26V
0.8
2
mA
IO = 400mA (*)
VO + 1V < VI <26V
65
90
mA
Maximal Output Current
800
Short Circuit Output Current (*)
350
mA
500
mA
(*) F oldback pr otection
ELECTRICAL CHARACTERISTICS (forVI = 14.4V,–40 ≤ TJ ≤ 125°C (note1), VO = 5V, CO = 100µF, unless
Otherwise Specified)
Symbol
VI
Parameter
Operating Input Voltage
Test Condition
VO ≥ 4.5V, IO = 400mA
Min.
Typ.
Max.
Unit
VO + 0.9
26
V
VREF ≤ VO < 4.5V, IO = 400mA
5.2
26
V
1.17
VREF
Reference Voltage
5.4V < VI < 26V
1.25
1.33
∆V O
Line Regulation
V
VO + 1.2V < VI < 26V, VO ≥ 4.5V
IO = 5mA
2
15
mV/V
∆V O
Load Regulation
5mA ≤ IO ≤ 400mA (*) VO ≥ 4.5V
5
25
mV/V
VD
Dropout Voltage
IO = 150mA
IO = 400mA
0.2
0.4
0.4
0.7
V
V
IQ
Quiescent Current
IO = 0mA
VO + 1.2V < VI <26V
1,2
3
mA
80
140
mA
IO = 400mA (*)
VO + 1.2V < VI <26V
IO
IOSC
Maximal Output Current
870
Short Circuit Output Current (*)
230
mA
500
mA
(*) Foldback protection.
N ote : 1. Design limits are guaranteed (but not 100% production tested) over the indicated temperatu re and supply voltage
ranges. These limits are not used to calculate outgoing quality levels.
3/7
L4920/L4921
Figure 1 : Output Voltage vs. Temperature.
Figure 2 : Foldback Current Limiting.
Figure 3 : Quiescent Current vs. Output Current
(Vo = 5V).
APPLICATION INFORMATION
1) The L4920 and L4921 have VREF ≅ 1.25V.Then
the output voltage can be set down to VREF but
Vi must be greater than 5.2V (Tj = 25°C).
2) As the regulator reference voltage source works
in closed loop, the reference voltagemay change
in foldbackcondition.
3) For applications with high Vl, the total power
dissipation of the device with respect to the ther-
4/7
mal resistance of the packagemay be limiting . The
total power dissipation is :
Ptot = Vi lq + (Vi - Vo) lo
A typical curve giving the quiescent current lq as a
function of the output current lo is shown in fig. 3.
L4920/L4921
mm
DIM.
MIN.
A
TYP.
inch
MAX.
MIN.
3.3
TYP.
MAX.
0.130
a1
0.7
B
1.39
1.65
0.055
0.065
B1
0.91
1.04
0.036
0.041
b
b1
0.028
0.5
0.38
0.020
0.5
D
0.015
0.020
9.8
0.386
E
8.8
0.346
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
7.1
0.280
I
4.8
0.189
L
Z
3.3
0.44
OUTLINE AND
MECHANICAL DATA
0.130
1.6
0.017
PowerMinidip
0.063
5/7
L4920/L4921
DIM.
A
C
D
D1
E
E1
F
F1
G
G1
H2
H3
L
L1
L2
L3
L4
L5
L6
L7
L9
M
M1
V4
MIN.
mm
TYP.
2.4
1.2
0.35
0.76
0.8
1
3.2
6.6
3.4
6.8
10.05
17.55
15.55
21.2
22.3
17.85
15.75
21.4
22.5
2.6
15.1
6
4.23
3.75
0.2
4.5
4
MAX.
4.8
1.37
2.8
1.35
0.55
1.19
1.05
1.4
3.6
7
10.4
10.4
18.15
15.95
21.6
22.7
1.29
3
15.8
6.6
MIN.
inch
TYP.
0.094
0.047
0.014
0.030
0.031
0.039
0.126
0.260
0.134
0.268
0.396
0.691
0.612
0.831
0.878
0.703
0.620
0.843
0.886
0.102
0.594
0.236
4.75 0.167
4.25 0.148
40° (typ.)
0.008
0.177
0.157
OUTLINE AND
MECHANICAL DATA
MAX.
0.189
0.054
0.110
0.053
0.022
0.047
0.041
0.055
0.142
0.276
0.409
0.409
0.715
0.628
0.850
0.894
0.051
0.118
0.622
0.260
0.187
0.167
Pentawatt V
L
L1
V3
V
V
V1
B
D
C
D1
L5
L2
V
M1
R
R
A
V
E
L8
R
M
V4
H2
L3
F
E
V4
H3 H1
G G1
Dia.
F1
L7
F
H2
V4
L6
L9
RESIN BETWEEN
LEADS
6/7
E1
L4920/L4921
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this
publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written
approval of STMicroelectronics.
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 2000 STMicroelectronics – Printed in Italy – All Rights Reserved
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