L6213 SOLENOID DRIVER + SWITCH MODE POWER SUPPLY ADVANCE DATA OPERATING SUPPLY VOLTAGE UP TO 46V 1A POWER SUPPLY (5V) 5A SOLENOID DRIVER PRECISE ON CHIP REFERENCE VOLTAGE DISCONTINUOUS MODE - FREQUENCY VARIABLE VERY HIGH EFFICIENCY 1Ω OUTPUT DMOS (SMPS) INTERNAL CURRENT LIMIT (SMPS SECTION) EXTERNALLY PROGRAMMABLE SOLENOID CURRENT RISING SLOPE EXTERNALLY PROGRAMMABLE FIXED HYSTERESIS CONTROL OPTIMIZED DMOS RDS ON FOR HIGH SIDE CHOPPING DESCRIPTION The L6213 is an IC containing a S.M.P.S. delivering 1A at a voltage of 5V and a section designed to drive a solenoid with a current up to 5A. The device is realized in BCD mixed technology, which combines isolated DMOS power transistor with CMOS and Bipolar circuits on the same chip. The SMPS section can deliver 1A DC with an out- MULTIPOWER BCD TECHNOLOGY Powerdip 16+2+2 put voltage of 5V, including current limiting, reset and power fail for microprocessor and thermal protection. The solenoid driver section is designed for high current applications like hammer driver in electronic typewriter. The solenoid output section contains a high side and a low side DMOS, which RDS ON are optimized for high side chopping. The current rising slope is externally programmable through an external capacitor. The level of hysteresis of the current can be changed through an external resistor. The device is supplied in Powerdip 16+2+2, and use the four center pins to conduct heat to the printed circuit. APPLICATION CIRCUIT November 1991 1/9 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6213 BLOCK DIAGRAM 2/9 L6213 ABSOLUTE MAXIMUM RATINGS Symbol Value Unit Supply Voltage 52 V VD; VOUT-UP Output Negative Voltage DC -1.3 V VS VD VOUT-DOWN Parameter Output Negative Voltage peak at t = 0.1µs f = 100KHz Output Positive Voltage DC Output Positive Voltage peak at t = 0.1µs f = 25KHz -5V V VS + 1.3 V VS + 5 V Output Negative Voltage peak at t = 0.1µs f = 25KHz -5 V PFP Input Voltage 25 V VO, Enable PIM Input Voltage 7 V Reset, PF Output Voltage 20 V CD, ISTP Input Voltage 5.5 V Out-Up Out-Down Output Current DC = 10% TON = 3.5ms 5.5 A -50 to 150 °C VOUT-UP Tstg Storage Temperature THERMAL DATA Symbol R th j-pins R th j-amb Description Thermal Resistance Junction-pins Thermal Resistance Junction-ambient Max. Max. Value Unit 14 60 °C/W °C/W PIN CONNECTION (Top view) 3/9 L6213 PIN DESCRIPTION Nr. Name 1 Out-Up 2 BSE 3 ENABLE Description Solenoid section upper DMOS output. Solenoid section upper DMOS bootstrap. A capacitor connected between pin 2 and pin 1 ensures the efficient driving of the solenoid section upper DMOS. Solenoid control input - TTL compatible. 4 +VS1 Unregulated voltage input - Solenoid section. 5, 6 GND Ground. 7 PF 8 PFP Power fail programming. A resistor divider connected to VPS changes the Power fail threshold levels. 9 CD Capacitor delay. A capacitor connected to this pin determines the Reset signal delay time td. Unregulated voltage input - SMPS sections. Power fail output, the saturation of PF is guaranteed if VPS exceed 3V. PF is at logic 1 a time T1 after RESET reached the high level. PF came back to logic 0 when VPS goes down under 18V. (see fig. 1) 10 VS2 11 VD Regulator output and diode voltage control. 12 BSA SMPS section DMOS bootstrap. A capacitor connected between pin 12 and pin 11 ensures efficient driving of SMPS DMOS. 13 RESET Reset output. The saturation of Reset is guaranteed if VPS exceeds 3V. The Reset output reaches the logic level 1 a time delay (set by capacitor CD) after VPS has reached a rising threshold voltage. Reset reaches 0 level when VPS goes down below folling threshold. 14 Vout Feed back input of the regulation loop. 15, 16 GND Ground. 17 R sense Connection for solenoid sensing resistor. 18 PIM Programming of solenoid current rising edge. An RC network connected to this pin determines the slope of the solenoid current rising edge. 19 ISTP Programming of solenoid current histeresys. 20 Out-Down Solenoid section lower DMOS output. ELECTRICAL CHARACTERISTICS (Refer to the application circuit, TJ =25°C, Iout Power Supply = 50mA, VPS from 12V to 46V; unless otherwise specified. Pin Symbol Parameter Test Condition Min. Typ. Max. Unit STEP-DOWN SECTION 10, 4 Vi Supply Voltage 14 Vo Output Voltage IO = 0.05 to 1A On State Drain Resistance TJ = 25°C; VPS = 15 to 46V R DS on 14 46 V 4.85 5.2 V 0.7 Ω V 0.56 10 th on Turn-on Threshold VPS Rising Fig. 1 10 12 10 th off Turn-off Threshold VPS Falling Fig. 1 10 12 V 10 IB Input Bias Current 15 mA 11 Ilim Static Current Limiting 3.4 A 2, 10 Ii Total Input Current ENABLE = 1, VPS = 46V, Iload = 0 13 mA 2, 10 Ii Total Input Current ENABLE = 1, VPS = 15V, Iload = 0 18 mA 11 tdp Protection Current Maximum Delay Time 1 µs toff Minimum Power off State 7.8 µs 4/9 2.2 VPS = 46V IO = 50mA 4.2 L6213 ELECTRICAL CHARACTERISTICS (continued) Pin Symbol Parameter Test Condition Min. Typ. Max. Unit POWER FAIL 10 VthR Rising Threshold Voltage PFP open Fig. 1 19.5 20 23 V 10 VthF Falling Threshold Voltage PFP open Fig. 1 16.6 18.1 19.5 V 10 ∆Vth Threshold Hysteresis PFP open Fig. 1 0.5 Divided Internal Current V 130 µA 8 IPFI 8 Vth-PFP Rising Threshold Voltage VPS = 24V 1.1 1.21 1.29 V 8 Vth-PFP Falling Threshold Voltage VPS = 24V 0.98 1.06 1.13 V 8 ∆Vth -PFP Threshold Hysteresis VPS = 24V 30 7 Vsat Output PF Saturation PF current = 2.5mA VPS = 3 to 46V 0.4 V 7 Ileak Output Leakage Current VPS = 46V VPF = 20V 50 µA 7 t1 Delay to Reset RESET High to PF high Delay Time (fig. 1) 0 1 µs 7 t2 Noise Immunity When VPS drops to 8V for a time from 0 to t2, PF must be at 1 logic level (fig. 2) 0 1 µs 7 t3 Noise Immunity When VPS drops to 17V for a time greater than t3, PF must be at 0 logic level (fig. 2) 4 9 Id Delay Source Current VD = 0 to 4.1V 70 9 Id Delay Sink Current VD = 4.3 to 2V 10 13 Vsat Output RESET Saturation RESET Current = 2.5mA VPS = 3 to 46V 0.4 V 13 Ileak Output Leakage Current VPS = 46V RD = 4 to 5V VRESET = 20V 50 µA 13 t4 Noise Immunity When VPS drops to 10V for a time greater than t4 RESET must be at 0 logic level (fig. 1) mV µs RESET 140 µA mA µs 4 SOLENOID CONTROL SECTION 18 Vsat Saturation Voltage ENABLE = 1 I PIM = 5mA 18 Ileak Leakage Current PIM = 0.2 to 2.5V ENABLE = 0 18 Vclamp Clamp Voltage 1.9 2 0.2 V +100 µA 2.1 V 17 Minimum Offset Threshold PIM = GND Vsens = 10mV ENABLE = 0 lower MOS must be in conduction 17 MAximum Offset Voltage PIM = GND Vse ns = 50mV ENABLE = 0 lower MOS must be open Static Voltage Limiting Threshold Vsens going from 0 to 0.6V PIM = 3V, the EMH DMOS goes to high resistance state when Vsens is within: (see Block Diagram) 17 Vsense 17 0.5 Maximum Delay Time 0.525 V 1 µs 4 µs EMH Ron OnStateDrain toSource Resistance Tj = 25°C, VPS 15 to 46V 0.35 0.45 Ω EML Ron OnStateDrain to SourceResistance Tj = 25°C, VPS 15 to 46V 0.28 0.4 Ω Vsense Hysteresis IST = Open IST = 0.75V IST = 3V 50 25 100 65 35 120 mV mV mV tp 17 0.475 Vsense Protection Time 2 35 15 80 5/9 L6213 Figure 1: Power Fail and Reset Static Operation. (PFP open) 6/9 L6213 Figure 2: Power Fail and Reset Noise Immunity and Dynamic Operation. 7/9 L6213 POWERDIP20 PACKAGE MECHANICAL DATA mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L Z 8/9 inch 3.30 0.130 1.27 0.050 L6213 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A. 9/9