L6225 DUAL DMOS FULL BRIDGE MOTOR DRIVER PRELIMINARY DATA ■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V ■ 2.8A PEAK CURRENT (1.4A DC) ■ RDS (ON) 0.73Ω TYP. VALUE @ Tj = 25 °C ■ CROSS CONDUCTION PROTECTION ■ THERMAL SHUTDOWN ■ OPERATING FREQUENCY UP TO 100KHz ■ HIGH SIDE OVER CURRENT PROTECTION ■ CMOS/TTL INPUT ■ INTRINSIC FAST FREE WHEELING DIODES ■ UNDER VOLTAGE LOCKOUT PowerDIP20 PowerSO20 SO20 (16+2+2) (16+2+2) ORDERING NUMBERS: L6225N TYPICAL APPLICATIONS ■ STEPPER MOTOR ■ DUAL OR QUAD DC MOTOR DESCRIPTION The L6225 is a dual full bridge driver for motor control applications manufactured with Multipower BCD technology which combines isolated DMOS power L6225PD L6225D transistors with CMOS and bipolar circuits on the same chip. The Logic Inputs are CMOS/TTL and µP compatible. The High Side switches are protected against unsafe over current conditions. Each full bridge is controlled by a separate Enable and has a sense pin for the current sense resistor insertion. Another feature is the thermal shutdown. The L6225 is assembled in PowerDIP20(16+2+2), PowerSO20 and SO20(16+2+2) packages. BLOCK DIAGRAM OUT1A GND SENSE A OUT2 A VS A VS A VS A VS A GND GND GND VBO OT ENA Logic & Drivers ENB IN1A IN2A Charg e Pump VCP IN1 B IN2B VS B VS B VS B OUT1 B SENSEB OUT2 B VS B March 2001 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice. 1/10 L6225 FUNCTIONAL BLOCK DIAGRAM Vboot Thermal Protection Voltage Regulator 10V Vboot VCP V SA Charge Pump Vboot Vboot 5V OUT1 A Over Current Detection 10V OUT2 A 10V EN A SENSE A Logic IN1 A IN2 A BIPOLAR STEPPER MOTOR BRIDGE A EN B VSB OUT1B OUT2 B IN1 B SENSE B IN2 B BRIDGE B ABSOLUTE MAXIMUM RATINGS Symbol VS Parameter Test conditio ns Supply Voltage Value Unit 60 V -0.3 to +7 V VIN,V EN Input and Enable Voltage Range V SENSE DC Sensing Voltage Range -1 to +4 V VBOOT Bootstrap Peak Voltage V S + 10 V IS(peak) Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection 3.55 A IS DC Supply Current (for each VS pin) 1.4 A VOD Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2 B, SENSEB 60 V -40 to 150 °C Tstg, TOP 2/10 Storage and Operating Temperature Range tPULSE < 1ms L6225 RECOMMENDED OPERATING CONDITIONS Symbol Parameter VS Supply Voltage VOD Differential Voltage Between VS A, OUT1A, OUT2A, SENSEA and VS B, OUT1B, OUT2B, SENSEB V SENSE MIN MAX Unit 12 52 V 52 V -6 -1 6 1 V V -0.1 5 V 1.4 A +125 °C 100 kHz Sensing voltage (pulsed tw<trr) (DC) Vref Vref Operating Voltage IOUT DC Output Current Tj Operating Junction Temperature fsw Switching Frequency -25 PIN CONNECTION (Top View) IN1A 1 20 ENA IN2A 2 19 VCP SENSEA 3 18 OUT2A OUT1A 4 17 VSA GND 5 16 GND 6 OUT1B GND 1 20 GND VSA 2 19 VSB OUT2A 3 18 OUT2B VCP 4 17 VBOOT GND ENA 5 16 ENB 15 GND IN1A 6 15 IN2B 7 14 VSB IN2A 7 14 IN1B SENSEB 8 13 OUT2B SENSEA 8 13 SENSEB IN1B 9 12 VBOOT OUT1A 9 12 OUT1B IN2B 10 11 ENB 10 11 GND D99IN1093A PowerDIP20/SO20 GND D99IN1092A PowerSO20 3/10 L6225 PIN DESCRIPTION Name PowerSO20 PowerDIP20/ SO20 V SA 2 17 Supply Voltage of the Bridge A. V SB 19 14 Supply Voltage of the Bridge B. This pin must be connected to VSA. OUT1A OUT2A 9 3 4 18 Bridge A outputs. OUT1B OUT2B 12 18 7 13 Bridge B outputs. SENSE A 8 3 Sense resistor for the bridge A SENSE B 13 8 Sense resistor for the bridge B GND 1,10,11,20 5, 6,15,16 Common ground terminals. In Powerdip and SO packages, these pins are also used for heat dissipation toward the PCB. EN A 5 20 Enable of the Bridge A. A LOW logic level applied to this pin switches off all the power DMOSs of the related bridge. The Bridge A over current protection open drain is internally connected to this pin. EN B 16 11 Enable of the Bridge B. A LOW logic level applied to this pin switches off all the power DMOSs of the related bridge. The Bridge B over current protection open drain is internally connected to this pin. IN1 A IN2 A 6 7 1 2 Logic inputs of the Bridge B. Provided the ENA signal is HIGH, a HIGH logic level applied to any of these pins switches on the related high side power DMOS, while a logic LOW switches on the related low side power DMOS . IN1 B IN2 B 14 15 9 10 Logic inputs of the Bridge B. Provided the ENB signal is HIGH, a HIGH logic level applied to any of these pins switches on the related high side power DMOS, while a logic LOW switches on the related low side power DMOS . VCP 4 19 Bootstrap Oscillator. Oscillator output for the external charge pump. VBOOT 17 12 Supply voltage to overdrive the upper DMOSs. Function THERMAL DATA Symbol Description PowerDIP20 SO20 PowerSO20 Unit 13 15 - °C/W - - 2 °C/W Rth-j-pins MaximumThermal Resistance Junction-Pins R th-j-case Maximum Thermal Resistance Junction-Case R th-j-amb1 MaximumThermal Resistance Junction-Ambient (1) 41 51 - °C/W R th-j-amb1 Maximum Thermal Resistance Junction-Ambient (2) - - 36 °C/W R th-j-amb1 MaximumThermal Resistance Junction-Ambient (3) - - 16 °C/W R th-j-amb2 Maximum Thermal Resistance Junction-Ambient (4) 57 78 63 °C/W (1) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm 2 (with a thickness of 35 µm). (2) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 µm). (3) Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 µm), 16 via holes and a ground layer. (4) Mounted on a multiplayer PCB without any heatsinking surface on the board. 4/10 L6225 ELECTRICAL CHARACTERISTICS(Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Parameter VS Supply Voltage IS Quiescent Supply Current Tj Thermal Shutdown Temperature Test Conditions Min Typ 8 All Bridges OFF; -25°C<Tj < 125 °C 5.5 Max Unit 52 V 10 mA °C 150 Output DMOS Transistors IDSS Leakage Current R DS(ON) High-side + Low-side Switch ON Resistance VS = 52V 1 mA Tj = 25 °C 1.47 1.69 Ω Tj =125 °C 2.35 2.7 Ω 1.2 V Source Drain Diodes VSD Forward ON Voltage ISD = 1.4A, EN = LOW trr Reverse Recovery Time If = 1.4A tfr Forward Recovery Time 300 ns 200 ns tD(on)EN Enable to out turn ON delay time (5) ILOAD = 1.4 A 250 ns tD(on)IN 600 ns Switching Rates tON Input to out turn ON delay time (5) 20 Output rise time(5) 105 300 ns tD(off)EN Enable to out turn OFF delay time (5) 450 ns Input to out turn OFF delay time (5) 500 ns tD(off)IN toff Output fall time (5) tdt Dead time protection fCP Charge pump frequency 20 78 300 ns µs 1 0.75 1 MHz 6.6 7 7.4 V 5.6 6 6.4 V UVLO comp V th(ON) Turn ON threshold Vth(OFF) Turn OFF threshold Logic Inpu t V INL Low level logic input voltage -0.3 0.8 V VINH High level logic input voltage 2 7 V IINH High level logic input current VIN, EN = 5 V 70 µA IINL Low level logic input current VIN, EN = GND -10 µA 3.55 A 0.4 V Over Current Protection IS OVER Input supply over current protection threshold VDIAG Open drain low level output voltage 2 I = 4 mA 2.8 (5) Resistive load used. See Fig. 1. 5/10 L6225 Figure 1. Switching rates definition En or IN 50 % t IOUT 90 % 10 % t tD(OFF) tOF F t D(ON) t(ON) CIRCUIT DESCRIPTION The L6225 is a dual full bridge IC designed to drive DC or stepper motors and other inductive loads. Each bridge has 4 power DMOS transistors with a typical RDS(ON) of 0.3 Ohm. Any of the 4 half bridges can be controlled independently by means of the 4 TTL/CMOS compatible inputs IN1A, IN2A, IN1B, IN2B, and 2 enable ENA, ENB . External connections are provided so that sensing resistor can be added for constant current chopping applicatio n. A non dissipative current sensing on the supply rails of the high side power DMOSs of each bridge, an internal reference and an internal open drain, with a pull down capability of 4mA (typical value), will pull to GND the ENABLE pin of the bridge under fault conditions, turning OFF all the four PowerDMOSs. This ensures a protection against short circuit to GND and between two phases of each of the two independent full bridges. By using an external R-C on the EN pins, the off time before recovering normal operation conditions after a fault can be easily programmed, by means of the accurate threshold of the logic inputs. Note that protection against short to the supply rail is typically provided by the external current control circuitry. The trip point of this protection is set at 2.8A (typ value). 6/10 L6225 DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T MIN. mm TYP. 0.1 0 0.4 0.23 15.8 9.4 13.9 MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547 1.27 11.43 10.9 inch TYP. 0.050 0.450 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10° (max.) 8° (max.) 5.8 0 15.5 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 10 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.394 PowerSO20 (1) ”D and F” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006”). - Critical dimensions: ”E”, ”G” and ”a3” N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane - C- S SEATING PLANE L G E2 E1 BOTTOM VIEW T E3 1 h x 45 7/10 10 PSO20MEC C (COPLANARITY) D1 L6225 mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L Z OUTLINE AND MECHANICAL DATA 3.30 0.130 1.27 Powerdip 20 0.050 8/10 L6225 mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 OUTLINE AND MECHANICAL DATA 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0° (min.)8° (max.) L h x 45° A B e A1 K H D 20 11 E 1 1 0 SO20MEC 9/10 C L6225 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. N o license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com 10/10