L6205 DMOS DUAL FULL BRIDGE DRIVER ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 5.6A OUTPUT PEAK CURRENT (2.8A DC) RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT PROTECTION PARALLELED OPERATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES TYPICAL APPLICATIONS ■ BIPOLAR STEPPER MOTOR ■ DUAL OR QUAD DC MOTOR DESCRIPTION The L6205 is a DMOS Dual Full Bridge designed for motor control applications, realized in MultiPower- PowerDIP20 (16+2+2) PowerSO20 SO20 (16+2+2) ORDERING NUMBERS: L6205N (PowerDIP20) L6205PD (PowerSO20) L6205D (SO20) BCD technology, which combines isolated DMOS Power Transistors with CMOS and bipolar circuits on the same chip. Available in PowerDIP20 (16+2+2), PowerSO20 and SO20(16+2+2) packages, the L6205 features a non-dissipative protection of the high side PowerMOSFETs and thermal shutdown. BLOCK DIAGRAM VBOOT VBOOT VBOOT VSA VBOOT CHARGE PUMP VCP OCDA OVER CURRENT DETECTION OUT1A 10V THERMAL PROTECTION OUT2A 10V GATE LOGIC ENA IN1A SENSEA IN2A VOLTAGE REGULATOR 10V 5V BRIDGE A OCDB OVER CURRENT DETECTION V SB OUT1B ENB OUT2B GATE LOGIC SENSEB IN1B IN2B BRIDGE B D99IN1091A September 2003 1/21 L6205 ABSOLUTE MAXIMUM RATINGS Symbol VS VOD VBOOT Parameter Test conditions Value Unit Supply Voltage VSA = VSB = VS 60 V Differential Voltage between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS = 60V; VSENSEA = VSENSEB = GND 60 V Bootstrap Peak Voltage VSA = VSB = VS VS + 10 V VIN,VEN Input and Enable Voltage Range -0.3 to +7 V VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB -1 to +4 V IS(peak) Pulsed Supply Current (for each VS pin), internally limited by the overcurrent protection VSA = VSB = VS; tPULSE < 1ms 7.1 A RMS Supply Current (for each VS pin) VSA = VSB = VS 2.8 A -40 to 150 °C IS Tstg, TOP Storage and Operating Temperature Range RECOMMENDED OPERATING CONDITIONS Symbol VS Parameter Test Conditions Supply Voltage VSA = VSB = VS VOD Differential Voltage Between VSA, OUT1A, OUT2A, SENSEA and VSB, OUT1B, OUT2B, SENSEB VSA = VSB = VS; VSENSEA = VSENSEB VSENSEA, VSENSEB Voltage Range at pins SENSEA and SENSEB (pulsed tW < trr) (DC) IOUT 2/21 MIN MAX Unit 8 52 V 52 V 6 1 V V 2.8 A +125 °C 100 KHz -6 -1 RMS Output Current Tj Operating Junction Temperature fsw Switching Frequency -25 L6205 THERMAL DATA Symbol Description Rth-j-pins MaximumThermal Resistance Junction-Pins Rth-j-case Maximum Thermal Resistance Junction-Case PowerDIP20 SO20 PowerSO20 Unit 12 14 - °C/W - - 1 °C/W 40 51 - °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2 - - 35 °C/W Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3 - - 15 °C/W Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4 56 77 62 °C/W (1) (2) (3) (4) 1 Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35µm). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm). Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes and a ground layer. Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board. PIN CONNECTIONS (Top View) IN1A 1 20 ENA GND 1 20 GND IN2A 2 19 VCP VSA 2 19 VSB SENSEA 3 18 OUT2A OUT2A 3 18 OUT2B OUT1A 4 17 VSA VCP 4 17 VBOOT GND 5 16 GND ENA 5 16 ENB GND 6 15 GND IN1A 6 15 IN2B OUT1B 7 14 VSB IN2A 7 14 IN1B SENSEB 8 13 OUT2B SENSEA 8 13 SENSEB IN1B 9 12 VBOOT OUT1A 9 12 OUT1B IN2B 10 11 ENB 10 11 GND GND D99IN1093A PowerDIP20/SO20 (5) D99IN1092A PowerSO20 (5) The slug is internally connected to pins 1,10,11 and 20 (GND pins). 3/21 L6205 PIN DESCRIPTION PACKAGE SO20/ PowerDIP20 PowerSO20 PIN # PIN # 1 Name Type Function 6 IN1A Logic Input Bridge A Logic Input 1. 2 7 IN2A Logic Input Bridge A Logic Input 2. 3 8 SENSEA Power Supply Bridge A Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 4 9 OUT1A Power Output Bridge A Output 1. 5, 6, 15, 16 1, 10, 11, 20 GND GND 7 12 OUT1B Power Output Bridge B Output 1. 8 13 SENSEB Power Supply Bridge B Source Pin. This pin must be connected to Power Ground directly or through a sensing power resistor. 9 14 IN1B Logic Input Bridge B Logic Input 1. 10 15 IN2B Logic Input Bridge B Logic Input 2. 11 16 ENB Logic Input (6) 12 17 VBOOT Supply Voltage 13 18 OUT2B Power Output Bridge B Output 2. 14 19 VSB Power Supply Bridge B Power Supply Voltage. It must be connected to the supply voltage together with pin VSA. 17 2 VSA Power Supply Bridge A Power Supply Voltage. It must be connected to the supply voltage together with pin VSB. 18 3 OUT2A Power Output Bridge A Output 2. 19 4 VCP Output 20 5 ENA Logic Input (6) Signal Ground terminals. In PowerDIP and SO packages, these pins are also used for heat dissipation toward the PCB. Bridge B Enable. LOW logic level switches OFF all Power MOSFETs of Bridge B. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. Bootstrap Voltage needed for driving the upper PowerMOSFETs of both Bridge A and Bridge B. Charge Pump Oscillator Output. Bridge A Enable. LOW logic level switches OFF all Power MOSFETs of Bridge A. This pin is also connected to the collector of the Overcurrent and Thermal Protection transistor to implement over current protection. If not used, it has to be connected to +5V through a resistor. (6) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a resistor with a value in the range of 2.2kΩ - 180KΩ, recommended 100kΩ 4/21 L6205 ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol Min Typ Max Unit VSth(ON) Turn-on Threshold 6.6 7 7.4 V VSth(OFF) Turn-off Threshold 5.6 6 6.4 V 5 10 mA IS Tj(OFF) Parameter Quiescent Supply Current Test Conditions All Bridges OFF; Tj = -25°C to 125°C (7) Thermal Shutdown Temperature °C 165 Output DMOS Transistors RDS(ON) High-Side Switch ON Resistance Tj = 25 °C Low-Side Switch ON Resistance IDSS Leakage Current 0.34 0.4 Ω Tj =125 °C (7) 0.53 0.59 Ω Tj = 25 °C 0.28 0.34 Ω Tj =125 °C (7) 0.47 0.53 Ω 2 mA EN = Low; OUT = VS EN = Low; OUT = GND -0.15 mA Source Drain Diodes Forward ON Voltage ISD = 2.8A, EN = LOW 1.15 trr Reverse Recovery Time If = 2.8A 300 ns tfr Forward Recovery Time 200 ns VSD 1.3 V Logic Input VIL Low level logic input voltage -0.3 0.8 V VIH High level logic input voltage 2 7 V IIL Low Level Logic Input Current GND Logic Input Voltage IIH High Level Logic Input Current 7V Logic Input Voltage Vth(ON) Turn-on Input Threshold Vth(OFF) Turn-off Input Threshold Vth(HYS) Input Threshold Hysteresis -10 µA 1.8 10 µA 2.0 V 0.8 1.3 V 0.25 0.5 V 100 250 Switching Characteristics tD(on)EN Enable to out turn ON delay time (8) ILOAD =2.8A, Resistive Load tD(on)IN Input to out turn ON delay time ILOAD =2.8A, Resistive Load (dead time included) Output rise time(8) ILOAD =2.8A, Resistive Load 40 Enable to out turn OFF delay time (8) ILOAD =2.8A, Resistive Load 300 tRISE tD(off)EN 400 1.6 550 ns µs 250 ns 800 ns 5/21 L6205 ELECTRICAL CHARACTERISTICS (continued) (Tamb = 25 °C, Vs = 48V, unless otherwise specified) Symbol tD(off)IN tFALL Parameter Test Conditions Input to out turn OFF delay time ILOAD =2.8A, Resistive Load Output Fall Time (8) ILOAD =2.8A, Resistive Load tdt Dead Time Protection fCP Charge pump frequency Min Typ Max 600 ns 40 0.5 -25°C<Tj <125°C Unit 250 1 ns µs 0.6 1 MHz 5.6 7.1 A 60 Ω Over Current Protection ISOVER Input Supply Overcurrent Protection Threshold Tj = -25°C to 125°C (7) ROPDR Open Drain ON Resistance I = 4mA 40 tOCD(ON) OCD Turn-on Delay Time (9) I = 4mA; CEN < 100pF 200 ns tOCD(OFF) OCD Turn-off Delay Time (9) I = 4mA; CEN < 100pF 100 ns (7) (8) (9) 4 Tested at 25°C in a restricted range and guaranteed by characterization. See Fig. 1. See Fig. 2. Figure 1. Switching Characteristic Definition EN Vth(ON) Vth(OFF) t IOUT 90% 10% t D01IN1316 tFALL tD(OFF)EN 6/21 tRISE tD(ON)EN L6205 Figure 2. Overcurrent Detection Timing Definition IOUT ISOVER ON BRIDGE OFF VEN 90% 10% tOCD(ON) tOCD(OFF) D02IN1399 7/21 L6205 CIRCUIT DESCRIPTION POWER STAGES and CHARGE PUMP The L6205 integrates two independent Power MOS Full Bridges. Each Power MOS has an Rdson=0.3ohm (typical value @ 25°C), with intrinsic fast freewheeling diode. Cross conduction protection is achieved using a dead time (td = 1µs typical) between the switch off and switch on of two Power MOS in one leg of a bridge. Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above the power supply voltage. The Bootstrapped (Vboot) supply is obtained through an internal Oscillator and few external components to realize a charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part numbers for the charge pump circuit are shown in Table1. Table 1. Charge Pump External Components Values CBOOT 220nF CP 10nF RP 100Ω D1 1N4148 D2 1N4148 (collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 5. If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are connected as shown in Fig. 6. The resistor REN should be chosen in the range from 2.2kΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF. More information on selecting the values is found in the Overcurrent Protection section. Figure 4. Logic Inputs Internal Structure 5V ESD PROTECTION D01IN1329 Figure 5. ENA and ENB Pins Open Collector Driving 5V 5V REN OPEN COLLECTOR OUTPUT ENA or ENB CEN Figure 3. Charge Pump Circuit D02IN1349 VS D1 Figure 6. ENA and ENB Pins Push-Pull Driving CBOOT D2 5V RP PUSH-PULL OUTPUT CP VCP VBOOT VSA VSB ENA or ENB CEN D01IN1328 LOGIC INPUTS Pins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and µC compatible logic inputs. The internal structure is shown in Fig. 4. Typical value for turn-on and turn-off thresholds are respectively Vthon=1.8V and Vthoff=1.3V. Pins ENA and ENB have identical input structure with the exception that the drains of the Overcurrent and thermal protection MOSFETs (one for the Bridge A and one for the Bridge B) are also connected to these pins. Due to these connections some care needs to be taken in driving these pins. The ENA and ENB inputs may be driven in one of two configurations as shown in figures 5 or 6. If driven by an open drain 8/21 REN D02IN1350 TRUTH TABLE INPUTS X OUTPUTS EN IN1 IN2 OUT1 OUT2 L X X High Z High Z H L L GND GND H H L Vs GND H L H GND Vs H H H Vs Vs = Don't care High Z = High Impedance Output L6205 NON-DISSIPATIVE OVERCURRENT PROTECTION The L6205 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 7 shows a simplified schematic of the overcurrent detection circuit. To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current in one bridge reaches the detection threshold (typically 5.6A) the relative OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. Figure 7. Overcurrent Protection Simplified Schematic OUT1A VSA OUT2A POWER SENSE 1 cell HIGH SIDE DMOSs OF THE BRIDGE A I1A POWER DMOS n cells TO GATE LOGIC µC or LOGIC POWER DMOS n cells POWER SENSE 1 cell + OCD COMPARATOR +5V I2A I1A / n I2A / n (I1A+I2A) / n REN CEN ENA INTERNAL OPEN-DRAIN RDS(ON) 40Ω TYP. IREF OVER TEMPERATURE D02IN1353 Figure 8 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN values and its magnitude is reported in Figure 9. The Delay Time tDELAY before turning off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 10. CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should be chosen according to the desired Disable Time. The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time. 9/21 L6205 Figure 8. Overcurrent Protection Waveforms IOUT ISOVER VEN VDD Vth(ON) Vth(OFF) VEN(LOW) ON OCD OFF ON tDELAY BRIDGE tDISABLE OFF tOCD(ON) tEN(FALL) tOCD(OFF) tD(OFF)EN 10/21 tEN(RISE) tD(ON)EN D02IN1400 L6205 Figure 9. tDISABLE versus CEN and REN (VDD = 5V). R EN = 2 20 kΩ 3 1 .1 0 R EN = 1 00 kΩ R EN = 4 7 kΩ R EN = 3 3 kΩ tDISABLE [µs] R EN = 1 0 kΩ 100 10 1 1 10 1 00 C E N [n F ] Figure 10. tDELAY versus CEN (VDD = 5V). tdelay [µs] 10 1 0.1 1 10 Cen [nF] 100 THERMAL PROTECTION In addition to the Ovecurrent Protection, the L6205 integrates a Thermal Protection for preventing the device destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value) with 15°C hysteresis (typ. value). 11/21 L6205 APPLICATION INFORMATION A typical application using L6205 is shown in Fig. 11. Typical component values for the application are shown in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power pins (VSA and VSB) and ground near the L6205 to improve the high frequency filtering on the power supply and reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is detected (see Overcurrent Protection). The two current sources (SENSEA and SENSEB) should be connected to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic pins (except ENA and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB. Table 2. Component Values for Typical Application C1 100uF D1 1N4148 C2 100nF D2 1N4148 CBOOT 220nF RENA 100kΩ CP 10nF RENB 100kΩ CENA 5.6nF RP 100Ω CENB 5.6nF Figure 11. Typical Application + VS 8-52VDC VSA C1 POWER GROUND - SIGNAL GROUND VSB C2 D1 CBOOT RP D2 VCP VBOOT SENSEB OUT1A OUT2A LOADB 14 19 20 ENA OUT1B OUT2B 11 ENABLEA ENB RENB ENABLEB CENB 12 3 8 9 10 1 4 18 2 16 7 15 13 6 5 IN1B IN2B IN1A IN2A GND GND GND GND D02IN1345 12/21 RENA CENA CP SENSEA LOADA 17 IN1B IN2B IN1A IN2A L6205 PARALLELED OPERATION The outputs of the L6205 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. It must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges. When the two halves of one full bridge (for example OUT1A and OUT2A) are connected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. In addition, the over current detection senses the sum of the current in the upper devices of each bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detection threshold. For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge 1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 12. The current in the two devices connected in parallel will share very well since the RDS(ON) of the devices on the same die is well matched. In this configuration the resulting Bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.15Ω Typ. Value @ TJ = 25°C - 5.6A max RMS Load Current - 11.2A OCD Threshold Figure 12. Parallel connection for higher current + VS 8-52VDC VSA VSB C2 C1 POWER GROUND - CBOOT 14 11 20 D1 SIGNAL GROUND 17 RP D2 VCP ENA REN EN CEN 19 CP VBOOT SENSEA SENSEB OUT1A OUT2A LOAD ENB OUT1B OUT2B 12 1 3 2 8 9 4 10 18 7 13 16 15 6 5 IN1A IN1 IN2A IN1B IN2B IN2 GND GND GND GND D02IN1359 To operate the device in parallel and maintain a lower over current threshold, Half Bridge 1 and the Half Bridge 2 of the Bridge A can be connected in parallel and the same done for the Bridge B as shown in Figure 13. In this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. This configuration, the resulting bridge has the following characteristics. - Equivalent Device: FULL BRIDGE - RDS(ON) 0.15Ω Typ. Value @ TJ = 25°C - 2.8A max RMS Load Current - 5.6A OCD Threshold 13/21 L6205 Figure 13. Parallel connection with lower Overcurrent Threshold + VS 8-52VDC VSA C1 17 VSB C2 POWER GROUND - D1 CBOOT SIGNAL GROUND RP D2 14 VCP 19 11 ENA ENB 12 SENSEA 1 3 SENSEB 2 8 OUT1A 4 OUT2A 18 OUT1B 7 OUT2B REN EN CEN CP VBOOT LOAD 20 9 10 16 15 6 13 5 IN1A IN2A INA IN1B INB IN2B GND GND GND GND D02IN1360 It is also possible to parallel the four Half Bridges to obtain a simple Half Bridge as shown in Fig. 14 The resulting half bridge has the following characteristics. - Equivalent Device: HALF BRIDGE - RDS(ON) 0.075Ω Typ. Value @ TJ = 25°C - 5.6A max RMS Load Current - 11.2A OCD Threshold Figure 14. Paralleling the four Half Bridges + VS 8-52VDC VSA C1 VSB C2 POWER GROUND - SIGNAL GROUND 14 11 20 D1 CBOOT 17 RP D2 VCP SENSEA SENSEB OUT1A OUT2A LOAD OUT1B OUT2B ENA 19 12 3 1 2 8 9 4 10 18 16 15 7 13 REN EN CEN CP VBOOT ENB 6 5 IN1A IN2A IN1B IN IN2B GND GND GND GND D02IN1366 14/21 L6205 OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION In Fig. 15 and Fig. 16 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types: – One Full Bridge ON at a time (Fig. 15) in which only one load at a time is energized. – Two Full Bridges ON at the same time (Fig. 16) in which two loads at the same time are energized. For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum). Figure 15. IC Power Dissipation versus Output Current with One Full Bridge ON at a time. ONE FULL BRIDGE ON AT A TIME IA 10 8 I OUT IB 6 PD [W] I OUT 4 Test Conditions: Supply Voltage = 24V 2 0 0 0.5 1 1.5 2 2.5 No PW M fSW = 30 kHz (slow decay) 3 I OUT [A] Figure 16. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time. TWO FULL BRIDGES ON AT THE SAME TIME IA 10 8 I OUT IB 6 I OUT PD [W ] 4 Test Conditions: Supply Voltage = 24V 2 0 0 0.5 1 1.5 I OUT [A ] 2 2.5 3 No PWM f SW = 30 kHz (slow decay) THERMAL MANAGEMENT In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be deliver by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking can be achieved using copper on the PCB with proper area and thickness. Figures 18, 19 and 20 show the Junction-toAmbient Thermal Resistance values for the PowerSO20, PowerDIP20 and SO20 packages. For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board with 6cm2 dissipating footprint (copper thickness of 35µm), the Rth j-amb is about 35°C/W. Fig. 17 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be reduced down to 15°C/W. 15/21 L6205 Figure 17. Mounting the PowerSO package. Slug soldered to PCB with dissipating area Slug soldered to PCB with dissipating area plus ground layer Slug soldered to PCB with dissipating area plus ground layer contacted through via holes Figure 18. PowerSO20 Junction-Ambient thermal resistance versus on-board copper area. ºC / W 43 38 33 W ith o ut G ro u nd La yer 28 W ith Gro un d La yer W ith Gro un d La yer+ 16 via H o le s 23 On-Board Copper Area 18 13 1 2 3 4 5 6 7 8 9 10 11 12 13 s q. cm Figure 19. PowerDIP20 Junction-Ambient thermal resistance versus on-board copper area. ºC / W On-Board Copper Area 42 41 Copper Area is on Bottom Side 40 Copper Area is on Top Side 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 s q . cm Figure 20. SO20 Junction-Ambient thermal resistance versus on-board copper area. On-Board Copper Area ºC / W 68 66 64 62 60 C o pp er A re a is o n T op S id e 58 56 54 52 50 48 1 2 3 4 5 6 7 s q. cm 16/21 8 9 10 11 12 L6205 Figure 21. Typical Quiescent Current vs. Supply Voltage Figure 24. Typical High-Side RDS(ON) vs. Supply Voltage Iq [m A] RDS(ON) [Ω] 5.6 fsw = 1kHz 0.380 Tj = 25°C 0.376 Tj = 85°C 5.4 0.372 Tj = 25°C 0.368 Tj = 125°C 0.364 5.2 0.360 0.356 5.0 0.352 0.348 4.8 0.344 0.340 0.336 4.6 0 10 20 30 V S [V] 40 50 0 60 5 10 15 20 25 30 VS [V] Figure 22. Normalized Typical Quiescent Current vs. Switching Frequency Figure 25. Normalized RDS(ON) vs.Junction Temperature (typical value) Iq / (Iq @ 1 kHz) R DS(ON) / (R DS(ON) @ 25 °C ) 1.7 1.8 1.6 1.6 1.5 1.4 1.4 1.3 1.2 1.2 1.1 1.0 1.0 0.8 0.9 0 20 40 60 80 0 100 20 40 60 80 100 120 140 Tj [°C] fSW [kHz] Figure 23. Typical Low-Side RDS(ON) vs. Supply Voltage Figure 26. Typical Drain-Source Diode Forward ON Characteristic R DS(ON) [Ω] ISD [A] 0.300 3.0 0.296 2.5 Tj = 25°C Tj = 25°C 0.292 2.0 0.288 1.5 0.284 1.0 0.280 0.5 0.276 0.0 700 0 5 10 15 V S [V] 20 25 30 800 900 1000 1100 1200 1300 VSD [mV] 17/21 L6205 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 0.013 c 0.23 0.32 0.009 D (1) 15.8 16 0.622 0.630 D1 9.4 9.8 0.370 0.386 E 13.9 14.5 0.547 0.570 e 1.27 e3 11.43 E1 (1) 10.9 0.450 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 h L 0.626 1.1 0.8 JEDEC MO-166 0.043 1.1 N Weight: 1.9gr 0.050 11.1 E2 OUTLINE AND MECHANICAL DATA MAX. 0.031 0.043 8˚ (typ.) S 8˚ (max.) T 10 0.394 PowerSO20 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 0056635 18/21 L6205 mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 24.80 0.976 E 8.80 0.346 e 2.54 0.100 e3 22.86 0.900 F 7.10 0.280 I 5.10 0.201 L OUTLINE AND MECHANICAL DATA 3.30 0.130 Powerdip 20 Z 1.27 0.050 19/21 L6205 mm inch OUTLINE AND MECHANICAL DATA DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0˚ (min.)8˚ (max.) L h x 45˚ A B e A1 K H D 20 11 E 1 0 1 SO20MEC 20/21 C L6205 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 21/21