STMICROELECTRONICS L6207

L6207
DMOS DUAL FULL BRIDGE DRIVER
WITH PWM CURRENT CONTROLLER
■
■
■
■
■
■
■
■
■
■
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
5.6A OUTPUT PEAK CURRENT (2.8A DC)
RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25 °C
OPERATING FREQUENCY UP TO 100KHz
NON DISSIPATIVE OVERCURRENT
PROTECTION
DUAL INDEPENDENT CONSTANT tOFF PWM
CURRENT CONTROLLERS
SLOW DECAY SYNCHRONOUS
RECTIFICATION
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOWN
UNDER VOLTAGE LOCKOUT
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■ BIPOLAR STEPPER MOTOR
■ DUAL DC MOTOR
DESCRIPTION
The L6207 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
PowerDIP24
(20+2+2)
PowerSO36
SO24
(20+2+2)
ORDERING NUMBERS:
L6207N (PowerDIP24)
L6207PD (PowerSO36)
L6207D (SO24)
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. The device also includes two independent constant off time PWM Current Controllers
that performs the chopping regulation. Available in
PowerDIP24 (20+2+2), PowerSO36 and SO24
(20+2+2) packages, the L6207 features a non-dissipative overcurrent protection on the high side Power
MOSFETs and thermal shutdown.
BLOCK DIAGRAM
VBOOT
VBOOT
VBOOT
VCP
VSA
VBOOT
CHARGE
PUMP
OCDA
OVER
CURRENT
DETECTION
OUT1A
10V
THERMAL
PROTECTION
OUT2A
10V
GATE
LOGIC
ENA
IN1A
SENSEA
IN2A
PWM
VOLTAGE
REGULATOR
10V
ONE SHOT
MONOSTABLE
MASKING
TIME
+
SENSE
COMPARATOR
5V
VREFA
RCA
BRIDGE A
OCDB
VSB
OVER
CURRENT
DETECTION
OUT1B
OUT2B
SENSEB
ENB
GATE
LOGIC
VREFB
RCB
IN1B
IN2B
BRIDGE B
D99IN1085A
September 2003
1/23
L6207
ABSOLUTE MAXIMUM RATINGS
Symbol
VS
VOD
VBOOT
Parameter
Test conditions
Value
Unit
Supply Voltage
VSA = VSB = VS
60
V
Differential Voltage between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS = 60V;
VSENSEA = VSENSEB = GND
60
V
Bootstrap Peak Voltage
VSA = VSB = VS
VS + 10
V
VIN,VEN
Input and Enable Voltage Range
-0.3 to +7
V
VREFA,
VREFB
Voltage Range at pins VREFA
and VREFB
-0.3 to +7
V
-0.3 to +7
V
-1 to +4
V
VRCA, VRCB Voltage Range at pins RCA and
RCB
VSENSEA,
VSENSEB
Voltage Range at pins SENSEA
and SENSEB
IS(peak)
Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
VSA = VSB = VS;
tPULSE < 1ms
7.1
A
RMS Supply Current (for each
VS pin)
VSA = VSB = VS
2.8
A
-40 to 150
°C
IS
Tstg, TOP
Storage and Operating
Temperature Range
RECOMMENDED OPERATING CONDITIONS
Symbol
VS
VOD
VREFA,
VREFB
VSENSEA,
VSENSEB
IOUT
2/23
Parameter
Test Conditions
Supply Voltage
VSA = VSB = VS
Differential Voltage Between
VSA, OUT1A, OUT2A, SENSEA and
VSB, OUT1B, OUT2B, SENSEB
VSA = VSB = VS;
VSENSEA = VSENSEB
Voltage Range at pins VREFA
and VREFB
Voltage Range at pins SENSEA
and SENSEB
(pulsed tW < trr)
(DC)
MIN
MAX
Unit
8
52
V
52
V
-0.1
5
V
-6
-1
6
1
V
V
2.8
A
+125
°C
100
KHz
RMS Output Current
Tj
Operating Junction Temperature
fsw
Switching Frequency
-25
L6207
THERMAL DATA
Symbol
Description
Rth-j-pins
Maximum Thermal Resistance Junction-Pins
Rth-j-case
Maximum Thermal Resistance Junction-Case
PowerDIP24
SO24
PowerSO36
Unit
18
14
-
°C/W
-
-
1
°C/W
43
51
-
°C/W
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient 2
-
-
35
°C/W
Rth-j-amb1
Maximum Thermal Resistance Junction-Ambient 3
-
-
15
°C/W
Rth-j-amb2
Maximum Thermal Resistance Junction-Ambient 4
58
77
62
°C/W
(1)
(2)
(3)
(4)
1
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the bottom side of 6cm2 (with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm).
Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm 2 (with a thickness of 35µm), 16 via holes
and a ground layer.
Mounted on a multi-layer FR4 PCB without any heat sinking surface on the board.
PIN CONNECTIONS (Top View)
IN1A
1
24
VREFA
IN2A
2
23
ENA
SENSEA
3
22
VCP
GND
1
36
GND
N.C.
2
35
N.C.
N.C.
3
34
N.C.
VSA
4
33
VSB
OUT2A
5
32
OUT2B
N.C.
6
31
N.C.
VCP
7
30
VBOOT
ENA
8
29
ENB
VREFA
9
28
VREFB
IN1A
10
27
IN2B
IN2A
11
26
IN1B
SENSEA
12
25
SENSEB
RCA
13
24
RCB
N.C.
14
23
N.C.
OUT1A
15
22
OUT1B
RCA
4
21
OUT2A
OUT1A
5
20
VSA
GND
6
19
GND
GND
7
18
GND
OUT1B
8
17
VSB
RCB
9
16
OUT2B
SENSEB
10
15
VBOOT
IN1B
11
14
ENB
N.C.
16
21
N.C.
IN2B
12
13
VREFB
N.C.
17
20
N.C.
GND
18
19
GND
D02IN1346
D02IN1347
PowerDIP24/SO24
(5)
PowerSO36 (5)
The slug is internally connected to pins 1,18,19 and 36 (GND pins).
3/23
L6207
PIN DESCRIPTION
PACKAGE
SO24/
PowerSO36
PowerDIP24
Name
Type
Function
PIN #
PIN #
1
10
IN1A
Logic input
Bridge A Logic Input 1.
2
11
IN2A
Logic input
Bridge A Logic Input 2.
3
12
SENSEA
Power Supply
4
13
RCA
RC Pin
5
15
OUT1A
Power Output
6, 7,
18, 19
1, 18,
19, 36
GND
GND
8
22
OUT1B
Power Output
9
24
RCB
RC Pin
10
25
SENSEB
Power Supply
11
26
IN1B
Logic Input
Bridge B Input 1
12
27
IN2B
Logic Input
Bridge B Input 2
13
28
VREFB
Analog Input
Bridge B Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
14
29
ENB
Logic Input (6)
Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
15
30
VBOOT
Supply
Voltage
16
32
OUT2B
Power Output
Bridge B Output 2.
17
33
VSB
Power Supply
Bridge B Power Supply Voltage. It must be connected to
the supply voltage together with pin VSA.
20
4
VSA
Power Supply
Bridge A Power Supply Voltage. It must be connected to
the supply voltage together with pin VSB.
21
5
OUT2A
Power Output
Bridge A Output 2.
22
7
VCP
Output
4/23
Bridge A Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge A.
Bridge A Output 1.
Signal Ground terminals. In Power DIP and SO packages,
these pins are also used for heat dissipation toward the
PCB.
Bridge B Output 1.
RC Network Pin. A parallel RC network connected
between this pin and ground sets the Current Controller
OFF-Time of the Bridge B.
Bridge B Source Pin. This pin must be connected to Power
Ground through a sensing power resistor.
Bootstrap Voltage needed for driving the upper Power
MOSFETs of both Bridge A and Bridge B.
Charge Pump Oscillator Output.
L6207
PIN DESCRIPTION (continued)
23
8
ENA
Logic Input (6)
Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
24
9
VREFA
Analog Input
Bridge A Current Controller Reference Voltage.
Do not leave this pin open or connect to GND.
(6)
Also connected at the output drain of the Over current and Thermal protection MOSFET. Therefore, it has to be driven putting in
series a resistor with a value in the range of 2.2KΩ - 180KΩ, recommended 100KΩ.
ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol
Min
Typ
Max
Unit
Turn-on Threshold
6.6
7
7.4
V
VSth(OFF) Turn-off Threshold
5.6
6
6.4
V
5
10
mA
VSth(ON)
IS
Tj(OFF)
Parameter
Quiescent Supply Current
Test Conditions
All Bridges OFF;
Tj = -25°C to 125°C (7)
Thermal Shutdown Temperature
°C
165
Output DMOS Transistors
RDS(ON)
High-Side Switch ON Resistance Tj = 25 °C
Low-Side Switch ON Resistance
IDSS
Leakage Current
0.34
0.4
Ω
Tj =125 °C (7)
0.53
0.59
Ω
Tj = 25 °C
0.28
0.34
Ω
Tj =125 °C (7)
0.47
0.53
Ω
2
mA
EN = Low; OUT = VS
EN = Low; OUT = GND
-0.15
mA
Source Drain Diodes
Forward ON Voltage
ISD = 2.8A, EN = LOW
1.15
trr
Reverse Recovery Time
If = 2.8A
300
ns
tfr
Forward Recovery Time
200
ns
VSD
1.3
V
Logic Input
VIL
Low level logic input voltage
-0.3
0.8
V
VIH
High level logic input voltage
2
7
V
IIL
Low Level Logic Input Current
GND Logic Input Voltage
IIH
High Level Logic Input Current
7V Logic Input Voltage
Vth(ON)
Turn-on Input Threshold
Vth(OFF)
Turn-off Input Threshold
Vth(HYS)
Input Threshold Hysteresis
-10
µA
1.8
10
µA
2.0
V
0.8
1.3
V
0.25
0.5
V
5/23
L6207
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
100
250
400
ns
Switching Characteristics
tD(on)EN
Enable to out turn ON delay time (8)
ILOAD =2.8A, Resistive Load
tD(on)IN
Input to out turn ON delay time
ILOAD =2.8A, Resistive Load
(dead time included)
Output rise time(8)
ILOAD =2.8A, Resistive Load
40
tD(off)EN
Enable to out turn OFF delay time (8) ILOAD =2.8A, Resistive Load
300
tD(off)IN
Input to out turn OFF delay time
ILOAD =2.8A, Resistive Load
Output Fall Time (8)
ILOAD =2.8A, Resistive Load
tRISE
tFALL
tdt
Dead Time Protection
fCP
Charge pump frequency
1.6
550
µs
250
ns
800
ns
600
40
0.5
-25°C<Tj <125°C
ns
250
1
0.6
ns
µs
1
MHz
PWM Comparator and Monostable
IRCA, IRCB Source Current at pins RCA and
RCB
Voffset
Offset Voltage on Sense
Comparator
tPROP
Turn OFF Propagation Delay (9)
tBLANK
Internal Blanking Time on
SENSE pins
tON(MIN)
tOFF
IBIAS
VRCA = VRCB = 2.5V
3.5
VREFA, VREFB = 0.5V
Minimum On Time
PWM Recirculation Time
5.5
mA
±5
mV
500
ns
1
µs
1.5
2
µs
ROFF = 20KΩ; COFF = 1nF
13
µs
ROFF = 100KΩ; COFF = 1nF
61
µs
Input Bias Current at pins VREFA
and VREFB
10
µA
5.6
7.1
A
60
Ω
Over Current Protection
ISOVER
Input Supply Overcurrent
Protection Threshold
Tj = -25°C to 125°C (7)
ROPDR
Open Drain ON Resistance
I = 4mA
40
tOCD(ON) OCD Turn-on Delay Time (10)
I = 4mA; CEN < 100pF
200
ns
tOCD(OFF) OCD Turn-off Delay Time (10)
I = 4mA; CEN < 100pF
100
ns
(7)
(8)
(9)
(10)
6/23
4
Tested at 25°C in a restricted range and guaranteed by characterization.
See Fig. 1.
Measured applying a voltage of 1V to pin SENSE and a voltage drop from 2V to 0V to pin VREF.
See Fig. 2.
L6207
Figure 1. Switching Characteristic Definition
EN
Vth(ON)
Vth(OFF)
t
IOUT
90%
10%
t
D01IN1316
tFALL
tD(OFF)EN
tRISE
tD(ON)EN
Figure 2. Overcurrent Detection Timing Definition
IOUT
ISOVER
ON
BRIDGE
OFF
VEN
90%
10%
tOCD(ON)
tOCD(OFF)
D02IN1399
7/23
L6207
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6207 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rdson =
0.3ohm (typical value @ 25°C), with intrinsic fast
freewheeling diode. Cross conduction protection is
achieved using a dead time (td = 1µs typical) between the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transistors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped
(VBOOT) supply is obtained through an internal Oscillator and few external components to realize a
charge pump circuit as shown in Figure 3. The oscillator output (VCP) is a square wave at 600kHz (typical) with 10V amplitude. Recommended values/part
numbers for the charge pump circuit are shown in
Table1.
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB inputs may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
REN and the capacitor CEN are connected as shown
in Fig. 6. The resistor REN should be chosen in the
range from 2.2kΩ to 180KΩ. Recommended values
for REN and CEN are respectively 100KΩ and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 4. Logic Inputs Internal Structure
5V
Table 1. Charge Pump External Components
Values
CBOOT
220nF
CP
10nF
RP
100Ω
D1
1N4148
D2
1N4148
ESD
PROTECTION
D01IN1329
Figure 5. ENA and ENB Pins Open Collector
Driving
Figure 3. Charge Pump Circuit
5V
VS
D1
OPEN
COLLECTOR
OUTPUT
CBOOT
D2
5V
REN
ENA or ENB
CEN
RP
D02IN1349
CP
VCP
VBOOT
VSA VSB
D01IN1328
LOGIC INPUTS
Pins IN1A, IN2B, IN1B and IN2B are TTL/CMOS and
uC compatible logic inputs. The internal structure is
shown in Fig. 4. Typical value for turn-on and turn-off
thresholds are respectively Vthon = 1.8V and Vthoff
= 1.3V.
Pins ENA and ENB have identical input structure with
the exception that the drains of the Overcurrent and
8/23
Figure 6. ENA and ENB Pins Push-Pull Driving
5V
PUSH-PULL
OUTPUT
REN
ENA or ENB
CEN
D02IN1350
L6207
TRUTH TABLE
INPUTS
OUTPUTS
Description (*)
EN
IN1
IN2
OUT1
OUT2
L
X
X
High Z
High Z
H
L
L
GND
GND
H
H
L
Vs
GND (Vs)
Forward
H
L
H
GND (Vs)
Vs
Reverse
H
H
H
Vs
Vs
Brake Mode (Upper Path)
Disable
Brake Mode (Lower Path)
X
= Don't care
High Z
= High Impedance Output
GND (Vs) = GND during Ton, Vs during Toff
(*) Valid only in case of load connected between OUT1 and OUT2
PWM CURRENT CONTROL
The L6207 includes a constant off time PWM current controller for each of the two bridges. The current control
circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected between the source of the two lower power MOS transistors and ground, as shown in Figure 7. As the current in
the load builds up the voltage across the sense resistor increases proportionally. When the voltage drop across
the sense resistor becomes greater than the voltage at the reference input (VREFA or VREFB) the sense comparator triggers the monostable switching the low-side MOS off. The low-side MOS remain off for the time set
by the monostable and the motor current recirculates in the upper path. When the monostable times out the
bridge will again turn on. Since the internal dead time, used to prevent cross conduction in the bridge, delays
the turn on of the power MOS, the effective off time is the sum of the monostable time plus the dead time.
Figure 7. PWM Current Controller Simplified Schematic
VSA (or B)
BLANKING TIME
MONOSTABLE
TO GATE LOGIC
1µs
FROM THE
LOW-SIDE
GATE DRIVERS
2H
5mA
S
Q
(0)
(1)
MONOSTABLE
RESET
1H
BLANKER
IOUT
R
OUT2A(or B)
DRIVERS
+
DEAD TIME
-
DRIVERS
+
DEAD TIME
OUT1A(or B)
+
5V
LOADA
(or B)
2.5V
SENSE
COMPARATOR
2L
1L
+
COMPARATOR
OUTPUT
RCA(or B)
C
R
-
SENSEA(or B)
VREFA(or B)
RSENSE
D02IN1352
Figure 8 shows the typical operating waveforms of the output current, the voltage drop across the sensing resistor, the RC pin voltage and the status of the bridge. Immediately after the low-side Power MOS turns on, a
high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. The
L6207 provides a 1µs Blanking Time tBLANK that inhibits the comparator output so that this current spike cannot
prematurely re-trigger the monostable.
9/23
L6207
Figure 8. Output Current Regulation Waveforms
IOUT
VREF
RSENSE
tON
tOFF
tOFF
1µs tBLANK
VSENSE
1µs tBLANK
VREF
Slow Decay
0
Slow Decay
tRCRISE
VRC
tRCRISE
5V
2.5V
tRCFALL
tRCFALL
1µs tDT
1µs tDT
ON
OFF
SYNCHRONOUS RECTIFICATION
D02IN1351
B
C
D
A
B
C
D
Figure 9 shows the magnitude of the Off Time tOFF versus COFF and ROFF values. It can be approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated Dead Time with:
20KΩ ≤ ROFF ≤ 100KΩ
0.47nF ≤ COFF ≤ 100nF
tDT = 1µs (typical value)
Therefore:
tOFF(MIN) = 6.6µs
tOFF(MAX) = 6ms
These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the Rise Time tRCRISE of the voltage at the pin RCOFF. The
Rise Time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the
monostable is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to
10/23
L6207
be bigger than tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON
can not be smaller than the minimum on time tON(MIN).
 t O N > t O N ( MIN ) = 1.5µ s (typ. value)

 t O N > t RCRISE – t DT
tRCRISE = 600 · COFF
Figure 10 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to
be said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller
than tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.
Figure 9. tOFF versus COFF and ROFF
4
1 .10
R off = 100kΩ
3
1 .10
R off = 47kΩ
toff [µs]
R off = 20kΩ
100
10
1
0.1
1
10
100
Coff [nF]
11/23
L6207
Figure 10. Area where tON can vary maintaining the PWM regulation.
ton(min) [µs]
100
10
1.5µs (typ. value)
1
0.1
1
10
100
Coff [nF]
SLOW DECAY MODE
Figure 11 shows the operation of the bridge in the Slow Decay mode. At the start of the off time, the lower power
MOS is switched off and the current recirculates around the upper half of the bridge. Since the voltage across
the coil is low, the current decays slowly. After the dead time the upper power MOS is operated in the synchronous rectification mode. When the monostable times out, the lower power MOS is turned on again after some
delay set by the dead time to prevent cross conduction.
Figure 11. Slow Decay Mode Output Stage Configurations
A) ON TIME
B) 1µs DEAD TIME
D01IN1336
12/23
C) SYNCHRONOUS
RECTIFICATION
D) 1µs DEAD TIME
L6207
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6207 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
circuit to ground or between two phases of the bridge. With this internal over current detection, the external current sense resistor normally used and its associated power dissipation are eliminated. Figure 12 shows a simplified schematic of the overcurrent detection circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference current IREF. When the output current in one bridge reaches the detection threshold (typically 5.6A) the relative
OCD comparator signals a fault condition. When a fault condition is detected, the EN pin is pulled below the turn
off threshold (1.3V typical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin, the off time before recovering normal operation can be easily programmed by means
of the accurate thresholds of the logic inputs.
Figure 12. Overcurrent Protection Simplified Schematic
OUT1A
VSA
OUT2A
POWER SENSE
1 cell
HIGH SIDE DMOSs OF
THE BRIDGE A
I1A
POWER DMOS
n cells
TO GATE
LOGIC
µC or LOGIC
POWER DMOS
n cells
POWER SENSE
1 cell
+
OCD
COMPARATOR
+5V
I2A
I1A / n
I2A / n
(I1A+I2A) / n
REN
CEN
ENA
INTERNAL
OPEN-DRAIN
RDS(ON)
40Ω TYP.
IREF
OVER TEMPERATURE
D02IN1353
Figure 13 shows the Overcurrent Detection operation. The Disable Time tDISABLE before recovering normal operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
CEN and REN values and its magnitude is reported in Figure 14. The Delay Time tDELAY before turning off the
bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in Figure 15.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN
should be chosen as big as possible according to the maximum tolerable Delay Time and the REN value should
be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2KΩ to 180KΩ. Recommended values for REN and CEN
are respectively 100KΩ and 5.6nF that allow obtaining 200µs Disable Time.
13/23
L6207
Figure 13. Overcurrent Protection Waveforms
IOUT
ISOVER
VEN
VDD
Vth(ON)
Vth(OFF)
VEN(LOW)
ON
OCD
OFF
ON
tDELAY
BRIDGE
tDISABLE
OFF
tOCD(ON)
tEN(FALL)
tOCD(OFF)
tD(OFF)EN
14/23
tEN(RISE)
tD(ON)EN
D02IN1400
L6207
Figure 14. tDISABLE versus C EN and REN (VDD = 5V).
R EN = 220 kΩ
3
1 .1 0
R EN = 1 00 k Ω
R EN = 4 7 kΩ
R EN = 3 3 kΩ
tDISABLE [µs]
R EN = 1 0 kΩ
1 00
10
1
1
10
100
C E N [n F ]
Figure 15. tDELAY versus CEN (VDD = 5V).
tdelay [µs]
10
1
0.1
1
10
Cen [nF]
100
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6207 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
15/23
L6207
APPLICATION INFORMATION
A typical application using L6207 is shown in Fig. 16. Typical component values for the application are shown
in Table 3. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VSA and VSB) and ground near the L6207 to improve the high frequency filtering on the power supply and
reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB
inputs to ground set the shut down time for the BrgidgeA and BridgeB respectively when an over current is detected (see Overcurrent Protection). The two current sensing inputs (SENSEA and SENSEB) should be connected to the sensing resistors with a trace length as short as possible in the layout. The sense resistors should be
non-inductive resistors to minimize the di/dt transients across the resistor. To increase noise immunity, unused
logic pins (except ENA and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see
pin description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Values for Typical Application
C1
100uF
D1
1N4148
C2
100nF
D2
1N4148
CA
1nF
RA
39KΩ
CB
1nF
RB
39KΩ
CBOOT
220nF
RENA
100KΩ
CP
10nF
RENB
100KΩ
CENA
5.6nF
RP
100Ω
CENB
5.6nF
RSENSEA
0.3Ω
CREFA
68nF
RSENSEB
0.3Ω
CREFB
68nF
Figure 16. Typical Application
+
VS
8-52VDC
VSA
C1
POWER
GROUND
-
SIGNAL
GROUND
VSB
C2
17
24
13
VREFA
RP
D2
VCP
RSENSEA
SENSEA
RSENSEB
SENSEB
OUT1A
OUT2A
LOADB
22
CP
VBOOT
LOADA
OUT1B
OUT2B
GND
GND
GND
GND
15
23
VREFB = 0-1V
14
CREFB
ENA
RENA
ENB
RENB
ENA
ENB
CENA
CENB
3
10
5
21
8
11
12
1
2
IN1B
4
IN1A
IN2A
CA
RCA
RA
CB
19
6
7
IN2B
IN1A
16
18
IN1B
IN2B
9
RCB
D02IN1343
16/23
VREFA = 0-1V
VREFB
CREFA
D1
CBOOT
20
RB
IN2A
L6207
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fig. 17 and Fig. 18 are shown the approximate relation between the output current and the IC power dissipation using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig.17) in which only one load at a time is energized.
– Two Full Bridges ON at the same time (Fig.18) in which two loads at the same time are energized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guarantee a safe operating junction temperature (125°C maximum).
Figure 17. IC Power Dissipation versus Output Current with One Full Bridge ON at a time.
ONE FULL BRIDGE ON AT A TIME
IA
10
8
I OUT
IB
6
PD [W]
I OUT
4
Test Conditions:
Supply Voltage = 24V
2
0
0
0.5
1
1.5
2
2.5
No PWM
fSW = 3 0 kHz (slow decay)
3
I OUT [A]
Figure 18. IC Power Dissipation versus Output Current with Two Full Bridges ON at the same time.
TWO FULL BRIDGES ON AT THE SAME TIME
IA
10
8
I OUT
IB
6
I OUT
PD [W ]
4
Test Conditions:
Supply Voltage = 24V
2
0
0
0.5
1
1.5
I OUT [A ]
2
2.5
3
No PWM
f SW = 30 kHz (slow decay)
THERMAL MANAGEMENT
In most applications the power dissipation in the IC is the main factor that sets the maximum current that can be delivered by the device in a safe operating condition. Therefore, it has to be taken into account very carefully. Besides
the available space on the PCB, the right package should be chosen considering the power dissipation. Heat sinking
can be achieved using copper on the PCB with proper area and thickness. Figures 20, 21 and 22 show the Junctionto-Ambient Thermal Resistance values for the PowerSO36, PowerDIP24 and SO24 packages.
For instance, using a PowerSO package with copper slug soldered on a 1.5 mm copper thickness FR4 board
with 6cm2 dissipating footprint (copper thickness of 35µm), the Rth j-amb is about 35°C/W. Fig. 19 shows mounting methods for this package. Using a multi-layer board with vias to a ground plane, thermal impedance can be
reduced down to 15°C/W.
17/23
L6207
Figure 19. Mounting the PowerSO package.
Slug soldered
to PCB with
dissipating area
Slug soldered
to PCB with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
Figure 20. PowerSO36 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
43
38
33
W ith o ut G ro u nd La yer
28
W ith Gro un d La yer
W ith Gro un d La yer+ 16 via
H o le s
23
On-Board Copper Area
18
13
1
2
3
4
5
6
7
8
9
10
11
12
13
s q. cm
Figure 21. PowerDIP24 Junction-Ambient thermal resistance versus on-board copper area.
ºC / W
On-Board Copper Area
49
48
C o p pe r Are a is o n Bo tto m
S id e
47
C o p pe r Are a is o n To p S i de
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
s q . cm
Figure 22. SO24 Junction-Ambient thermal resistance versus on-board copper area.
On-Board Copper Area
ºC / W
68
66
64
62
60
C o pp er A re a is o n T op S id e
58
56
54
52
50
48
1
2
3
4
5
6
7
s q. cm
18/23
8
9
10
11
12
L6207
Figure 23. Typical Quiescent Current vs.
Supply Voltage
Figure 26. Typical High-Side RDS(ON) vs.
Supply Voltage
Iq [m A]
RDS(ON) [Ω]
5.6
fsw = 1kHz
0.380
Tj = 25°C
0.376
Tj = 85°C
5.4
0.372
Tj = 25°C
0.368
Tj = 125°C
0.364
5.2
0.360
0.356
5.0
0.352
0.348
4.8
0.344
0.340
0.336
4.6
0
10
20
30
V S [V]
40
50
0
60
5
10
15
20
25
30
VS [V]
Figure 24. Normalized Typical Quiescent
Current vs. Switching Frequency
Figure 27. Normalized RDS(ON) vs.Junction
Temperature (typical value)
Iq / (Iq @ 1 kHz)
R DS(ON) / (R DS(ON) @ 25 °C )
1.7
1.8
1.6
1.6
1.5
1.4
1.4
1.3
1.2
1.2
1.1
1.0
1.0
0.8
0.9
0
20
40
60
80
0
100
20
40
60
80
100
120
140
Tj [°C]
fSW [kHz]
Figure 25. Typical Low-Side RDS(ON) vs.
Supply Voltage
Figure 28. Typical Drain-Source Diode
Forward ON Characteristic
R DS(ON) [Ω]
ISD [A]
0.300
3.0
0.296
2.5
Tj = 25°C
Tj = 25°C
0.292
2.0
0.288
1.5
0.284
1.0
0.280
0.5
0.276
0.0
700
0
5
10
15
V S [V]
20
25
30
800
900
1000
1100
1200
1300
VSD [mV]
19/23
L6207
DIM.
A
a1
a2
a3
b
c
D (1)
D1
E
e
e3
E1 (1)
E2
E3
E4
G
H
h
L
N
S
MIN.
mm
TYP.
0.10
0
0.22
0.23
15.80
9.40
13.90
MAX.
3.60
0.30
3.30
0.10
0.38
0.32
16.00
9.80
14.50
inch
TYP.
MIN.
0.004
0
0.008
0.009
0.622
0.370
0.547
0.65
11.05
10.90
0.0256
0.435
11.10 0.429
2.90
6.20 0.228
3.20 0.114
0.10
0
15.90 0.610
1.10
1.10 0.031
10°(max.)
8 °(max.)
5.80
2.90
0
15.50
0.80
OUTLINE AND
MECHANICAL DATA
MAX.
0.141
0.012
0.130
0.004
0.015
0.012
0.630
0.385
0.570
0.437
0.114
0.244
0.126
0.004
0.626
0.043
0.043
PowerSO36
(1): "D" and "E1" do not include mold flash or protrusions
- Mold flash or protrusions shall not exceed 0.15mm (0.006 inch)
- Critical dimensions are "a3", "E" and "G".
N
N
a2
e
A
DETAIL A
A
c
a1
DETAIL B
E
e3
H
DETAIL A
lead
D
slug
a3
36
BOTTOM VIEW
19
E3
B
E1
E2
D1
DETAIL B
0.35
Gage Plane
1
1
-C-
8
S
h x 45˚
20/23
b
⊕ 0.12
L
SEATING PLANE
G
M
AB
PSO36MEC
C
(COPLANARITY)
L6207
mm
DIM.
MIN.
TYP.
A
A1
inch
MAX.
MIN.
TYP.
4.320
0.380
A2
0.170
0.015
3.300
0.130
B
0.410
0.460
0.510
0.016
0.018
0.020
B1
1.400
1.520
1.650
0.055
0.060
0.065
c
0.200
0.250
0.300
0.008
0.010
0.012
D
31.62
31.75
31.88
1.245
1.250
1.255
E
7.620
8.260
0.300
e
2.54
E1
6.350
e1
L
6.600
M
0.325
0.100
6.860
0.250
0.260
0.270
0.300
7.620
3.180
OUTLINE AND
MECHANICAL DATA
MAX.
3.430
0.125
0.135
Powerdip 24
0˚ min, 15˚ max.
E1
A2
A
A1
L
B
B1
e
e1
D
24
13
c
1
12
M
SDIP24L
21/23
L6207
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
15.20
15.60
0.598
0.614
E
7.40
7.60
0.291
0.299
e
1.27
10.0
10.65
0.394
0.419
h
0.25
0;75
0.010
0.030
L
0.40
1.27
0.016
0.050
ddd
Weight: 0.60gr
0.050
H
k
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO24
0070769 C
22/23
L6207
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2003 STMicroelectronics - All rights reserved
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23/23