LNBS21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I2C INTERFACE
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COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
SUITS WIDELY ACCEPTED STANDARDS
FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING
BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM
LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
CABLE LENGTH DIGITAL COMPENSATION
INTERNAL OVER TEMPERATURE
PROTECTION
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBS21 is a
monolithic voltage regulator and interface IC,
PowerSO-20
assembled in PowerSO-20, specifically designed
to provide the power and the 13/18V, 22KHz tone
signalling to the LNB downconverter in the
antenna or to the multiswitch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I2CTM
standard interfacing.
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
SCHEMATIC DIAGRAM
LNBS21
Gate
LT1
Sense
Step-up
Controller
Feedback
LT2
Vup
Vcc
OUT
Preregul.+
U.V.lockout
Byp
+P.ON res.
Enable
I Select
V Select
Linear Post-reg
+Modulator
+Protections
SDA
SCL
ADDR
DSQIN
November 2002
EXTM
Diagnostics
I²C
interf.
DETIN
22KHz
Oscill.
Tone
Detector
DSQOUT
1/19
LNBS21
post-regulator to work at a minimum dissipated
power. An UnderVoltage Lockout circuit will
disable the whole circuit when the supplied VCC
drops below a fixed threshold (6.7V typically). The
internal 22KHz tone generator is factory trimmed
in accordance to the standards, and can be
controlled either by the I2CTM interface or by a
dedicated pin (DSQIN) that allows immediate
DiSEqCTM data encoding (*). All the functions of
this IC are controlled via I2CTM bus by writing 6
bits on the System Register (SR, 8 bits) . The
same register can be read back, and two bits will
report the diagnostic status. When the IC is put in
Stand-by (EN bit LOW), the power blocks are
disabled and the loop-through switch between
LT1 and LT2 pins is closed, thus leaving all LNB
powering and control functions to the Master
Receiver (**). When the regulator blocks are
active (EN bit HIGH), the output can be logic
controlled to be 13 or 18 V (typ.) by mean of the
VSEL bit (Voltage SELect) for remote controlling
of non-DiSEqC LNBs. Additionally, it is possible
to increment by 1V (typ.) the selected voltage
value to compensate for the excess voltage drop
along the coaxial cable (LLC bit HIGH). In order to
minimise the power dissipation, the output voltage
of the internal step-up converter is adjusted to
allow the linear regulator to work at minimum
dropout. Another bit of the SR is addressed to the
remote control of non-DiSEqC LNBs: the TEN
(Tone ENable) bit. When it is set to HIGH, a
continuous 22KHz tone is generated regardless
of the DSQIN pin logic status. The TEN bit must
be set LOW when the DSQIN pin is used for
encoding. The fully bi-directional
DiSEqCTM
DiSEqCTM interfacing is completed by the built-in
22KHz tone detector. Its input pin (DETIN) must
be AC coupled to the DiSEqCTM bus, and the
extracted PWK data are available on the
DSQOUT pin (*).
The current limitation block has two thresholds
that can be selected by the ISEL bit of the SR; the
lower threshold is between 650 and 900mA
(ISEL=HIGH), while the higher threshold is
between 750 and 1000mA (ISEL=LOW).
In order to improve design flexibility and to allow
implementation of newcoming LNB remote control
standards, an analogic modulation input pin is
available (EXTM). An appropriate DC blocking
capaci-tor must be used to couple the modulating
signal source to the EXTM pin. When external
modulation is not used, the relevant pin can be left
open.
This IC is also protected against overheating:
when the junction temperature exceeds 150°C
(typ.), the step-up converter and the linear
regulator are shut off, the loop-trough switch is
opened, and the OTF bit of the SR is set to HIGH.
Normal operation is resumed and the OTF bit is
reset to LOW when the junction is cooled down to
140°C (typ.).
The current protection block is SOA type. This
limits the short circuit current (Isc) typically at
300mA with ISEL=HIGH and at 400mA with
ISEL=LOW when the output port is connected to
ground.
It is possible to set the Short Circuit Current
protection either statically (simple current clamp)
or dy-namically by the PCL bit of the SR; when
the PCL (Pulsed Current Limiting) bit is set to
LOW, the overcurrent protection circuit works
dynamically: as soon as an overload is detected,
the output is shut-down for a time toff, typically
900ms. Simultaneously the OLF bit of the System
Register is set to HIGH. After this time has
elapsed, the output is resumed for a time ton=1/
10toff (typ.). At the end of ton, if the overload is still
detected, the protection circuit will cycle again
through Toff and Ton. At the end of a full Ton in
which no overload is detected, normal operation is
resumed and the OLF bit is reset to LOW. Typical
Ton+Toff time is 990ms and it is determined by an
internal timer. This dynamic operation can greatly
reduce the power dissipation in short circuit
condition, still ensuring excellent power-on start
up in most conditions (**) .
However, there could be some cases in which an
highly capacitive load on the output may cause a
difficult start-up when the dynamic protection is
chosen. This can be solved by initiating any power
start-up in static mode (PCL=HIGH) and then
switching to the dynamic mode (PCL=LOW) after
a chosen amount of time. When in static mode,
the OLF bit goes HIGH when the current clamp
limit is reached and returns LOW when the
overload condition is cleared.
(*): External components are needed to comply to bi-directional DiSEqCTM bus hardware require-ments. Full compliance of the whole application to DiSEqCTM specifications is not implied by the use of this IC.
(**): The current limitation circuit has no effect on the loop-through switch. When EN bit is LOW, the current flowing from LT1 to LT2 must
be externally limited.
2/19
LNBS21
ORDERING CODES
TYPE
PowerSO-20
(Tube)
PowerSO-20
(Tape & Reel)
LNBS21
LNBS21PD
LNBS21PD-TR
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
VCC
DC Input Voltage
Parameter
16
V
VUP
DC Input Voltage
25
V
VLT1, VLT2 DC Input Voltage
20
V
Internally Limited
mA
IO
Output Current
VO
DC Output Pin Voltage
-0.3 to 22
V
VI
Logic Input Voltage (SDA, SCL, DSQIN)
-0.3 to 7
V
Detector Input Signal Amplitude
2
VPP
Logic High Output Voltage (DSQOUT)
7
V
VDETIN
VOH
ILT
Bypass Switch ON Current
900
mA
VLT
Bypass Switch OFF Voltage
±20
V
IGATE
VSENSE
Gate Current
Current Sense Voltage
VADDRESS Address Pin Voltage
±400
mA
-0.3 to 1
V
-0.3 to 7
V
Tstg
Storage Temperature Range
-40 to +150
°C
Top
Operating Junction Temperature Range
-40 to +125
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is
not implied.
THERMAL DATA
Symbol
Rthj-case
Parameter
Thermal Resistance Junction-case
PowerSO-20
Unit
2
°C/W
PIN CONFIGUARATION (top view)
PowerSO-20
3/19
LNBS21
TABLE A: PIN CONFIGURATIONS
SYMBOL
VCC
NAME
Supply Input
GATE
Exrernal Switch Gate
SENSE
Current Sense Input
Vup
Step-up Voltage
OUT
Output Port
SDA
Serial Data
SCL
Serial Clock
DSQIN
DiSEqC Input
DETIN
Detector In
DSQOUT DiSEqC Output
EXTM
Extrernal Modulator
GND
Ground
BYP
LT1
Bypass Capacitor
Loop Through Switch
LT2
ADDR
Loop Through Switch
Address Setting
4/19
FUNCTION
8V to 15V supply. A 220µF bypass capacitor to
GND with a 470nF (ceramic) in parallel is
recommended
External MOS switch Gate connection of the
step-up converter
Current Sense comparator input. Connected to
current sensing resistor
Input of the linear post-regulator. The voltage on this
pin is monitored by internal step-ut controller to
keep a minimum dropout across the linear pass
transistor
Output of the linear post regulator modulator to the
LNB. See truth table for voltage selections.
Bidirectional data from/to I2C bus.
I2C
Clock from
bus.
When the TEN bit of the System Register is LOW,
this pin will accept the DiSEqC code from the main
µcontroller. The LNBS21 will use this code to
modulate the internally generated 22kHz carrier. Set
to GND thi pin if not used.
22kHz Tone Detector Input. Must be AC coupled to
the DiSEcQ bus.
Open collector output of the tone Detector to the
main µcontroller for DiSEcQ data decoding. It is
LOW when tone is detected.
External Modulation Input. Need DC decoupling to
the AC source. If not used, can be left open.
Circuit Ground. It is internally connected to the die
frame for heat dissipation.
Needed for internal preregulator filtering
In standby mode the power switch between LT1
and LT2 is closed. Max allowed current is 900mA.
this pin can be left open if loopthrough function is
not needed.
Same as above
2
Four I C bus addresses available by setting the
Address Pin level voltage
PIN NUMBER
vs PACKAGE
18
17
16
19
2
12
13
14
9
15
5
1, 10, 11, 20
8
4
3
7
LNBS21
TYPICAL APPLICATION CIRCUIT
D1 1N4001
IC1
Master STB
LT1
Vup
C2
220µF
C3
470nF
C7
10nF
Ceramic
Schottky
diode
STPS3L40S
or 1N5821
LT2
270µH
to LNB
Gate
MOSFET
STN4NF03L
Vout
C8
10nF
LNBS21
Sense
L1=22µH
D2
BAT43
15 ohm
(**) see note
DETIN(*)
C6
10nF
Rsc
0.05 Ω
Byp
C5
470nF
Vcc
Vin
12V
C1
220µF
C4
470nF
Ceramic
EXTM
DSQIN(*)
ADDRESS
SCL
SDA
GND
0<Vaddr<VByp
DSQOUT
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqCTM 2.0, not needed if bidirectional DiSEqCTM 2.0 is
not implemented (see DiSEqC implementation note)
I2C BUS INTERFACE
Data transmission from main µP to the LNBS21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBS21) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBS21 won't gen-erate the acknowledge if
the Vcc supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBS21, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
5/19
LNBS21
Figure 1 : DATA VALIDITY ON THE I2C BUS
Figure 2 : TIMING DIAGRAM ON I2C BUS
Figure 3 : ACKNOWLEDGE ON I2C BUS
6/19
LNBS21
LNBS1 SOFTWARE DESCRIPTION
INTERFACE PROTOCOL
- A chip address byte = hex 10 / 11 (the LSB bit
determines read(=1)/write(=0) transmission)
- A sequence of data (1 byte + acknowledge)
- A stop condition (P)
The interface protocol comprises:
- A start condition (S)
CHIP ADDRESS
MSB
0
S
0
0
1
0
DATA
0
LSB
MSB
R/W ACK
0
LSB
ACK
P
ACK= Acknowledge
S= Start
P= Stop
R/W= Read/Write
SYSTEM REGISTER (SR, 1 BYTE)
MSB
R, W
PCL
R, W
ISEL
R, W
TEN
R, W
LLC
R, W
VSEL
R, W
EN
R
OTF
LSB
R
OLF
R,W= read and write bit
R= Read-only bit
All bits reset to 0 at Power-On
TRANSMITTED DATA (I2C BUS WRITE MODE)
When the R/W bit in the chip address is set to 0,
the main µP can write on the System Register
(SR) of the LNBS21 via I2C bus. Only 6 bits out of
PCL
ISEL
TEN
LLC VSEL
EN
OTF
OLF
0
0
1
X
X
VOUT=13V, VUP=16V Loopthrough switch open
0
1
1
X
X
VOUT=18V, VUP=21V Loopthrough switch open
1
0
1
X
X
VOUT=14V, VUP=17V Loopthrough switch open
1
1
0
1
0
1
X
the 8 available can be written by the µP, since the
re-maining 2 are left to the diagnostic flags, and
are read-only.
Function
1
X
X
VOUT=19V, VUP=22V Loopthrough switch open
1
1
X
X
X
X
0
1
X
X
22KHz tone is controlled by DSQIN pin
22KHz tone is ON, DSQIN pin disabled
IOUT(min)=750mA, IOUT(max)=1A ISC=300mA
1
1
X
X
IOUT(min)=600mA, IOUT(max)=900mA ISC=300mA
X
1
1
0
X
X
X
X
X
X
Pulsed (dynamic) current limiting is selected
Static current limiting is selected
Power blocks disabled, Loopthrough switch closed
X
X
X
X= don't care.
Values are typical unless otherwise specified
RECEIVED DATA (I2C bus READ MODE)
The LNBS21 can provide to the Master a copy of
the SYSTEM REGISTER information via I2C bus
in read mode. The read mode is Master activated
by sending the chip address with R/W bit set to 1.
At the following master generated clocks bits, the
LNBS21 issues a byte on the SDA data bus line
(MSB transmitted first).
At the ninth clock bit the MCU master can:
- acknowledge the reception, starting in this way
the transmission of another byte from the
LNBS21;
7/19
LNBS21
- no acknowledge, stopping the read mode
communication.
PCL
ISEL
TEN
LLC VSEL
EN
OTF
OLF
Function
TJ<140°C, normal operation
0
These bits are read exactly the same as
they were left after last write operation
While the whole register is read back by the µP,
only the two read-only bits OLF and OTF convey
di-agnostic informations about the LNBS21.
TJ>150°C, power block disabled, Loothrough switch open
1
0
IOUT<IOMAX, normal operation
1
IOUT>IOMAX, overload protection triggered
Values are typical unless otherwise specified
POWER-ON I2C INTERFACE RESET
The I2C interface built in the LNBS21 is
automatically reset at power-on. As long as the
Vcc stays be-low the UnderVoltage Lockout
threshold (6.7V typ.), the interface will not respond
to any I2C com-mand and the System Register
(SR) is initialised to all zeroes, thus keeping the
power blocks disabled. Once the Vcc rises above
7.3V, the I2C interface becomes operative and the
SR can be configured by the main µP. This is due
to About 500mV of hysteresis provided in the UVL
threshold to avoid false retriggering of the
Power-On reset circuit.
DiSEqCTM IMPLEMENTATION
The LNBS21 helps the system designer to
implement the bi-directional (2.x) DiSEqC protocol
by al-lowing an easy PWK modulation/
demodulation of the 22KHz carrier. The PWK data
are exchanged between the LNBS21 and the
main µP using logic levels that are compatible with
both 3.3 and 5V mi-crocontrollers. This data
exchange is made through two dedicated pins,
DSQIN and DSQOUT, in or-der to maintain the
timing relationships between the PWK data and
the PWK modulation as accurate as possible.
These two pins should be directly connected to
two I/O pins of the µP, thus leaving to the resident
firmware the task of encoding and decoding the
PWK data in accordance to the DiSEqC pro-tocol.
Full compliance of the system to the specification
is thus not implied by the bare use of the LNBS21.
The system designer should also take in
consideration the bus hardware requirements,
that include the source impedance of the Master
Transmitter measured at 22KHz. To limit the
attenuation at car-rier frequency, this impedance
has to be 15ohm at 22KHz, dropping to zero ohm
at DC to allow the power flow towards the
peripherals. This can be simply accomplished by
the LR termination put on the OUT pin of the
LNBS, as shown in the Typical Application Circuit
on page 5.
Unidirectional (1.x) DiSEqC and non-DiSEqC
systems normally don't need this termination, and
the OUT pin can be directly connected to the LNB
supply port of the Tuner. There is also no need of
Tone Decoding, thus, it is recommended to
connect the DETIN and DSQOUT pins to ground
to avoid EMI.
ADDRESS PIN
Connecting this pin to GND the Chip I2C interface
address is 0001000, but, it is possible to choice
among 4 different addresses simply setting this
pin at 4 fixed voltage levels (see table on page
10).
ELECTRICAL CHARACTERISTICS FOR LNBS SERIES (TJ = 0 to 85°C, EN=1, LLC=0, TEN=0, ISEL=0,
PCL=0, DSQIN=0, VIN=12V, IOUT=50mA, unless otherwise specified. See software description section
for I2C access to the system register)
Symbol
Parameter
VIN
Supply Voltage
VLT1
LT1 Input Voltage
Test Conditions
IO = 750 mA TEN=VSEL=LLC=1
IIN
Supply Current
IO = 0mA TEN=VSEL=LLC=1
VO
Output Voltage
IO = 750 mA VSEL=1
VO
Output Voltage
IO = 750 mA VSEL=0
8/19
Min.
EN=1
EN=0
LLC=0
LLC=1
LLC=0
LLC=1
Typ.
8
17.3
12.5
20
2.5
18
19
13
14
Max.
Unit
15
V
20
V
40
5
18.7
mA
mA
V
V
V
V
13.5
LNBS21
Symbol
Parameter
∆VO
Line Regulation
∆VO
Load Regulation
IMAX
Output Current Limiting
Test Conditions
Min.
VIN1=8 to 15V
VSEL=0
VSEL=1
VSEL=0 or 1 IOUT = 50 to 750mA
ISEL=1
ISEL=0
ISEL=1
ISEL=0
Typ.
Max.
Unit
5
5
40
60
200
mV
mV
mV
900
1000
mA
mA
mA
mA
ms
ms
650
750
ISC
Output Short Circuit Current
tOFF
PCL=0
Output Shorted
PCL=0
Output Shorted
tOFF/10
fTONE
Dynamic Overload
protection OFF Time
Dynamic Overload
protection ON Time
Tone Frequency
300
400
900
TEN=1
20
22
24
KHz
ATONE
Tone Amplitude
TEN=1
0.55
0.72
0.9
Vpp
DTONE
Tone Duty Cycle
TEN=1
40
50
60
%
Tone Rise and Fall Time
TEN=1
5
8
15
µs
400
mVpp
tON
tr, tf
GEXTM External Modulation Gain
VEXTM
ZEXTM
VLT
fSW
fDETIN
VDETIN
ZDETIN
VOL
IOZ
VIL
VIH
IIH
IOBK
External Modulation Input
Voltage
External Modulation
Impedance
Loopthrough Switch Voltage
Drop (lt1 to LT2)
DC/DC Converter Switch
Frequency
Tone Detector Frequency
Capture Range
Tone Detector Input
Amplitude
Tone Detector Input
Impedance
Overload Flag Pin Logic
LOW
Overload Flag Pin OFF
State Leakage Current
DSQIN Input Pin Logic
LOW
DSQIN Input Pin Logic
HIGH
DSQIN Pins Input Current
AC Coupling
Output Backward Current
EN=0
Temperature Shutdown
Threshold
∆TSHDN Temperature Shutdown
Hysteresis
TSHDN
∆VOUT/∆VEXTM,
f = 10Hz to 40KHz
6
f = 10Hz to 50KHz
EN=0,
Ω
260
ILT=300mA,
VMI=12 or 19V
0.35
0.6
220
V
kHz
0.4Vpp sinewave
18
24
kHz
fIN=22kHz sinewave
0.2
1.5
Vpp
150
Tone present
IOL=2mA
Tone absent
VOH = 6V
0.3
kΩ
0.5
V
10
µA
0.8
V
2
VIH = 5V
V
µA
15
VOBK = 18V
-4
-10
mA
150
°C
15
°C
9/19
LNBS21
GATE AND SENSE ELECTRICAL CHARACTERISTICS (TJ = 0 to 85°C, VIN=12V)
Symbol
Parameter
Test Conditions
RDSON-L Gate LOW RDSON
IGATE=-100mA
RDSON-H Gate LOW RDSON
IGATE=100mA
Min.
Typ.
Max.
Ω
4.5
VSENSE Current Limit Sense Voltage
Unit
4.5
Ω
200
mV
I2C ELECTRICAL CHARACTERISTICS (TJ = 0 to 85°C, VIN=12V)
Symbol
Parameter
Test Conditions
VIL
LOW Level Input Voltage
VIH
HIGH Level Input Voltage
SDA, SCL
IIH
Input Current
SDA, SCL, VIN= 0.4 to 4.5V
VIL
DSQIN Input Pin Logic
SDA (open drain), IOL = 6mA
LOW
Maximum Clock Frequency SCL
fMAX
Min.
Typ.
SDA, SCL
Max.
Unit
0.8
V
10
µA
0.6
V
2
V
-10
500
KHz
ADDRESS PIN CHARACTERISTICS (TJ = 0 to 85°C, VIN=12V)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VADDR-1 "0001000" Addr Pin Voltage
0
0.7
V
VADDR-2 "0001001" Addr Pin Voltage
1.3
1.7
V
VADDR-3 "0001010" Addr Pin Voltage
2.3
2.7
V
VADDR-4 "0001011" Addr Pin Voltage
3.3
5
V
TEST CIRCUIT
1N4001
ILT
Vup
10nF
STPS3L40A
470nF
220µF
V
STN4NF03L
Gate
Vin
220µF
From I2C
Master
IOUT, IOBK
{
Load
A
OUT
Ω
0.05Ω
Vcc
Scope Probe
10nF
Rsc
A
VLT
LT2
Sense
L1=22µH
IIN
VMI, VOBK
A
LT1
LNBS21
VOUT
V
20µF
470nF
EXTM
SDA
SDA
SCL
SCL
VEXTM, VDETIN
10nF
DETIN
DSQIN
470nF
Pulse Gen.
BYP
ADDRESS
10/19
A
DSQOUT
VOL
V
IOZ / IOL
VOH / IOL
LNBS21
TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25°C)
Figure 4 : Output Voltage vs Temperature
Figure 7 : Line Regulation vs Temperature
Figure 5 : Output Voltage vs Temperature
Figure 8 : Load Regulation vs Temperature
Figure 6 : Line Regulation vs Temperature
Figure 9 : Load Regulation vs Temperature
11/19
LNBS21
Figure 10 : Supply Current vs Temperature
Figure 13 : Dynamic Overload Protection OFF
Time vs Temperature
Figure 11 : Supply Current vs Temperature
Figure 14 : Output Current Limiting vs
Temperature
Figure 12 : Dynamic Overload Protection ON
Time vs Temperature
Figure 15 : Output Current Limiting vs
Temperature
12/19
LNBS21
Figure 16 : Tone Frequency vs Temperature
Figure 19 : Tone Rise Time vs Temperature
Figure 17 : Tone Amplitude vs Temperature
Figure 20 : Tone Fall Time vs Temperature
Figure 18 : Tone Duty Cicle vs Temperature
Figure 21 : Loopthrought Switch Drop Voltage vs
Temperature
13/19
LNBS21
Figure 22 : Loopthrought Switch Drop Voltage vs
Temperature
Figure 25 : DSQOUT Pin Logic Low vs
Temperature
Figure 23 : Loopthrought Switch Drop Voltage vs
Loopthrought Current
Figure 26 : Undervoltage Lockout Threshold vs
Temperature
Figure 24 : Loopthrought Switch Drop Voltage vs
Loopthrought Current
Figure 27 : Output Backward Current vs
Temperature
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LNBS21
Figure 28 : DC/DC Converter Efficiency vs
Temperature
Figure 31 : DSQIN Tone Enable Transient
Response
VCC=12V, IO=50mA, EN=1, TEN=0
Figure 29 : Current Limit Sense vs Temperature
Figure 32 : DSQIN Tone Enable Transient
Response
VCC=12V, IO=50mA, EN=1, TEN=0
Figure 30 : 22kHz Tone
Figure 33 : DSQIN Tone Disable Transient
Response
VCC=12V, IO=50mA, EN=TEN=1
VCC=12V, IO=50mA, EN=1, TEN=0
15/19
LNBS21
Figure 34 : Output Voltage Transient Response
from 13V to 18V
Figure 35 : Output Voltage Transient Response
from 13V to 18V
VCC=12V, IO=50mA, VSEL=from 0 to 1, EN=1
VCC=12V, IO=50mA, VSEL=from 1 to 0, EN=1
TERMAL DESIGN NOTES
During normal operation, this device dissipates
some power. At maximum rated output current
(500mA), the voltage drop on the linear regulator
lead to a total dissipated power that is of about
1.7W. The heat generated requires a suitable
heatsink to keep the junction temperature below
the
overtemperature
protection
threshold.
Assuming a 40°C temperature inside the
Set-Top-Box case, the total Rthj-amb has to be
less than 50°C/W.
While this can be easily achieved using a
through-hole power package that can be attached
to a small heatsink or to the metallic frame of the
receiver, a surface mount power package must
rely on PCB solutions whose thermal efficiency is
often limited. The simplest solution is to use a
large, con-tinuous copper area of the GND layer to
dissipate the heat coming from the IC body.
The SO-20 package of this IC has 4 GND pins that
are not just intended for electrical GND
connec-tion, but also to provide a low thermal
resistance path between the silicon chip and the
PCB heatsink. Given an Rthj-c equal to 15°C/W,
a maximum of 35°C/W are left to the PCB
heatsink. This figure is achieved if a minimum of
25cm2 copper area is placed just below the IC
16/19
body. This area can be the inner GND layer of a
multi-layer PCB, or, in a dual layer PCB, an
unbroken GND area even on the opposite side
where the IC is placed. In both cases, the thermal
path between the IC GND pins and the dissipating
copper area must exhibit a low thermal resistance.
In figure 4 , it is shown a suggested layout for the
SO-20 package with a dual layer PCB, where the
IC Ground pins and the square dissipating area
are thermally connected through 32 vias holes,
filled by solder.
This arrangement, when
L=50mm, achieves an Rthc-a of about 25°C/W.
Different layouts are possible, too. Basic
principles, however, suggest to keep the IC and its
ground pins approximately in the middle of the
dissipating area; to provide as many vias as
possible; to de-sign a dissipating area having a
shape as square as possible and not interrupted
by other copper traces.
Due to presence of an exposed pad connected to
GND below the IC body, the PowerSO-20
package has a Rthj-c much lower than the SO-20,
only 2°C/W. As a result, much lower copper area
must be provided to dissipate the same power and
minimum of 12cm2 copper area is enough, see
figure 5.
LNBS21
Figure 36 : SO-20 SUGGESTED PCB HEATSINK LAYOUT
Figure 37 : PowerSO-20 SUGGESTED PCB HEATSINK LAYOUT
17/19
LNBS21
PowerSO-20 MECHANICAL DATA
mm.
DIM.
MIN.
inch
TYP
MAX.
A
MIN.
TYP.
MAX.
3.60
a1
0.10
0.1417
0.30
a2
0.0039
0.0118
0.0039
3.30
0.1299
a3
0
0.10
0
b
0.40
0.53
0.0157
0.0209
c
0.23
0.32
0.0090
0.0013
D (1)
15.80
16.00
0.6220
0.630
E
13.90
14.50
0.5472
0.5710
e
1.27
e3
11.43
E1 (1)
0.0500
0.4500
10.90
11.10
E2
0.4291
0.4370
0.0000
0.0039
2.90
G
0
0.1141
0.10
h
1.10
L
0.80
0.0433
1.10
N
0.0314
0.0433
10˚
S
0˚
10˚
8˚
T
0˚
8˚
10.0
0.3937
(1) “D and E1” do not include mold flash or protusions - Mold flash or protusions shall not exceed 0.15mm (0.006”)
N
R
N
a2
b
A
a1
e
DETAIL A
c
DETAIL B
E
e3
D
DETAIL A
lea
d
20
11
slug
a3
DETAIL B
E2
E1
0.35
Gage Plan
e
T
- C-
S
L
SEATING PLANE
G C
(COPLANARITY)
1
1
0
PSO20MEC
h x 45˚
0056635
18/19
LNBS21
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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