LNBK20D2 LNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE) ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ COMPLETE INTERFACE FOR TWO LNBs REMOTE SUPPLY AND CONTROL GUARANTEED 400mA OUTPUT CURRENT LNB SELECTION AND STAND-BY FUNCTION BUILT-IN TONE OSCILLATOR FACTORY TRIMMED AT 22KHz FAST OSCILLATOR START-UP FACILITATES DiSEqC ENCODING TWO SUPPLY INPUTS FOR LOWEST DISSIPATION BYPASS FUNCTION FOR SLAVE OPERATION LNB SHORT CIRCUIT PROTECTION AND DIAGNOSTIC AUXILIARY MODULATION INPUT EXTENDS FLEXIBILITY CABLE LENGTH COMPENSATION INTERNAL OVER TEMPERATURE PROTECTION BACKWARD CURRENT PROTECTION COST-EFFECTIVE VERSION OF LNBP SERIES DESCRIPTION Intended for analog and digital satellite receivers, the LNBK20D2 is a monolithic linear voltage regulator, assembled in SO-20, specifically designed to provide the powering voltages and the interfacing signals to the LNB downconverter situated in the antenna via the coaxial cable. It has the same functionality of the LNBP1X and LNBP20 series, at a reduced output current capability. Since most satellite receivers have two antenna ports, the output voltage of the regulator is available at one of two logic-selectable output pins (LNBA, LNBB). When the IC is powered and put in Stand-by (EN pin LOW), both regulator outputs are disabled to allow the antenna downconverters to be supplied/controlled by others satellite receivers sharing the same coaxial lines. In this occurrence the device will limit at 3 mA (max) the backward current that could flow from LNBA and LNBB output pins to GND. For slave operation in single dish, dual receiver systems, the bypass function is implemented by an electronic switch between the Master Input pin July 2003 SO-20 (MI) and the LNBA pin, thus leaving all LNB powering and control functions to the Master Receiver. This electronic switch is closed when the device is powered and EN pin is LOW. The regulator outputs can be logic controlled to be 13 or 18 V (typ.) by mean of the VSEL pin for remote controlling of LNBs. Additionally, it is possible to increment by 1V (typ.) the selected voltage value to compensate the excess voltage drop along the coaxial cable (LLC pin HIGH). In order to reduce the power dissipation of the device when the lowest output voltage is selected, the regulator has two Supply Input pins VCC1 and VCC2. They must be powered respectively at 16V (min) and 23V (min), and an internal switch automatically will select the suitable supply pin according to the selected output voltage. If adequate heatsink is provided and higher power losses are acceptable, both supply pins can be powered by the same 23V source without affecting any other circuit performance. The ENT (Tone Enable) pin activates the internal oscillator so that the DC output is modulated by a ±0.3 V, 22KHz (typ.) square wave. This internal oscillator is factory trimmed within a tolerance of ±2KHz, thus no further adjustments neither external components are required. A burst coding of the 22KHz tone can be accomplished thanks to the fast response of the ENT input and the prompt oscillator start-up. This helps designers who want to implement the DiSEqC protocols (*). In order to improve design flexibility and to allow implementation of newcoming LNB remote control standards, an analogic modulation input pin is 1/14 LNBK20D2 available (EXTM). An appropriate DC blocking capacitor must be used to couple the modulating signal source to the EXTM pin. When external modulation is not used, the relevant pin can be left open. Two pins are dedicated to the overcurrent protection/monitoring: CEXT and OLF. The overcurrent protection circuit works dynamically: as soon as an overload is detected in either LNB output, the output is shut-down for a time Toff determined by the capacitor connected between CEXT and GND. Simultaneously the OLF pin, that is an open collector diagnostic output flag, from HIGH IMPEDANCE state goes LOW. After the time has elapsed, the output is resumed for a time ton=1/15toff (typ.) and OLF goes in HIGH IMPEDANCE. If the overload is still present, the protection circuit will cycle again through toff and ton until the overload is removed. Typical ton+toff value is 1200ms when a 4.7µF external capacitor is used. This dynamic operation can greatly reduce the power dissipation in short circuit condition, still ensuring excellent power-on start up even with highly capacitive loads on LNB outputs. The device is packaged in Multiwatt15 for thru-holes mounting and in PowerSO-20 for surface mounting. When a limited functionality in a smaller package matches design needs, a range of cost-effective PowerSO-10 solutions is also offered. All versions have built-in thermal protection against overheating damage. (*): External components are needed to comply to level 2.x and above (bidirectiona) DiSEqC bus hardware requirements. DiSEqC is a trademark or EUTELSAT. PIN CONFIGURATION (top view) 2/14 LNBK20D2 TABLE A: PIN CONFIGURATIONS PIN N° SYMBOL NAME FUNCTION 1 LLC 2 OLF Line Length Compens. (1V typ) Over Load Flag 3 MI Master Input 4 5, 6, 15, 16 7, 13 LNBB GND Output Port Ground N.C. Not Connected 8 VCC1 Supply Input 1 15V to 27V supply. It is automatically selected when VOUT = 13 or 14V 9 VCC2 Supply Input 2 22V to 27V supply. It is automatically selected when VOUT = 18 or 19V 10 LNBA Output Port 11 VSEL 12 14 18 19 EN OSEL ENT CEXT Output Voltage Selection: 13 or 18V (typ) Port Enable Port Selection 22KHz Tone Enable External Capacitor 20 EXTM External Modulator Logic control input: see truth table Logic output (open collector). Normally in HIGH IMPEDANCE, goes LOW when current or thermal overload occurs In stand-by mode, the voltage on MI is routed to LNBA pin. Can be left open if bypass function is not needed See truth tables for voltage and port selection Circuit Ground. It is internally connected to the die frame See truth table voltage and port selection. In stand-by mode this port is powered by the MI pin via the internal Bypass Switch Logic control input: see truth table Logic control input: see truth table Logic control input: see truth table Logic control input: see truth table Timing Capacitor used by the Dynamic Overload protection. Typical application is 4.7µF for a 1200ms cycle External Modulation Input. Needs DC decoupling to the AC source. if not used, can be left open. NOTE: the limited pin availability of the PowerSO-10 package leads to drop some functions. ABSOLUTE MAXIMUM RATINGS Symbol Parameter² VI DC Input Voltage (VCC1, VCC2, MI) IO Output Current (LNBA, LNBB) VI Logic Input Voltage (ENT, EN OSEL, VSEL, LLC) Value Unit 28 V Internally Limited mA -0.5 to 7 V 900 mA 3 W ISW Bypass Switch Current PD Power Dissipation at Tcase < 85°C Tstg Storage Temperature Range -40 to +150 °C Top Operating Junction Temperature Range -40 to +125 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied. THERMAL DATA Symbol Rthj-case Parameter Thermal Resistance Junction-case Value Unit 15 °C/W 3/14 LNBK20D2 LOGIC CONTROLS TRUTH TABLE CONTROL I/O PIN NAME L OUT OLF IOUT > IOMAX or Tj > 150°C IOUT < IOMAX IN IN IN IN IN ENT EN OSEL VSEL LLC 22KHz tone OFF See Table Below See Table Below See Table Below See Table Below 22KHz tone ON See Table Below See Table Below See Table Below See Table Below EN OSEL VSEL LLCO VLNBA VLNBB L X X X VMI - 0.4V (typ.) Disabled H H H H H H H H L L L L H H H H L H L H L H L H L L H H L L H H 13V (typ.) 18V (typ.) 14V (typ.) 19V (typ.) Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled 13V (typ.) 18V (typ.) 14V (typ.) 19V (typ.) NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ) BLOCK DIAGRAM 4/14 H LNBK20D2 ELECTRICAL CHARACTERISTICS FOR LNBK SERIES (TJ = 0 to 85°C, CI = 0.22µF, C O =0.1µF, EN=H, ENT=L, LLC=L, VIN1=16V, VIN2=23V IOUT=50mA, unless otherwise specified.) Symbol VIN1 VIN2 VO1 Parameter VCC1 Supply Voltage VCC2 Supply Voltage Output Voltage Test Conditions Min. Typ. Max. Unit IO = 400 mA ENT=H, VSEL=L, LLC=L 15 27 V IO = 400 mA ENT=H, VSEL=L, LLC=H 16 27 V IO = 400 mA ENT=H, VSEL=L, LLC=L 22 27 V IO = 400 mA VSEL=L, LLC=H 23 27 V IO = 400 mA VSEL=L, LLC=L 17.3 18.7 V IO = 400 mA ENT=H, VSEL=L, LLC=H 19 12.5 13 V VO2 Output Voltage ∆VO Line Regulation VIN2=22 to 25V VOUT=18V 5 50 mV ∆VO Load Regulation VIN1=VIN2=22V IO = 0 to 3A VOUT=13 or 18V 65 150 mV SVR Supply Voltage Rejection VIN1 = VIN2 = 23 ± 0.5Vac fac = 120 Hz, IMAX Output Current Limiting 800 mA tOFF Output Shorted CEXT =4.7µF 1100 ms Output Shorted CEXT =4.7µF tOFF/15 ms fTONE Dynamic Overload protection OFF Time Dynamic Overload protection ON Time Tone Frequency ENT=H 20 22 24 KHz ATONE Tone Amplitude ENT=H 0.55 0.72 0.9 Vpp DTONE tON IO = 400 mA VSEL=L, LLC=L 18 IO = 400 mA ENT=H, VSEL=L, LLC=H 14 VIN1=15 to 18V 5 VOUT=13V 13.5 V 50 mV V 45 500 650 dB Tone Duty Cycle ENT=H 40 50 60 % Tone Rise and Fall Time tr, tf GEXTM External Modulation Gain ENT=H 5 10 15 µs VEXTM AC Coupling 400 mVpp IIH External Modulation Input Voltage External Modulation Impedance Bypass Switch Voltage Drop (MI to LNBA) Overload Flag Pin Logic LOW Overload Flag Pin OFF State Leakage Current Control Input Pin Logic LOW Control Input Pin Logic HIGH Control Pins Input Current VIH = 5V 20 ICC Supply Current Output Disabled (EN=L) ENT=H, IOUT=500mA 0.3 3.1 1 6 mA mA IOBK Output Backward Current EN=L VLNBA = VLNBB = 18V VIN1 = VIN2 = 22V or floating 0.2 3 mA ZEXTM VSW VOL IOZ VIL VIH TSHDN Temperature Shutdown Threshold ∆VOUT/∆VEXTM, f = 10Hz to 40KHz 5 f = 10Hz to 40KHz EN=L, ISW=300mA, Ω 400 VCC2-VMI=4V IOL=8mA 0.35 0.6 V 0.28 0.5 V 10 µA 0.8 V VOH = 6V 2.5 V 150 µA °C 5/14 LNBK20D2 TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25°C) Figure 1 : Output Voltage vs Output Current Figure 4 : Tone Frequency vs Temperature Figure 2 : Tone Duty Cycle vs Temperature Figure 5 : Tone Rise Time vs Temperature Figure 3 : Tone Fall Time vs Temperature Figure 6 : Tone Amplitude vs Temperature 6/14 LNBK20D2 Figure 7 : S.V.R. vs Frequency Figure 10 : LNBA External Modulation gain vs Frequency Figure 8 : External Modulation vs Temperature Figure 11 : Bypass switch Drop vs Output Current Figure 9 : Bypass Switch Drop vs Output Current Figure 12 : overload Flag pin Logic LOW vs Flag Current 7/14 LNBK20D2 Figure 13 : Supply Voltage vs Temperature Figure 14 : Supply Current vs Temperature Figure 15 : Dynamic Overload protection (ISC vs Time) 8/14 Figure 16 : Tone Enable Figure 17 : Tone Disable Figure 18 : 22KHz Tone LNBK20D2 Figure 19 : Enable Time Figure 21 : 18V to 13V Change Figure 20 : Disable Time Figure 22 : 18V to 13V Change TYPICAL APPLICATION SCHEMATICS TWO ANTENNA PORTS RECEIVER MCU+V 17V 24V 10uF C2 AUX DATA ANT CONNECTORS 11 EXTM 1 VCC1 2 VCC2 OLF 3 LNBA 15 LNBB 14 MI R1 13 47K 4 9 5 7 12 VSEL ENT EN OSEL LLC CEXT JA JB TUNER 10 4.7µF C1 + GND C4 2x 0.1µF LNBK20 Vcc C3 C5 C6 8 I/Os 2x 47nF I/Os MCU 9/14 LNBK20D2 SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT 17V MCU+V 10uF C2 AUX DATA 11 EXTM VCC1 VCC2 R1 13 47K LNBA LNBB MI OLF 4 9 5 7 12 CEXT VSEL ENT EN OSEL LLC 1 2 ANT 3 15 14 MASTER 10 TUNER 4.7µF C1 + GND C3 C4 C5 47nF 8 2x 0.1µF LNBK20 Vcc 24V I/Os I/Os MCU USING SERIAL BUS TO SAVE MPU I/Os 17V 24V MCU+V ANT CONNECTORS C2 R1 47K 11 AUX DATA EXTM 10uF 1 2 3 15 STR D CLK OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 4 5 6 7 14 13 12 11 QS QS 9 10 VCC1 VCC2 1 2 13 OLF LNBA 3 LNBB 15 14 MI 4 9 5 7 12 VSEL CEXT 10 ENT EN OSEL LLC GND 8 LNBK20 4.7µF C1 + JA JB TUNER C3 C4 C5 C6 2x 0.1µF 2x 47nF 4094 SERIAL BUS MCU+V I/Os Vcc MCU 10/14 LNBK20D2 THERMAL DESIGN NOTE During normal operation, this device dissipates some power. At maximum rated output current (400mA), the voltage drop on the linear regulator lead to a total dissipated power that is of about 2W. The heat generated requires a suitable heatsink to keep the junction temperature below the over temperature protection threshold. Assuming a 40°C temperature inside the Set-Top-Box case, the total Rthj-amb has to be less than 43°C/W. While this can be easily achieved using a through-hole power package that can be attached to a small heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous copper area of the GND layer to dissipate the heat coming from the IC body. The SO-20 package of this IC has 4 GND pins that are not just intended for electrical GND connection, but also to provide a low thermal resistance path between the silicon chip and the PCB heatsink. Given an Rthj-c equal to 15°C/W, a maximum of 28°C/W are left to the PCB heatsink. This figure is achieved if a minimum of 25cm2 copper area is placed just below the IC body. This area can be the inner GND layer of a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the IC is placed. In both cases, the thermal path between the IC GND pins and the dissipating copper area must exhibit a low thermal resistance. In figure 4, it is shown a suggested layout for the SO-20 package with a dual layer PCB, where the IC Ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by solder. This arrangement, when L=50mm, achieves an Rthc-a of about 28°C/W. Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground pins approximately in the middle of the dissipating area; to provide as many vias as possible; to design a dissipating area having a shape as square as possible and not interrupted by other copper traces. SO-20 SUGGESTED PCB HEATSINK LAYOUT 11/14 LNBK20D2 SO-20 MECHANICAL DATA mm. inch DIM. MIN. TYP A a1 MAX. MIN. TYP. 2.65 0.1 0.104 0.2 a2 MAX. 0.004 0.008 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 12.60 13.00 0.496 0.512 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 M S 0.75 0.029 8˚ (max.) PO13L 12/14 LNBK20D2 Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 30.4 0.519 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 13/14 LNBK20D2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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