LNBH23
LNBs supply and control IC with step-up and I²C interface
Features
■
Complete interface between LNB and I²C bus
■
Built-in DC-DC converter for single 12 V supply
operation and high efficiency (Typ. 93% @
0.75 A), with integrated NMOS
■
Selectable output current limit by external
resistor
■
Compliant with main satellite receiver systems
specifications
■
New accurate built-in 22 kHz tone generator
suits widely accepted standards (patent
pending) see Figure 1 and Figure 4
■
Fast oscillator start-up facilitates DiSEqCTM
encoding
■
Built-in 22 kHz tone detector supports bidirectional DiSEqCTM 2.0
■
Very low-drop post regulator and high
efficiency step-up PWM with integrated power
N-MOS allow low power losses
■
Two output pins suitable to by-pass the output
R-L filter and avoid any tone distortion (R-L
filter as per DiSEqCTM 2.0 specs, see typ.
application circuits)
■
Overload and over-temperature internal
protections with I²C diagnostic bits
■
Output voltage and output current level
diagnostic feedback by I²C bits
■
LNB Short circuit dynamic protection
■
+/- 4 kV ESD tolerant on output power pins
Table 1.
PowerSSO-24
(Exposed pad)
QFN32 (5x5mm)
(Exposed pad)
Description
Intended for analog and digital satellite
receivers/Sat-TV, sat-PC cards, the LNBH23 is a
monolithic voltage regulator and interface IC,
assembled in PowerSSO-24 ePAD and QFN32
(5x5 mm) ePAD, specifically designed to provide
the 13/18 V power supply and the 22 kHz tone
signalling to the LNB down-converter in the
antenna dish or to the multi-switch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I²C
standard interfacing.
Device summary
Order code
Package
Packaging
LNBH23PPR
PowerSSO-24 (Exposed pad)
Tape and reel
LNBH23QTR (1)
QFN32 (Exposed pad)
Tape and reel
1. Available on request.
March 2008
Rev 4
1/32
www.st.com
32
Contents
LNBH23
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
DiSEqCTM data encoding and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
DiSEqCTM 2.0 implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
DiSEqCTM 1.X implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Data encoding by external tone generator (EXTM) . . . . . . . . . . . . . . . . . . 6
2.5
I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6
Output voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.7
Diagnostic and protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.8
Output voltage diagnostic - VMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.9
22 kHz tone diagnostic - TMON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.10
Minimum output current diagnostic - IMON . . . . . . . . . . . . . . . . . . . . . . . . 7
2.11
Output current limit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.12
Over-current and short circuit protection and diagnostic . . . . . . . . . . . . . . 8
2.13
Thermal protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
I²C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7
2/32
6.1
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
Start and stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.3
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.5
Transmission without acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LNBH23 software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.1
Interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.2
System register (SR, 1 byte) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNBH23
Contents
7.3
Transmitted data (I²C bus write mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.4
Diagnostic received data (I²C read mode) . . . . . . . . . . . . . . . . . . . . . . . . 17
7.5
Power-ON I²C interface reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6
Address pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7
DiSEqCTM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
8
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
9
Typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
Block diagram
LNBH23
1
Block diagram
Figure 1.
Block diagram
ISEL
TTX
ADDR
SDA SCL
Vcc
LX
PWM
Controller
Rsense
P-GND
Byp Vcc-L
Preregulator
+U.V.lockout
+P.ON reset
EN
VSEL
VSEL
EN
TTX
ITEST
Vup
I²C interface
VOUT Control
TEN
Linear Post-reg
+Modulator
+Protections
+Diagnostics
VoRX
VoTX
TTX
I²C Diagnostics
22KHz
Oscill.
22KHz Tone
Amp. Diagn.
EXTM
22KHz Tone
Freq. Detector
DSQIN
VCTRL
LNBH23
A-GND
4/32
DETIN
DSQOUT
LNBH23
2
Application information
Application information
This IC has a built-in DC-DC step-up converter with integrated NMOS that, from a single
source from 8 V to 15 V, generates the voltages (VUP) that let the linear post-regulator to
work at a minimum dissipated power of 0.375 W Typ. @ 500 mA load (the linear postregulator drop voltage is internally kept at VUP-VORX=0.75 V typ.). An under voltage lockout
circuit will disable the whole circuit when the supplied VCC drops below a fixed threshold (6.7
V typically).
Note:
In this document the output voltage (VO) is intended as the voltage present at the linear
post-regulator output (VORX pin).
2.1
DiSEqCTM data encoding and decoding
The new internal 22 kHz tone generator (patent pending) is factory trimmed in accordance
to the standards, and can be selected by I²C interface TTX bit (or TTX pin) and activated by
a dedicated pin (DSQIN) that allows immediate DiSEqCTM data encoding, or through TEN
I²C bit in case the 22 kHz presence is requested in continuous mode. In stand-by condition
(EN bit LOW) The TTX function must be disabled setting TTX to LOW.
2.2
DiSEqCTM 2.0 implementation
The built-in 22 kHz tone detector completes the fully bi-directional DiSEqCTM 2.0 interfacing
(see Note: 1). It’s input pin (DETIN) must be AC coupled to the DiSEqCTM BUS, and
extracted PWK data are available on the DSQOUT pin. To comply to the bi-directional
DiSEqCTM 2.0 bus hardware requirements an output R-L filter is needed. The LNBH23 is
provided with two output pins, one for the dc voltage output (VoRX) and one for the 22 kHz
tone transmission (VoTX). The VoTX must be activated only during the tone transmission
while the VoRX provides the 13/18 V output voltage. This allows the 22 kHz Tone to pass
without any losses due to the R-L filter impedance (see Figure 4 typ. application circuit).
During the 22 kHz transmission, in DiSEqCTM 2.0 applications, activated by DSQIN pin or
by the TEN bit, the VoTX pin must be preventively set ON by the TTX function. This can be
controlled both through the TTX pin and by I²C bit. As soon as the tone transmission is
expired, the VoTX must be disabled by setting the TTX to LOW to set the device in the 22
kHz receiving mode. The 13/18 V power supply is always provided to the LNB from the VoRX
pin through the R-L filter.
2.3
DiSEqCTM 1.X implementation
When the LNBH23 is used in DiSEqCTM 1.x applications the R-L filter is always needed for
the proper operation of the new 22 kHz tone generator (patent pending. See application
circuit). Also in this case, the TTX function must be preventively enabled before to start the
22 kHz data transmission and disabled as soon as the data transmission has been expired.
The tone can be activated both with the DSQIN pin or the TEN I²C bit. The DSQIN internal
circuit activates the 22 kHz tone on the VoTX output with 0.5 cycles ±25 µs delay from the
TTL signal presence on the DSQIN pin, and it stops with 1 cycles ±25 µs delay after the TTL
signal is expired.
5/32
Application information
2.4
LNBH23
Data encoding by external tone generator (EXTM)
In order to improve design flexibility an external tone input pin is available (EXTM). The
EXTM is a logic input pin which activates the 22 kHz tone output, on the VoTX pin, by using
the LNBH23 integrated tone generator (similarly to the DSQIN pin function). As a matter of
fact, the output tone waveform characteristics will be always internally controlled by the
LNBH23 tone generator and the EXTM signal will be used just as a timing control of the
DiSEqC tone data encoding on the VoTX output. A TTL compatible 22 kHz signal is required
for the proper control of the EXTM pin function. Before to send the TTL signal on the EXTM
pin, the VoTX tone generator must be previously enabled through the TTX function (TTX pin
or TTX bit set HIGH). As soon as the EXTM internal circuit detects the 22 kHz TTL signal
code, it activates the 22 kHz tone on the VoTX output with 1.5 cycles ±25 µs delay from the
TTL signal presence on the EXTM pin, and it stops with 2 cycles ±25 µs delay after the TTL
signal is expired. Refer to the below Figure 2
Figure 2.
EXTM waveform
2.5
I²C interface
The main functions of the IC are controlled via I²C bus by writing 8 bits on the system
register (SR 8 bits in write mode). On the same register there are 8 bits that can be read
back (SR 8 bits in read mode) to provide 8 diagnostic functions: five bits will report the
diagnostic status of five internal monitoring functions (IMON, VMON, TMON, OTF, OLF)
while, three will report the last output voltage register status (EN, VSEL, LLC) received by
the IC (see below diagnostic functions section).
2.6
Output voltage selection
When the IC sections are in stand-by mode (EN bit LOW), the power blocks are disabled.
When the regulator blocks are active (EN bit HIGH), the output can be logic controlled to be
13 or 18 V by means of the VSEL bit (Voltage SELect) for remote controlling of non-DiSEqC
LNBs. Additionally, the LNBH23 is provided with the LLC I²C bit that increases the selected
voltage value by +1 V to compensate the excess of voltage drop along the coaxial cable.
The LNBH23 is also compliant to the USA LNB power supply standards. In order to allow
fast transition of the output voltage from 18 V to 13 V and vice versa, the LNBH23 is
provided with the VCTRL TTL pin which keeps the output to 13 V when it is set LOW and to
18 V when it is set HIGH or floating. VSEL and, if required, LLC bits must be set HIGH before
to use the VCTRL pin to switch the output voltage level. If VCTRL=1 or floating VoRX=18.5 V
(or 19.5 V if LLC=1). With VCTRL=0 VoRX=13.4 V (LLC= either 0 or 1). Be aware that the
VCTRL pin controls only the linear regulator VoRX stage while the step-up VUP voltage is
controlled only through the VSEL and LLC I²C bits, that is: Even if VCTRL=0 (keeping
6/32
LNBH23
Application information
VoRX=13.4 V) you will have VUP=19.25 V typ when VSEL=1 and 20.25 V with VSEL=LLC=1.
This means that VCTRL=0 must be used only for short time to avoid the higher power
dissipation. In stand-by condition (EN bit LOW) all the I²C bits and the TTX pin must be set
LOW (if the TTX pin is not used it can be left floating but the TTX bit must be set LOW during
the stand-by condition).
2.7
Diagnostic and protection functions
The LNBH23 has 5 diagnostic internal functions provided via I²C bus by reading 5 bits on
the system register (SR bits in read mode). All the diagnostic bits are, in normal operation
(no failure detected), set to LOW. Two diagnostic bits are dedicated to the over-temperature
and over-load protections status (OTF and OLF) while, the remaining 3 bits, are dedicated to
the output voltage level (VMON), 22 kHz tone (TMON) and to the minimum load current
diagnostic function (IMON).
2.8
Output voltage diagnostic - VMON
When VSEL=0 or 1 and LLC=0, the output voltage pin (VoRX) is internally monitored and, as
long as the output voltage level is below the guaranteed limits the VMON I²C bit is set to "1".
The output voltage diagnostic is valid only with LLC=0. Any VMON information with LLC=1
must be disregarded by the MCU.
2.9
22 kHz tone diagnostic - TMON
The 22 kHz tone can be internally detected and monitored if DETIN pin is connected to the
LNB output bus (see typical application circuits Figure 4) through a decoupling capacitor.
The tone diagnostic function is provided with the TMON I²C bit. If the 22 kHz Tone amplitude
and/or the tone frequency is out of the guaranteed limits (see TMON limits in the electrical
characteristics Table 13), the TMON I²C bit is set to "1".
2.10
Minimum output current diagnostic - IMON
In order to detect the output load absence (no LNB connected on the bus or cable not
connected to the IRD) the LNBH23 is provided with a minimum output current flag by the
IMON I²C bit in read mode, which is set to "1" if the output current is lower than 12 mA
typically with ITEST=1 and 6 mA with ITEST=0. The minimum current diagnostic function
(IMON) is always active. In order to make it work even in a multi-IRD configuration (multiswitch), where the supply current could be sunk only from the higher supply voltage
connected to the multi-switch box, the LNBH23 is provided with the AUX I²C bit which can
be set HIGH, in write mode by the MCU, before to read the IMON I²C bit status, to force the
LNBH23 output voltage as the highest voltage on the bus (22 V typ.) during the minimum
current diagnostic phase. When the AUX bit is set to HIGH, the VoRX is set to 22 V (typ.) and
VUP is set to 22.75 V (VUP = VoRX+0.75 V typ.) independently of the VSEL/LLC bits status. If
the AUX function is used to force the VoRX to 22 V, it is recommended to set the AUX bit to
LOW as soon as the minimum current test phase is expired, so that the VoRX voltage will be
controlled again as per the VSEL/LLC bits status. In order to avoid false triggering, the
IMON function must be used only with the 22 kHz tone transmission deactivated
(TEN=TTX=0 and DSQIN=LOW), otherwise the IMON bit could be erroneously set to 0 even
if the output current is below the minimum current thresholds (6 mA or 12 mA). Any TMON
information with 22 kHz tone enabled must be disregarded by the MCU.
7/32
Application information
2.11
LNBH23
Output current limit selection
The linear regulator current limit threshold can be set by an external resistor connected to
ISEL pin. The resistor value defines the output current limit by the equation:
IMAX[A] = 10000/RSEL
where RSEL is the resistor connected between ISEL and GND. The highest selectable current
limit threshold is 1.0 A typ with RSEL=10 kΩ. The above equation defines the typical
threshold value.
2.12
Over-current and short circuit protection and diagnostic
In order to reduce the total power dissipation during an overload or a short circuit condition,
the device is provided with a dynamic short circuit protection. It is possible to set the short
circuit current protection either statically (simple current clamp) or dynamically by the PCL
bit of the I²C SR. When the PCL (Pulsed Current Limiting) bit is set lo LOW, the over current
protection circuit works dynamically: as soon as an overload is detected, the output current
is provided for 90 ms (typ.), after that the output is set in shut-down for a time TOFF of
typically 900 ms. Simultaneously the diagnostic OLF I²C bit of the system register is set to
"1". After this time has elapsed, the output is resumed for a time TON=1/10 TOFF = 90 ms
(typ.). At the end of TON, if the overload is still detected, the protection circuit will cycle again
through TOFF and TON. At the end of a full TON in which no overload is detected, normal
operation is resumed and the OLF diagnostic bit is reset to LOW. Typical TON +TOFF time is
990 ms and an internal timer determines it. This dynamic operation can greatly reduce the
power dissipation in short circuit condition, still ensuring excellent power-on start-up in most
conditions. However, there could be some cases in which a highly capacitive load on the
output may cause a difficult start-up when the dynamic protection is chosen. This can be
solved by initiating any power start-up in static mode (PCL=1) and, then, switching to the
dynamic mode (PCL=0) after a chosen amount of time depending on the output
capacitance. Also in static mode, the diagnostic OLF bit goes to "1" when the current clamp
limit is reached and returns LOW when the overload condition is cleared.
2.13
Thermal protection and diagnostic
The LNBH23 is also protected against overheating: when the junction temperature exceeds
150 °C (typ.), the step-up converter and the liner regulator are shut-off, and the diagnostic
OTF SR bit is set to "1". Normal operation is resumed and the OTF bit is reset to LOW when
the junction is cooled down to 135 °C (typ.).
Note:
8/32
1
External components are needed to comply to bidirectional DiSEqCTM bus hardware
requirements. Full compliance of the whole application with DiSEqCTM specifications is not
implied by the use of this IC. NOTICE: DiSEqCTM is a trademark of EUTELSAT. I²C is
trademark of Philips Semiconductors.
LNBH23
Pin configuration
3
Pin configuration
Figure 3.
Pin connections (top view for PowerSSO-24, bottom view for QFN32)
DETIN
1
24
NC
VCTRL
2
23
ISEL
3
22
VUP
NC
4
21
NC
NC
5
20
VoTX
LX
6
19
VoRX
P-GND
7
18
A-GND
SDA
8
17
VCC
VCC-L
NC
9
16
ADDR
10
15
BYP
DSQOUT
11
14
TTX
DSQIN
12
13
EXTM
SCL
QFN32 (5x5 mm)
PowerSSO-24
Table 2.
Pin description
Pin n° for Pin n° for
QFN32 PSSO-24
Symbol
Name
Function
19
17
VCC
Supply input
8 to 15 V IC DC-DC power supply.
18
16
VCC–L
Supply input
8 to 15 V analog power supply.
4
6
LX
N-MOS drain
Integrated N-Channel power MOSFET drain.
27
22
VUP
Step-Up voltage
Input of the linear post-regulator. The voltage on this pin is
monitored by the internal step-up controller to keep a
minimum dropout across the linear pass transistor.
21
19
VoRX
LDO output port
Output of the integrated low drop linear post-regulator. See
truth tables for voltage selections and description.
22
20
VoTX
6
8
SDA
Serial data
Bi-directional data from/to I²C bus.
9
9
SCL
Serial clock
Clock from I²C bus.
Output port for 22
TX Output to the LNB. See truth tables for selection.
kHz tone TX
12
12
DSQIN
DiSEqC input
This pin will accept the DiSEqC code from the main
microcontroller. The LNBH23 will use this code to modulate
the internally generated 22 kHz carrier. Set to ground if not
used.
14
14
TTX
TTX enable
This pin can be used, as well as the TTX I²C bit of the system
register, to control the TTX function enable before to start the
22 kHz tone transmission. Set floating or to GND if not used.
29
1
DETIN
Tone decoder
input
22 kHz tone decoder Input, must be AC coupled to the
DiSEqC 2.0 bus.
9/32
Pin configuration
Table 2.
LNBH23
Pin description (continued)
Pin n° for Pin n° for
QFN32 PSSO-24
Symbol
Name
Function
Open drain output of the tone decoder to the main
microcontroller for DiSEqC 2.0 data decoding. It is LOW
when tone is detected on DETIN pin.
11
11
DSQOUT
DiSEqC output
13
13
EXTM
External
modulation
Needed for internal pre-regulator filtering. The BYP pin is
intended only to connect an external ceramic capacitor. Any
connection of this pin to external current or voltage sources
may cause permanent damage to the device.
Two I²C bus addresses available by setting the Address pin
level voltage. See address pin characteristics Table 10
15
15
BYP
By-pass
capacitor
10
10
ADDR
Address setting
28
23
ISEL
External modulation logic input pin which activates the 22
kHz tone output on the VoTX pin. Set to ground if not used.
The resistor “RSEL” connected between ISEL and GND
Current selection defines the linear regulator current limit threshold by the
equation: Imax(typ.)=10000/ RSEL.
30
2
VCTRL
Output voltage
control
13V-18V linear regulator VoRX switch control. To be used
only with VSEL=1. If VCTRL=1 or floating VoRX=18.5V (or
19.5V if LLC=1). If VCTRL=0 than VoRX=13.4V (LLC=either 0
or 1). Leave floating if not used. Do not connect to ground if
not used.
5
7
P-GND
Power ground
DC-DC converter power ground.
Epad
Epad
Epad
Exposed pad
To be connected with power grounds and to the ground layer
through vias to dissipate the heat.
20
18
A-GND
Analog ground
Analog circuits ground.
1, 2, 3, 7,
8, 16, 17,
23, 24,
25, 26,
31, 32
3, 4, 5,
21, 24
N.C.
Not connected
Not internally connected pins.
10/32
LNBH23
Maximum ratings
4
Maximum ratings
Table 3.
Absolute maximum ratings
Symbol
Parameter
VCC-L, VCC DC power supply input voltage pins
DC input voltage
VUP
IO
Output current
Value
Unit
-0.3 to 16
V
-0.3 to 24
V
Internally Limited
mA
VoRX
DC output pin voltage
-0.3 to 25
V
VoTX
Tone output pin voltage
-0.3 to 25
V
VI
Logic input voltage (TTX, SDA, SCL, DSQIN, EXTM, VCTRL,
ADDR)
-0.3 to 7
V
LX
LX input voltage
-0.3 to 24
V
2
VPP
VDETIN
Detector input signal amplitude
VOH
Logic high output voltage (DSQOUT)
-0.3 to 7
V
VBYP
Internal reference pin voltage (Note 2)
-0.3 to 4.6
V
ISEL
Current selection pin voltage
-0.3 to 4.6
V
TSTG
Storage temperature range
-50 to 150
°C
Operating junction temperature range
-25 to 125
°C
TJ
ESD
ESD rating with human body model (HBM) for all pins unless
6,19,20,
2
ESD rating with Human Body Model (HBM) for pins 19, 20
4
ESD rating with Human Body Model (HBM) for pin 6
Note:
kV
0.6
1
Absolute maximum ratings are those values beyond which damage to the device may occur.
These are stress ratings only and functional operation of the device at these conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. All voltage values are with respect to network ground terminal.
2
The BYP pin is intended only to connect an external ceramic capacitor. Any connection of
this pin to external current or voltage sources may cause permanent damage to the device.
Table 4.
Symbol
Thermal data
Parameter
QFN32
PowerSSO-24
Unit
RthJC
Thermal resistance junction-case
2
2
°C/W
RthJA
Thermal resistance junction-ambient (PowerSSO24) with device soldered on 2s2p PC Board
35
30
°C/W
11/32
Application circuit
LNBH23
5
Application circuit
Figure 4.
Typical application circuit
D3 1N4001
Ferrite Bead Filter
L2 suggested part number:
MURATA BL01RN1-A62
Panasonic EXCELS A35
L2
C9
10µF
Vup
C4
470nF
Ceramic
C5
100µF
VoTX
C3
100µF
C6
470nF
C13
10nF
D4
BAT43
Ceramic
LNBH23
D1
STPS130A
L3
270µH
LX
L1=22µH
R1
100Ohm
C2
100nF
Ceramic
C7
100nF
I C Bus
Tone Enable
EXTM
{
ADDR
SDA
TTX
C12
10nF
C11
220nF
Ceramic
DSQOUT
SCL
VCTRL
DSQIN
TTX Enable
R3
10kOhm
Byp
Ceramic
Ceramic
R4
15 Ohm
DETIN
C8
220nF
2
Table 5.
Ceramic
Vcc-L
C1
100µF
D2
BAT43
C10
220nF
Vcc
Vin
12V
to LNB
VoRX
13/18
ISEL
P-GND
A-GND
R2 (RSEL)
11kOhm
Bill of material
Component
Notes
R1, R4
1/4W Resistors. Refer to the typical application circuit for the relative values
R2 (RSEL), R3
1/4W Resistors. Refer to the typical application circuit for the relative values
C1
25V Electrolytic Capacitor, 100µF or higher is suitable.
C9
10µF, >35V Electrolytic Capacitor
C3, C5
100µF, >25V Electrolytic Capacitor, ESR in the 150mΩ to 350mΩ range
C2, C4, C6, C7, C8, C10,
>25V Ceramic Capacitors. Refer to the Typ. Appl. Circuit for the relative values
C11, C12, C13
STPS130A or any similar schottky diode with VRRM>25V and IF(AV) higher than:
D1
D2, D4
D3
12/32
IF ( AV) > IOUT_MAX x
VUP_MAX
VIN MIN
BAT43, 1N5818, or any schottky diode with IF(AV)>0.2A, VRRM>25V, VF<0.5V
1N4001 or equivalent
LNBH23
Table 5.
Application circuit
Bill of material (continued)
Component
Notes
22 µH Inductor with Isat>Ipeak where Ipeak is the boost converter peak current:
L1
L2
FERRITE BEAD, Panasonic-EXCELS A35 or Murata-BL01RN1-A62 or Taiyo-YudenBKP1608HS600 or equivalent with similar or higher impedance and current rating
higher than 2A
L3
220µH-270µH Inductor with current rating higher than rated output current
13/32
I²C bus interface
6
LNBH23
I²C bus interface
Data transmission from main MCU to the LNBH23 and vice versa takes place through the 2
wires I²C bus Interface, consisting of the 2 lines SDA and SCL (pull-up resistors to positive
supply voltage must be externally connected).
6.1
Data validity
As shown in Figure 5, the data on the SDA line must be stable during the high semi-period
of the clock. The HIGH and LOW state of the data line can only change when the clock
signal on the SCL line is LOW.
6.2
Start and stop condition
As shown in Figure 6 a start condition is a HIGH to LOW transition of the SDA line while
SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is
HIGH. A STOP condition must be sent before each START condition.
6.3
Byte format
Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.
6.4
Acknowledge
The master (MCU) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 7). The peripheral (LNBH23) that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
this clock pulse. The peripheral which has been addressed has to generate acknowledge
after the reception of each byte, otherwise the SDA line remains at the HIGH level during the
ninth clock pulse time. In this case the master transmitter can generate the STOP
information in order to abort the transfer. The LNBH23 won't generate acknowledge if the
VCC supply is below the Under-voltage Lockout threshold (6.7 V typ.).
6.5
Transmission without acknowledge
Avoiding to detect the acknowledges of the LNBH23, the MCU can use a simpler
transmission: simply it waits one clock cycle without checking the slave acknowledging, and
sends the new data. This approach of course is less protected from misworking and
decreases the noise immunity.
14/32
LNBH23
I²C bus interface
Figure 5.
Data validity on the I²C bus
Figure 6.
Timing diagram of I²C bus
Figure 7.
Acknowledge on the I²C bus
15/32
LNBH23 software description
LNBH23
7
LNBH23 software description
7.1
Interface protocol
The interface protocol comprises:
●
A start condition (S)
●
A chip address byte (the LSB bit determines read(=1)/write(=0) transmission)
●
A sequence of data (1 byte + acknowledge)
●
A stop condition (P)
Chip address
Data
MSB
S
0
LSB
0
0
1
0
1
X
MSB
LSB
R/W ACK
ACK
ACK = Acknowledge
S = Start
P = Stop
R/W = 1/0, Read/Write bit
X = 0/1, two selectable addresses available through ADDR pin (see Address pin
characteristics Table 10)
7.2
System register (SR, 1 byte)
Mode
MSB
LSB
Write
PCL
TTX
TEN
LLC
VSEL
EN
ITEST
AUX
Read
IMON
VMON
TMON
LLC
VSEL
EN
OTF
OLF
Write = control bits functions in write mode
Read= diagnostic bits in read mode.
All bits reset to 0 at power On
16/32
P
LNBH23
LNBH23 software description
7.3
Transmitted data (I²C bus write mode)
Table 6.
When the R/W bit in the chip address is set to 0, the main MCU can write on the system
register (SR) of the LNBH23 via I²C bus. All and 8 bits are available and can be written by
the MCU to control the device functions as per the below truth table
Truth table
PCL
TTX
TEN
LLC
VSEL
EN
ITEST
0
0
0
1
0
VoRX= 13.4V, VUP=14.15V, (VUP-VoRX=0.75V)
0
0
1
1
0
VoRX= 18.5V, VUP=19.25V, (VUP-VoRX=0.75V)
0
1
0
1
0
VoRX= 14.4V, VUP=15.15V, (VUP-VoRX=0.75V)
0
1
1
1
0
VoRX= 19.5V, VUP=20.25V, (VUP-VoRX=0.75V)
X
X
1
1
VoRX= 22V, VUP=22.75V, (VUP-VoRX=0.75V)
X
AUX
Function
0
1
22 kHz controlled by DSQIN pin (only if TTX=1)
1
1
22 kHz tone output is always activated
0
1
VoRX output is ON, VoTX Tone generator output is
OFF
1
1
VoRX output is ON, VoTX Tone generator output is ON
0
1
Pulsed (Dynamic) current limiting is selected
1
1
Static current limiting is selected
1
X
X
X
X
X
1
0
Minimum output current diagnostic threshold = 6mA
typ.
X
X
1
1
Minimum output current diagnostic threshold = 12mA
typ.
X
X
0
X
X
Power block disabled
X = don't care
All values are typical unless otherwise specified
Valid with TTX pin floating or to GND
7.4
Diagnostic received data (I²C read mode)
LNBH23 can provide to the MCU Master a copy of the diagnostic system register
information via I²C bus in read mode. The read mode is master activated by sending the
chip address with R/W bit set to 1. At the following master generated clocks bits, LNBH23
issues a byte on the SDA data bus line (MSB transmitted first). At the ninth clock bit the
master can:
●
Acknowledge the reception, starting in this way the transmission of another byte from
the LNBH23
●
No acknowledge, stopping the read mode communication
Three bits of the register are read back as a copy of the corresponding write output voltage
register status (LLC, VSEL, EN), while, the other five bits convey diagnostic information
about the over-temperature (OTF), output voltage level (VMON), output over-load (OLF),
Minimum output current presence (IMON) and 22 kHz tone (TMON). In normal operation the
diagnostic bits are set to zero, while, if a failure is occurring, the corresponding bit is set to
one. At start-up all the bits are reset to zero.
17/32
LNBH23 software description
Table 7.
IMON
LNBH23
Register
VMON
TMON
LLC
VSEL
EN
These bits are read
exactly the same as
they were left after
last write operation
0/1 (2)
0/1 (3)
OTF
OLF
Function
0
TJ < 135°C, normal operation (1)
1
TJ > 150°C, power blocks disabled (1)
0
IO < IOMAX, normal operation
1
IO > IOMAX, Overload Protection triggered
0/1
These bits are set to 1 if the relative parameter
is out of the specification limits.
1. Values are typical unless otherwise specified
2. IMON information must be disregarded if 22 kHz TONE output is enabled
3. VMON information must be disregarded if LLC=1 (valid only if LLC=0)
7.5
Power-ON I²C interface reset
I²C interface built in LNBH23 is automatically reset at power-on. As long as the VCC stays
below the undervoltage lockout (UVL) threshold (6.7 V), the interface does not respond to
any I²C command and the system register (SR) is initialized to all zeroes, thus keeping the
power blocks disabled. Once the VCC rises above 7.3 V typ. The I²C interface becomes
operative and the SR can be configured by the main MCU. This is due to 500 mV of
hysteresis provided in the UVL threshold to avoid false retriggering of the power-on reset
circuit.
7.6
Address pin
It is possible to select two I²C interface addresses by means of ADDR pin. This pin is TTL
compatible and can be set as per hereafter address pin characteristics Table 10.
7.7
DiSEqCTM implementation
LNBH23 helps system designer to implement bi-directional DiSEqC 2.0 protocol by allowing
an easy PWK modulation/demodulation of the 22 kHz carrier. Between the LNBH23 and the
main MCU the PWK data is exchanged using logic levels that are compatible with both 3.3 V
and 5 V MCU. This data exchange is made through two dedicated pins, DSQIN and
DSQOUT, in order to maintain the timing relationships between the PWK data and the PWK
modulation as accurate as possible. These two pins should be directly connected to two I/O
pins of the MCU, thus leaving to the firmware the task of encoding and decoding the PWK
data in accordance to the DiSEqC protocol.
Full compliance of the system to the specification is thus not implied by the bare use of the
LNBH23. The system designer should also take in consideration the bus hardware
requirements; that can be simply accomplished by the R-L termination connected between
VoRX and VoTX pins of LNBH23, as shown in the typical application circuit in Figure 4. To
avoid any losses due to the R-L impedance during the tone transmission, LNBH23 has
dedicated Tone output (VoTX) that is connected after the filter and must be enabled by
setting the TTX function to HIGH only during the tone transmission (see DiSEqC 2.0
operation implementation in section 2.2 and 2.3). Also unidirectional DiSEqC 1.x and nonDiSEqC systems need this termination connected through a bypass capacitor and after a RL filter with 15 Ω in parallel with a 220 µH-270 µH inductor but, there is no need of Tone
Decoding, thus DETIN and DSQOUT pins can be left connected to GND.
18/32
LNBH23
Electrical characteristics
8
Electrical characteristics
Table 8.
Electrical characteristics (Refer to the typical application circuit, TJ = 0 to 85 °C, EN=1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ, DSQIN = LOW, VI = 12 V, IO =
50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO = VoRX pin
voltage. See software description section for I²C access to the system register)
Symbol
VI
II
VO
Parameter
Supply voltage
Supply current
Output voltage
Test conditions
Min.
Typ.
Max.
Unit
8
12
15
V
IO=0
7
15
EN=TEN=TTX=1, IO=0
20
40
EN=0
2
AUX=1; IO=50mA
22
IO=750mA, VSEL=LLC=1
VSEL=1 IO=750mA
VSEL=0 IO=750mA
LLC=0
17.8
18.5
19.2
LLC=1
18.8
19.5
20.2
LLC=0
12.8
13.4
14
LLC=1
13.8
14.4
15
VSEL=0
5
40
VSEL=1
5
60
VO
Line regulation
VO
Load regulation
VSEL=0 or 1, IO from 50 to750mA
13/18V Rise and Fall
transition time by VCTRL pin
VSEL=LLC=1, VCTRL from LOW to
HIGH and vice versa, IO from 6 to
450mA, CO from 10 to 330nF
13/18
TR - T F
IMAX
Output current limiting
VI=8 to 15V
mA
V
mV
200
575
mV
µs
RSEL=11kΩ
750
1000
RSEL= 22kΩ
300
600
mA
Output short circuit current
VSEL=0/1, AUX=0/1
1000
TOFF
Dynamic overload protection
OFF time
PCL=0, Output shorted
900
TON
Dynamic overload protection
ON time
PCL=0, Output shorted
FTONE
Tone frequency
DSQIN=HIGH or TEN=1, TTX=1
20
22
24
kHz
ATONE
Tone amplitude
DSQIN=HIGH or TEN=1, TTX=1
IO from 0 to750mA
CO from 0 to 750nF
0.4
0.650
0.9
VPP
DTONE
Tone duty cycle
DSQIN=HIGH or TEN=1, TTX=1
43
50
57
%
Tone rise or fall time
DSQIN=HIGH or TEN=1, TTX=1
5
8
15
µs
20
22
24
kHz
ISC
mA
ms
tr, tf
EXTM frequency
VEXTM-H =3.3V, VEXTM-L =0V,
EffDC-DC
DC-DC converter efficiency
IO=750mA
FSW
DC-DC converter switching
frequency
FEXTM
TOFF/10
(1)
93
%
220
kHz
19/32
Electrical characteristics
Table 8.
LNBH23
Electrical characteristics (continued) (Refer to the typical application circuit, TJ = 0 to 85
°C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ, DSQIN = LOW, VI =
12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO =
VoRX pin voltage. See software description section for I²C access to the system register)
Symbol
Parameter
Test conditions
FDETIN
Tone detector frequency
capture range
VDETIN
Tone detector input amplitude Sine wave signal, 22 kHz
ZDETIN
Tone detector input
impedance
VOL
DSQOUT pin logic LOW
IOZ
0.4VPP sine wave(2)
Min.
Typ.
Max.
Unit
19
22
25
kHz
1.5
VPP
0.3
150
0.5
V
DSQOUT pin leakage current DETIN Tone absent, VOH=6V
10
µA
VIL
DSQIN,TTX,13/18, EXTM pin
logic Low
0.8
V
VIH
DSQIN,TTX,13/18, EXTM pin
logic High
IIH
DSQIN,TTX,13/18, EXTM pin
VIH=5V
input current
15
Output backward current
-6
IOBK
TSHDN
ΔTSHDN
DETIN Tone present, IOL=2mA
0.3
kΩ
2
EN=0, VOBK=21V
V
µA
-15
mA
Thermal shut-down threshold
150
°C
Thermal shut-down
hysteresis
15
°C
1. External signal frequency range in which the EXTM function is guaranteed.
2. Frequency range in which the DETIN function is guaranteed. The VPP level is intended on the LNB bus (before the C12
capacitor. See Figure 4)
Table 9.
I²C electrical characteristics (TJ from 0 to 85 °C, VI = 12 V)
Symbol
Parameter
Test conditions
VIL
LOW Level input voltage
SDA, SCL
VIH
HIGH Level input voltage
SDA, SCL
Input current
SDA, SCL, VI = 0.4 to 4.5V
VOL
Low level output voltage
SDA (open drain), IOL = 6mA
fMAX
Maximum clock frequency
SCL
II
Table 10.
Symbol
Min.
Typ.
Max.
Unit
0.8
V
2
V
-10
10
µA
0.6
V
400
kHz
Address pin characteristics (TJ from 0 to 85 °C, VI = 12 V)
Parameter
Test condition
Min.
Typ.
Max.
Unit
VADDR-1
"0001010(R/W)" Address pin R/W bit determines the transmission
voltage range
mode: read (R/W=1) write (R/W=0)
0
0.8
V
VADDR-2
"0001011(RW)" Address pin
voltage range
2
5
V
20/32
R/W bit determines the transmission
mode: read (R/W=1) write (R/W=0)
LNBH23
Table 11.
Electrical characteristics
Output voltage diagnostic (VMON bit) characteristics (Refer to the typical application
circuit, TJ from 0 to 85 °C, EN=1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL=11 kΩ,
DSQIN=LOW, VI = 12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to
TJ = 25 °C. VO=VoRX pin voltage. See software description section for I²C access to the
system register)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
VTH-L
Diagnostic low threshold at
VO=13.4V
EN=1, VSEL=0
LLC=0
85
90
95
%
VTH-L
Diagnostic low threshold at
VO=18.5V
EN=VSEL=1
LLC=0
84
90
96
%
Note:
If the output voltage is lower than the min. value the VMON I²C bit is set to 1.
When VSEL=0: If VMON=0 then VoRX>85% of VoRX typical; If VMON=1 then VoRX<95% of
VoRX typical.
When VSEL=1: If VMON=0 then VoRX>84% of VoRX typical; If VMON=1 then VoRX<96% of
VoRX typical.
Table 12.
Symbol
ITH
Minimum output current diagnostic (IMON bit) characteristics (TJ from 0 to 85 °C,
EN = 1, VSEL=LLC=TEN=PCL=TTX=0, DSQIN=LOW, VI = 12 V, unless otherwise stated.
See software description section for I²C access to the system register)
Parameter
Minimum current diagnostic
threshold
Test condition
Min.
Typ.
Max.
ITEST=1, AUX=0/1
5
12
20
ITEST=0, AUX=0/1
2.5
6
10
Unit
mA
Note:
If the output current is lower than the min. threshold limit the IMON I²C bit is set to 1. if the
output current is higher than the max threshold limit the IMON I²C bit is set to 0.
Table 13.
22 kHz tone diagnostic (TMON bit) characteristics (Refer to the typical application circuit,
TJ from 0 to 85 °C, EN = 1, VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 KΩ,
DSQIN=LOW, VI = 12 V, IO = 50 mA, unless otherwise stated. Typical values are referred to
TJ=25°C. VoRX=VoRX pin voltage. See software description section for I²C access to the
system register)
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
ATH-L
Amplitude diagnostic low
threshold
DETIN pin AC coupled
200
300
400
mV
ATH-H
Amplitude diagnostic high
threshold
DETIN pin AC coupled
900
1100
1200
mV
FTH-L
Frequency diagnostic low
thresholds
DETIN pin AC coupled
13
16.5
20
kHz
FTH-H
Frequency diagnostic high
thresholds
DETIN pin AC coupled
24
29.5
38
kHz
Note:
If the 22 kHz tone parameters are lower or higher than the above limits the TMON I²C bit is
set to 1.
21/32
Typical performance characteristics
LNBH23
9
Typical performance characteristics
Figure 8.
(Refer to the typical application circuit, TJ from 0 to 85 °C, EN = 1,
VSEL=LLC=TEN=PCL=ITEST=TTX=AUX=0, RSEL = 11 kΩ, DSQIN=LOW, VI = 12 V,
IO = 50 mA, unless otherwise stated. Typical values are referred to TJ = 25 °C. VO=VoRX pin
voltage. See software description section for I²C access to the system register).
Output voltage vs temperature
Figure 9.
Output voltage vs temperature
15
14
VCC=12V, IO=50mA, VO=13V range
13.6
14.6
13.4
14.4
13.2
14.2
13
14
12.8
13.8
EN=1, VSEL=LLC=0
12.6
-10
0
10
20
30
VCC=12V, IO=50mA, VO=14V range
14.8
VO [V]
VO [V]
13.8
40
50
60
70
80
90
EN=LLC=1, VSEL=0
13.6
-10
0
10
20
30
T [°C]
Figure 10. Output voltage vs temperature
VCC=12V, IO=50mA, VO=18V range
18.6
VO [V]
VO [V]
18.8
18.4
18.2
18
EN=VSEL=1, LLC=0
17.8
-10
0
10
20
30
40
50
60
70
80
20.3
20.1
19.9
19.7
19.5
19.3
19.1
18.9
18.7
18.5
0
Figure 13.
16
-20
14
-40
12
-60
10
IIN [mA]
Load [mV]
80
90
10
20
30
40
50
60
70
80
90
T [°C]
0
-80
-100
Supply current vs temperature
VCC=12V, IO=No Load
8
6
4
VCC=12V
-140
2
IO=From 50 to 750mA
EN=LLC=VSEL=1, TEN=TTX=0
0
-10
0
10
20
30
40
T [°C]
22/32
70
EN=VSEL=LLC=1
-10
90
Figure 12. Load regulation vs temperature
-160
60
VCC=12V, IO=50mA, VO=19.5V range
T [°C]
-120
50
Figure 11. Output voltage vs temperature
19.2
19
40
T [°C]
50
60
70
80
90
-10
0
10
20
30
40
T [°C]
50
60
70
80
90
LNBH23
Typical performance characteristics
Figure 14.
Supply current vs temperature
Figure 15. Dynamic overload protection ON
time vs temperature
40
140
VCC=12V
35
120
30
110
25
T ON [ms]
II [mA]
VCC=12V, VO=Shorted to GND
130
IO=No Load
20
15
100
90
80
70
10
60
5
50
EN=TEN=TTX=LLC=VSEL=1
40
0
-10
0
10
20
30
40
50
60
70
80
-10
90
0
10
20
30
40
50
60
70
80
90
T [°C]
T [°C]
Figure 16. Dynamic overload protection OFF
Time vs temperature
Figure 17. Output current limiting vs RSEL
1.4
1200
VCC=12V
VCC=12V
VO=Shorted to GND
1100
1.2
IMAX [mA]
TOFF [ms]
1
1000
900
800
0.8
0.6
0.4
700
0.2
600
-10
0
10
20
30
40
50
60
70
80
0
90
10
T [°C]
12
14
16
18
20
22
24
26
28
30
32
RSEL [KΩ]
Figure 18. Output current limiting vs
temperature
Figure 19. Output current limiting vs
temperature
550
1000
VCC=12V, RSEL=22KΩ
VCC=12V, RSEL=11KΩ
500
IMAX [mA]
IMAX [mA]
950
900
850
800
450
400
350
750
300
-10
0
10
20
30
40
T [°C]
50
60
70
80
90
-10
0
10
20
30
40
50
60
70
80
90
T [°C]
23/32
Typical performance characteristics
LNBH23
Figure 20. Tone frequency vs temperature
Figure 21. Tone amplitude vs temperature
26
1000
VCC=12V, IO=50mA
25
VCC=12V, IO=50mA
900
ATONE [mV]
FTONE [KHz]
24
23
22
21
20
19
600
EN=TEN=TTX=1
-10
400
0
10
20
30
40
T [°C]
50
60
70
80
-10
90
tr [µs]
EN=TEN=TTX=1
0
10
20
30
40
10
20
30
40
50
60
70
80
90
Figure 23. Tone rise time vs temperature
VCC=12V, IO=50mA
-10
0
T [°C]
Figure 22. Tone duty cycle vs temperature
DTONE [%]
700
500
EN=TEN=TTX=1
18
55
54
53
52
51
50
49
48
47
46
45
800
50
60
70
80
14
13
12
11
10
9
8
7
6
5
4
-10
90
VCC=12V, IO=50mA
EN=TEN=TTX=1
0
10
20
30
40
50
60
70
80
90
80
90
T [°C]
T [°C]
Figure 24. Tone fall time vs temperature
Figure 25. Output backward current vs
temperature
-10
VCC=12V, VOBK=21V externally forced
VCC=12V, IO=50mA
-1
IOBK [mA]
tf [µs]
0
14
13
12
11
10
9
8
7
6
5
4
-2
-3
EN=TEN=TTX=1
EN=0
0
10
20
30
40
50
60
70
80
90
-4
-10
0
10
20
30
40
T [°C]
T [°C]
24/32
50
60
70
LNBH23
Typical performance characteristics
Figure 26. DC-DC Converter efficiency vs
temperature
Figure 27. 22 kHz tone waveform
100
90
Eff [%]
80
VCC=12V, IO=750mA
70
LNBOUT
60
50
EN=VSEL=LLC=1
40
-10
0
10
20
30
40
50
60
70
80
90
VCC=12V
EN=TEN=TTX=1
T [°C]
Figure 28. DSQIN tone enable transient
response
Figure 29. DSQIN tone disable transient
response
VCC=12V
EN=TTX=1, TEN=0
DSQIN
DSQIN
LNBOUT
LNBOUT
VCC=12V
EN=TTX=1, TEN=0
25/32
Package mechanical data
10
LNBH23
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
26/32
LNBH23
Table 14.
Package mechanical data
QFN32 (5x5 mm) mechanical data
(mm.)
Dim.
Min.
Typ.
Max.
A
0.80
0.90
1.00
A1
0
0.02
0.05
A3
0.20
b
0.18
0.25
0.30
D
4.85
5.00
5.15
D2
3.20
E
4.85
E2
3.20
e
L
3.70
5.00
5.15
3.70
0.50
0.30
ddd
0.40
0.50
0.08
Figure 30. QFN32 package dimensions
7376875/E
27/32
Package mechanical data
DIM.
LNBH23
mm
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
2.15
2.47
0.084
0.097
A2
2.15
2.40
0.084
0.094
a1
0
0.075
0
0.003
b
0.33
0.51
0.013
0.020
c
0.23
0.32
0.009
0.012
D
(1)
10.10
10.50
0.398
0.413
E
(1)
7.4
7.6
0.291
0.299
e
0.8
0.031
e3
8.8
0.346
G
0.10
G1
H
h
L
0.004
0.06
10.10
10.50
0.002
0.398
0.40
0.413
0.016
0.55
0.85
X
4.10
4.70
0.161
0.185
Y
6.50
7.10
0.256
0.279
N
OUTLINE AND
MECHANICAL DATA
0.022
0.033
10˚ (max)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”)
(2) No intrusion allowed inwards the leads.
(3) Flash or bleeds on exposed die pad shall not exceed 0.4 mm
per side
PowerSSO -24
(Exposed Pad)
7412818 A
28/32
LNBH23
Package mechanical data
Tape & reel PowerSSO-24 mechanical data
mm.
inch.
Dim.
Min.
A
Typ.
Max.
Min.
330
Max.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
Typ.
0.504
30.4
0.519
1.197
Ao
10.8
11.0
0.425
0.433
Bo
10.7
10.9
0.421
0.429
Ko
2.65
2.85
0.104
0.112
Po
3.9
4.1
0.154
0.161
P1
11.9
12.1
0.469
0.476
W
23.7
24.3
0.933
0.957
29/32
Package mechanical data
LNBH23
Tape & reel QFNxx/DFNxx (5x5 mm.) mechanical data
mm.
inch.
Dim.
Min.
Typ.
A
Min.
Typ.
330
C
12.8
D
20.2
N
99
13.2
Max.
12.992
0.504
0.519
0.795
101
T
30/32
Max.
3.898
3.976
14.4
0.567
Ao
5.25
0.207
Bo
5.25
0.207
Ko
1.1
0.043
Po
4
0.157
P
8
0.315
LNBH23
Revision history
11
Revision history
Table 15.
Document revision history
Date
Revision
Changes
02-Apr-2007
1
Initial release.
15-Nov-2007
2
Added Note 2 on Table 3.
11-Jan-2008
3
Added: new package QFN32 and Table 5.
26-Mar-2008
4
Modified: mechanical data for QFN32 Figure 30 on page 27, and Table 14 on
page 27.
31/32
LNBH23
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