STMICROELECTRONICS M48Z128

M48Z128
M48Z128Y, M48Z128V*
5.0V OR 3.3V, 1 Mbit (128 Kbit x 8) ZEROPOWER® SRAM
FEATURES SUMMARY
■ INTEGRATED, ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT, and
BATTERY
■
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■
10 YEARS OF DATA RETENTION IN THE
ABSENCE OF POWER
■
BATTERY INTERNALLY ISOLATED UNTIL
POWER IS FIRST APPLIED
■
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
■
■
WRITE PROTECT VOLTAGES:
(VPFD = Power-fail Deselect Voltage)
– M48Z128: VCC = 4.75 to 5.5V
4.5V ≤ VPFD ≤ 4.75V
– M48Z128Y: VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– M48Z128V: VCC = 3.0 to 3.6V
2.8V ≤ VPFD ≤ 3.0V
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP WHICH
CONTAINS THE BATTERY
■
SNAPHAT HOUSING (BATTERY) IS
REPLACEABLE
■
PIN and FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
■
EQUIVALENT SURFACE-MOUNT (SMT)
SOLUTION REQUIRES A 28-PIN M40Z300/W
and A STAND-ALONE 128K x8 LPSRAM
(SNAPHAT® Top to be ordered separately)
Figure 1. 32-pin PMDIP Module
32
1
PMDIP32 (PM)
Module
* Contact Local Sales Office
October 2003
Rev. 3.4
1/21
M48Z128, M48Z128Y, M48Z128V*
TABLE OF CONTENTS
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Diagram (Figure 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Signal Names (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
DIP Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Hardware Hookup for Equivalent Surface-Mount (SMT) Solution (Figure 5.) . . . . . . . . . . . . . . . . . . 5
Equivalent Surface-Mount (SMT) Solution (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operating and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC Measurement Load Circuit (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
OPERATING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating Modes (Table 7.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip Enable or Output Enable Controlled, READ Mode AC Waveforms (Figure 7.). . . . . . . . . . . . . 9
Address Controlled, READ Mode AC Waveforms (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ Mode AC Characteristics (Table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Enable Controlled, WRITE AC Waveforms (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chip Enable Controlled, WRITE AC Waveforms (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode AC Characteristics (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Mode AC Waveforms (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up AC Characteristics (Table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power Down/Up Trip Points DC Characteristics (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Supply Voltage Protection (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SNAPHAT Battery Table (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
M48Z128, M48Z128Y, M48Z128V*
DESCRIPTION
The M48Z128/Y/V ZEROPOWER® RAM is a
128 Kbit x 8 non-volatile static RAM organized
as131,072 words by 8 bits. The device combines
an internal lithium battery, a CMOS SRAM and a
control circuit in a plastic, 32-pin DIP module. This
solution is available in two special packages to
provide a highly integrated battery backed-up
memory solution.
The M48Z128/Y/V is a non-volatile pin and function equivalent to any JEDEC standard 128K x 8
SRAM. It also easily fits into many ROM, EPROM,
and EEPROM sockets, providing the non-volatility
of PROMs without any requirement for special
WRITE timing or limitations on the number of
WRITEs that can be performed. The 32-pin,
600mil DIP Module houses the M48Z128/Y/V silicon with a long life lithium button cell in a single
package.
For surface-mount environments ST provides an
equivalent SMT solution consisting of a 28-pin,
330mil SOIC NVRAM SUPERVISOR (M40Z300/
W) and a 32-pin, (TSOP, 8 x 20mm) 1Mb
LPSRAM. Both 5V and 3V versions are available
(see Table 2, page 5).
The 28-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC package after the completion of the surface-mount process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SNAPHAT battery package is shipped separately in plastic anti-static tubes or in Tape & Reel
form. The part number is “M4Zxx-BR00SH” (see
Table 13, page 15).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A16
VCC
DQ0-DQ7
17
8
A0-A16
W
DQ0-DQ7
M48Z128
M48Z128Y
M48Z128V
E
G
Address Inputs
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
VSS
AI01194
3/21
M48Z128, M48Z128Y, M48Z128V*
Figure 3. DIP Connections
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VCC
A15
NC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
32
1
31
2
30
3
29
4
28
5
27
6
26
7
8 M48Z128 25
M48Z128Y
24
9
M48Z128V
23
10
22
11
21
12
20
13
19
14
18
15
17
16
AI01195
Figure 4. Block Diagram
VCC
A0-A16
POWER
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
131,072 x 8
DQ0-DQ7
SRAM ARRAY
E
W
G
INTERNAL
BATTERY
VSS
4/21
AI01196
M48Z128, M48Z128Y, M48Z128V*
Figure 5. Hardware Hookup for Equivalent Surface-Mount (SMT) Solution
THS(1,2)
VOUT
VCC
E2
SNAPHAT
(3)
BATTERY
1Mb LPSRAM
M40Z300/W
DQ0-DQ7
E1CON
E
E
E2CON
E3CON
E4CON
A0-A16
A
RST
B
W
BL
VSS
VSS
AI03625
Note: For pin connections, see individual data sheet for M48Z300/300W at www.st.com.
1. Connect THS pin to VOUT if 4.2V ≤ VPFD ≤ 4.5V (M48Z128Y) or connect THS pin to VSS if 4.5V ≤ VPFD ≤ 4.75V (M48Z128).
2. Connect THS pin to VSS if 2.8V ≤ VPFD ≤ 3.0V (M48Z128V).
3. SNAPHAT® Top ordered separately.
Table 2. Equivalent Surface-Mount (SMT) Solution
NVRAM
LPSRAM
SUPERVISOR
THS Pin(1)
M48Z128
5V 1Mb LPSRAM
M40Z300
VSS
M48Z128Y
5V 1Mb LPSRAM
M40Z300
VOUT
M48Z128V
3V 1Mb LPSRAM
M40Z300W
VSS
Note: 1. Connection of Threshold Select Pin (Pin 13) of SUPERVISOR (M40Z300/300W).
5/21
M48Z128, M48Z128Y, M48Z128V*
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other relevant quality documents.
Table 3. Absolute Maximum Ratings
Symbol
TA
Parameter
Ambient Operating Temperature
Value
Unit
0 to 70
°C
TSTG
Storage Temperature (VCC Off, Oscillator Off)
–40 to 85
°C
TBIAS
Temperature Under Bias
–10 to 70
°C
260
°C
–0.3 to 7
V
M48Z128/Y
–0.3 to 7.0
V
M48Z128V
–0.3 to 4.6
V
TSLD(1,2)
Lead Solder Temperature for 10 seconds
VIO
Input or Output Voltages
VCC
Supply Voltage
IO
Output Current
20
mA
PD
Power Dissipation
1
W
Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer
than 30 seconds).
2. For SO package: Reflow at peak temperature of 215°C to 225°C for < 60 seconds (total thermal budget not to exceed 180°C for
between 90 to 120 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
6/21
M48Z128, M48Z128Y, M48Z128V*
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 4. Operating and AC Measurement Conditions
Parameter
M48Z128/Y
M48Z128V
Unit
4.75 to 5.5V or 4.5 to 5.5
3.0 to 3.6
V
0 to 70
0 to 70
°C
Load Capacitance (CL)
100
50
pF
Input Rise and Fall Times
≤5
≤5
ns
0 to 3
0 to 3
V
1.5
1.5
V
Supply Voltage (VCC)
Ambient Operating Temperature (TA)
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 6. AC Measurement Load Circuit
650Ω
DEVICE
UNDER
TEST
CL = 100pF
or 50pF(1)
CL includes JIG capacitance
1.75V
AI03630
Note: 1. 50pF for M48Z128V (3.3V).
Table 5. Capacitance
Symbol
CIN
CIO(3)
Parameter(1,2)
Min
Max
Unit
Input Capacitance
10
pF
Input / Output Capacitance
10
pF
Note: 1. Effective capacitance measured with power supply at 5V (M48Z128/Y) or 3.3V (M48Z128V); sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
7/21
M48Z128, M48Z128Y, M48Z128V*
Table 6. DC Characteristics
Sym
Parameter
(1)
Test Condition
M48Z128/Y
M48Z128V
–70 / –85 / –120
–85 / –120
Min
ILI
ILO(2)
Input Leakage Current
Output Leakage Current
Max
Min
Unit
Max
0V ≤ VIN ≤ VCC
±1
±1
µA
0V ≤ VOUT ≤ VCC
±1
±1
µA
E = VIL
Outputs open
105
50
mA
E = VIH
7
4
mA
E = VCC – 0.2V
4
3
mA
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
VIL
Input Low Voltage
–0.3
0.8
–0.3
0.6
V
VIH
Input High Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
0.4
2.4
2.2
V
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted).
2. Outputs deselected.
OPERATING MODES
The M48Z128/Y/V also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single VCC supply for an out of tolerance
condition. When VCC is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls
below the switchover voltage (VSO), the control circuitry connects the battery which maintains data
until valid power returns.
Table 7. Operating Modes
Mode
Deselect
WRITE
READ
READ
VCC
4.75 to 5.5V
or
4.5 to 5.5V
or
3.0 to 3.6V
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
Deselect
VSO to VPFD (min)(1)
X
X
X
High Z
CMOS Standby
Deselect
≤ VSO(1)
X
X
X
High Z
Battery Back-up Mode
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
1. See Table 11, page 14 for details.
8/21
M48Z128, M48Z128Y, M48Z128V*
READ Mode
The M48Z128/Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The device architecture allows ripple-through
access of data from eight of 1,048,576 locations in
the static storage array. Thus, the unique address
specified by the 17 address inputs defines which
one of the 131,072 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (tAVQV) after the last
address input signal is stable, providing that the E
and G (Output Enable) access times are also sat-
isfied. If the E and G access times are not met, valid data will be available after the later of Chip
Enable Access time (tELQV) or Output Enable Access Time (tGLQV). The state of the eight threestate Data I/O signals is controlled by E and G. If
the outputs are activated before tAVQV, the data
lines will be driven to an indeterminate state until
tAVQV. If the address inputs are changed while E
and G remain low, output data will remain valid for
Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
Figure 7. Chip Enable or Output Enable Controlled, READ Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DATA OUT
DQ0-DQ7
AI01197
Note: WRITE Enable (W) = High.
Figure 8. Address Controlled, READ Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
DQ0-DQ7
tAXQX
DATA VALID
AI01078
Note: Chip Enable (E) and Output Enable (G) = Low, WRITE Enable (W) = High.
9/21
M48Z128, M48Z128Y, M48Z128V*
Table 8. READ Mode AC Characteristics
Symbol
M48Z128/Y
M48Z128/Y/V
M48Z128/Y/V
–70
–85
–120
(1)
Parameter
Min
Max
Min
Max
Min
Unit
Max
tAVAV
READ Cycle Time
tAVQV
Address Valid to Output Valid
70
85
120
ns
tELQV
Chip Enable Low to Output Valid
70
85
120
ns
tGLQV
Output Enable Low to Output Valid
35
45
60
ns
70
85
120
ns
tELQX(2)
Chip Enable Low to Output Transition
5
5
5
ns
tGLQX(2)
Output Enable Low to Output Transition
3
3
3
ns
tEHQZ(2)
Chip Enable High to Output Hi-Z
30
35
45
ns
tGHQZ(2)
Output Enable High to Output Hi-Z
20
25
35
ns
tAXQX
Address Transition to Output Transition
5
5
10
ns
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
10/21
M48Z128, M48Z128Y, M48Z128V*
WRITE Mode
The M48Z128/Y/V is in the WRITE Mode whenever W and E are active. The start of a WRITE is referenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the earlier rising
edge of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of
tEHAX from E or tWHAX from W prior to the initiation
of another READ or WRITE cycle. Data-in must be
valid tDVWH prior to the end of WRITE and remain
valid for tWHDX or tEHDX afterward. G should be
kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G, a low on W will disable
the outputs tWLQZ after W falls.
Figure 9. WRITE Enable Controlled, WRITE AC Waveforms
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01198
Note: Output Enable (G) = High.
Figure 10. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01199
Note: Output Enable (G) = High.
11/21
M48Z128, M48Z128Y, M48Z128V*
Table 9. WRITE Mode AC Characteristics
Symbol
M48Z128/Y
M48Z128/Y/V
M48Z128/Y/V
–70
–85
–120
(1)
Parameter
Min
Max
Min
Max
Min
Unit
Max
tAVAV
WRITE Cycle Time
70
85
120
ns
tAVWL
Address Valid to WRITE Enable Low
0
0
0
ns
tAVEL
Address Valid to Chip Enable Low
0
0
0
ns
tWLWH
WRITE Enable Pulse Width
55
65
85
ns
tELEH
Chip Enable Low to Chip Enable High
55
75
100
ns
tWHAX
WRITE Enable High to Address Transition
5
5
5
ns
tEHAX
Chip Enable High to Address Transition
15
15
15
ns
tDVWH
Input Valid to WRITE Enable High
30
35
45
ns
tDVEH
Input Valid to Chip Enable High
30
35
45
ns
tWHDX
WRITE Enable High to Input Transition
0
0
0
ns
tEHDX
Chip Enable High to Input Transition
10
10
10
ns
tWLQZ(2,3)
WRITE Enable Low to Output Hi-Z
25
30
40
ns
tAVWH
Address Valid to WRITE Enable High
65
75
100
ns
tAVEH
Address Valid to Chip Enable High
65
75
100
ns
WRITE Enable High to Output Transition
5
5
5
ns
tWHQX(2,3)
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
12/21
M48Z128, M48Z128Y, M48Z128V*
Data Retention Mode
With valid VCC applied, the M48Z128/Y/V operates as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself tWP after VCC falls below VPFD. All outputs
become high impedance, and all inputs are treated
as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to completion. If
the memory cycle fails to terminate within the time
tWP, write protection takes place. When VCC drops
below VSO, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z128/Y/V after the initial application of VCC for
an accumulated period of at least 10 years when
VCC is less than VSO. As system power returns
and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write protection continues for tER after
VCC reaches VPFD to allow for processor stabilization. After tER, normal RAM operation can resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
Figure 11. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tDR
tFB
tRB
tER
tWP
E
DON'T CARE
RECOGNIZED
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01031
Table 10. Power Down/Up AC Characteristics
Parameter(1)
Symbol
tF(2)
VPFD (max) to VPFD (min) VCC Fall Time
tFB(3)
VPFD (min) to VSS VCC Fall Time
Min
Max
300
M48Z128/Y
10
M48Z128V
150
Unit
µs
µs
tR
VPFD (min) to VPFD (max) VCC Rise Time
10
µs
tRB
VSS to VPFD (min) VCC Rise Time
1
µs
tWP
Write Protect Time
tER
E Recovery Time
M48Z128/Y
40
150
M48Z128V
40
250
40
120
µs
ms
Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
13/21
M48Z128, M48Z128Y, M48Z128V*
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol
VPFD
Parameter(1,2)
Power-fail Deselect Voltage
VSO
Battery Back-up Switchover Voltage
tDR(3)
Expected Data Retention Time
Min
Typ
Max
Unit
M48Z128
4.5
4.6
4.75
V
M48Z128Y
4.2
4.3
4.5
V
M48Z128V
2.8
2.9
3.0
V
M48Z128/Y
3.0
V
M48Z128V
2.5
V
10
YEARS
Note: 1. All voltages referenced to VSS.
2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V, 4.5 to 5.5V, or 3.0 to 3.6V (except where noted).
3. At 25°C; VCC = 0V.
VCC Noise And Negative Going Transients
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients
can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (see Figure 12) is
recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values
below VSS by as much as one volt. These negative
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, ST recommends connecting
a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). (Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface-mount).
14/21
Figure 12. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
M48Z128, M48Z128Y, M48Z128V*
PART NUMBERING
Table 12. Ordering Information Scheme
Example:
M48Z
128Y
–70
PM
1
Device Type
M48Z
Supply Voltage and Write Protect Voltage
128 = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
128Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
128V(1) = VCC = 3.0 to 3.6V; VPFD = 2.8 to 3.0V
Speed
–70 = 70ns (for M48Z128/Y)
–85 = 85ns (for M48Z128/Y/V)
–120 = 120ns (for M48Z128/Y/V)
Package(2)
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Note: 1. Contact Local Sales Office
2. The SOIC package (SOH28) requires the battery package (SNAPHAT ®) which is ordered separately under the part number
“M4Zxx-BR00SH” in plastic tube or “M4Zxx-BR00SHTR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package “M4Zxx-BR00SH” in conductive foam as it will drain the lithium button-cell battery.
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Table 13. SNAPHAT Battery Table
Part Number
Description
Package
M4Z28-BR00SH
Lithium Battery (48mAh) SNAPHAT
SH
M4Z32-BR00SH
Lithium Battery (120mAh) SNAPHAT
SH
15/21
M48Z128, M48Z128Y, M48Z128V*
PACKAGE MECHANICAL INFORMATION
Figure 13. PMDIP32 – 32-pin Plastic DIP Module, Package Outline
A
A1
B
S
L
C
eA
e1
e3
D
N
E
1
PMDIP
Note: Drawing is not to scale.
Table 14. PMDIP32 – 32-pin Plastic DIP Module, Package Mechanical Data
mm
inches
Symb
Typ
16/21
Min
Max
A
9.27
A1
Typ
Min
Max
9.52
0.365
0.375
0.38
–
0.015
–
B
0.43
0.59
0.017
0.023
C
0.20
0.33
0.008
0.013
D
42.42
43.18
1.670
1.700
E
18.03
18.80
0.710
0.740
e1
2.29
2.79
0.090
0.110
e3
34.29
41.91
1.350
1.650
eA
14.99
16.00
0.590
0.630
L
3.05
3.81
0.120
0.150
S
1.91
2.79
0.075
0.110
N
32
32
M48Z128, M48Z128Y, M48Z128V*
Figure 14. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 15. SOH28 – 28-lead Plastic Small Outline, battery SNAPHAT, Package Mechanical Data
mm
inch
Symbol
Typ
Min
A
Max
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
CP
1.27
0.050
28
0.10
0.004
17/21
M48Z128, M48Z128Y, M48Z128V*
Figure 15. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHZP-A
Note: Drawing is not to scale.
Table 16. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Typ
Min
9.78
Max
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
18/21
Max
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
M48Z128, M48Z128Y, M48Z128V*
Figure 16. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1
eA
A2
A
A3
B
L
eB
D
E
SHZP-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
19/21
M48Z128, M48Z128Y, M48Z128V*
REVISION HISTORY
Table 18. Revision History
Date
Rev. #
May 1999
1.0
First Issue
13-Apr-00
2.0
Document Layout changed; surface-Mount Chip Set solution added
20-Jun-00
2.1
tGLQX changed (Table 8)
19-Jul-00
2.2
M48Z128V added
14-Sep-01
3.0
Reformatted; added temperature information (Table 5, 6, 8, 9, 10, 11)
07-Nov-01
3.1
Remove chipset option from Ordering Information (Table 12)
20-May-02
3.2
Modify reflow time and temperature footnotes (Table 3)
18-Nov-02
3.3
Modifying SMT solution text (Figure 2, 5; Table 2)
17-Sep-03
3.4
Remove references to M68ZXXX (obsolete) parts (Figure 5; Table 2); update disclaimer
20/21
Revision Details
M48Z128, M48Z128Y, M48Z128V*
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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