a High End, Multichannel, 32-Bit Floating-Point Audio Processor SST-Melody -SHARC ® FEATURES Super Harvard Architecture Computer (SHARC) 4 Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory, Integrated I/O Peripheral I 2S Support for 8 Simultaneous Receive and Transmit Channels 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory 2 External Port, DMA Channels and 8 Serial Port, DMA Channels Decodes Industry Standard Formats Using a 32-Bit Floating Point Implementation for Decoding Dolby® Digital AC-3, Dolby Digital EX Processing Dolby Pro Logic®, 96 kHz, Dolby Pro Logic II Dolby Headphone, Dolby 3/0 DTS® 5.1, DTS-ES®-Discreet 6.1, DTS Matrix and Matrix 3.0, DTS 96/24 ®, DTS NEO:6 THX ® Ultra, Select, Ultra2, 5.1, 7.1, EX SRS ® Labs Circle Surround II TM, Virtual Loudspeaker MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode PCM, PCM 96 kHz HDCD, MLP* Delay 7.1, 96 kHz Bass 7.1, 96 kHz, Bass/Treble 2 Channel ADI Surround: Club, Music, and Stadium AAC (LC), AAC (LC) 2 Channel, AAC MP WaveSurround 5.1 Channel to Headphone, Stereo to Headphone, Channel to Loudspeaker, Stereo to Loudspeaker Downsampling 96 kHz to 48 kHz (2-Channel) 3-Band Equalizer, 2-Channel Encoders: AC-3 2-Channel Consumer Encoder Single Chip DSP-Based Implementation of Digital Audio Algorithms I2S Compatible Ports Interface to External SDRAM ® FUNCTIONAL BLOCK DIAGRAM SDRAM 128K ⴛ 32, BOOT ROM 1M ⴛ 8 IRQ GPIO SST-Melody-SHARC ADC SERIAL PORT DAC ALGORITHMS COMMAND S/PDIF TRANSMITTER KERNEL S/PDIF RECEIVER DMA CONNECTION OR DUAL BUFFER HOST MICRO Easy Interfaces to Audio Codecs 96 kHz Processing Supports Customer Specific Post Processing Automatic Stream Detection and Code Loading Easy to Use Software Architecture Optimized Library of Routines Host Communication Using 16-Bit Parallel Port or SPI Port Highly Flexible Serial Ports SRAM Interface for More Delay Supports IEC60958 For Bit Streams 8-Channel Output Using TDM Codecs APPLICATIONS Home Theater AVR Systems Automotive Audio Receivers Video Game Consoles DVD Players Cable and Satellite Set-Top Boxes Multimedia Audio/Video Gateways GENERAL DESCRIPTION Melody and SHARC are registered trademarks of Analog Devices, Inc. DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater Systems, Inc. Dolby and Pro Logic are registered trademarks of Dolby Laboratories Licensing Corporation. SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs. THX is a registered trademark of the THX, Ltd. *MLP is implemented, not certified. The SST-Melody-SHARC family of powerful 32-bit Audio Processors from Analog Devices provides flexible solutions and delivers a host of features across high end and high fidelity audio systems to the AV receiver and DVD markets. It includes multichannel audio decoders, encoders, and post processors for digital audio designs using DSP chipsets in home theater systems and automotive audio receivers. (continued on page 11) REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 SST-Melody-SHARC–SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS1 Test Conditions Parameter VDD TCASE VIH VIL1 VIL2 Supply Voltage Case Operating Temperature High Level Input Voltage @ VDD = max Low Level Input Voltage2 @ VDD = min Low Level Input Voltage3 @ VDD = min Min 3.13 –40 2.0 –0.5 –0.5 C Grade Max 3.60 +100 VDD + 0.5 +0.8 +0.7 K Grade Min Max Unit 3.13 0 2.0 –0.5 –0.5 V °C V V V 3.60 +85 VDD + 0.5 +0.8 +0.7 NOTES 1 See Environmental Conditions section for information on thermal specifications. 2 Applies to input and bidirectional pins: DATA31–0, ADDR23–0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG11–0, HBG, CS, DMAR1, DMAR2, BR2–1, ID2–0, RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST, PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE. 3 Applies to input pin CLKIN. ELECTRICAL CHARACTERISTICS Parameter VOH VOL IIH IIL IILP IOZH IOZL IOZLS IOZLA IOZLAR IOZLC CIN C and K Grades Min Max Test Conditions 1 High Level Output Voltage Low Level Output Voltage1 High Level Input Current3 Low Level Input Current3 Low Level Input Current4 Three-State Leakage Current5, 6, 7, 8 Three-State Leakage Current5 Three-State Leakage Current6 Three-State Leakage Current9 Three-State Leakage Current8 Three-State Leakage Current7 Input Capacitance10, 11 2 @ VDD = min, IOH = –2.0 mA @ VDD = min, IOL = +4.0 mA2 @ VDD = max, VIN = VDD max @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = VDD max @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = 1.5 V @ VDD = max, VIN = 0 V @ VDD = max, VIN = 0 V fIN = 1 MHz, TCASE = 25°C, VIN = 2.5 V 2.4 0.4 10 10 150 10 8 150 350 4 1.5 8 Unit V V µA µA µA µA µA µA µA mA mA pF NOTES 1 Applies to output and bidirectional pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, HBG, REDY, DMAG1, DMAG2, BR2–1, CPA, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0, PWM_EVENT1, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10. 2 See Output Drive Current section for typical drive current capabilities. 3 Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID1–0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership). 4 Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI. 5 Applies to three-statable pins: DATA31–0, ADDR 23–0, MS3–0, RD, WR, SW, ACK, FLAG11–0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10, and EMU (note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID1–0 = 01 and another SST-Melody-SHARC is not requesting bus mastership). 6 Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1. 7 Applies to CPA pin. 8 Applies to ACK pin when pulled up. 9 Applies to ACK pin when keeper latch enabled. 10 Guaranteed but not tested. 11 Applies to all signal pins. Specifications subject to change without notice. –2– REV. 0 SST-Melody-SHARC ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF Junction Temperature Under Bias . . . . . . . . . . . . . . . . . 130°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . . . . 280°C *Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Part Number Case Temperature Range Instruction Rate (MHz) On-Chip SRAM (Kbit) Operating Voltage (V) Package Options ADSST-21065LKS-240 ADSST-21065LCS-240 ADSST-21065LKCA-240 ADSST-21065LKS-264 ADSST-21065LKCA-264 0°C to 85°C –40°C to +100°C 0°C to 85°C 0°C to 85°C 0°C to 85°C 60 60 60 66 66 544 544 544 544 544 3.3 3.3 3.3 3.3 3.3 S-208-2 S-208-2 BC-196 S-208-2 BC-196 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SST-Melody-SHARC features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– SST-Melody-SHARC 157 RESET 159 GND 158 VDD 160 ADDR23 161 ADDR22 162 ADDR21 163 VDD 165 ADDR19 164 ADDR20 167 GND 166 ADDR18 168 GND 169 ADDR17 171 ADDR15 170 ADDR16 173 ADDR14 172 VDD 175 ADDR12 174 ADDR13 176 VDD 177 GND 178 ADDR11 181 GND 180 ADDR9 179 ADDR10 183 ADDR8 182 VDD 185 ADDR6 184 ADDR7 187 GND 186 GND 189 ADDR4 188 ADDR5 191 VDD 190 ADDR3 193 ADDR2 192 VDD 195 ADDR0 194 ADDR1 197 FLAG0 196 GND 200 VDD 199 FLAG2 198 FLAG1 202 NC 201 FLAG3 204 GND 203 NC 1 156 2 155 PIN 1 IDENTIFIER 3 4 154 153 5 152 6 151 7 150 8 149 9 148 10 147 11 146 12 13 144 14 143 15 142 16 141 145 17 140 18 139 19 138 20 137 21 22 135 23 134 136 24 133 25 132 OO 26 131 ADSST-21065L 27 130 TOP VIEW (Not to Scale) 28 29 129 128 30 31 127 126 32 125 33 124 34 123 35 122 36 121 37 120 38 119 39 40 118 41 116 42 115 43 114 117 44 113 45 112 46 111 47 110 48 109 49 108 50 107 104 103 102 101 99 98 100 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 81 80 82 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 61 62 60 59 58 57 56 55 105 54 106 52 53 51 VDD GND GND BMS BSEL TCK GND TMS TDI TRST TDO EMU ID0 ID1 NC VDD VDD GND FLAG4 FLAG5 FLAG6 GND FLAG7 DATA31 DATA30 VDD VDD GND DATA29 DATA28 DATA27 GND VDD DATA26 DATA25 DATA24 VDD GND DATA23 DATA22 DATA21 NC GND DATA20 DATA19 DATA18 VDD DATA17 DATA16 DATA15 GND VDD BMSTR VDD CS SBTS GND WR RD GND VDD GND REDY SW CPA VDD VDD GND ACK MS0 MS1 GND GND MS2 MS3 FLAG11 VDD FLAG10 FLAG9 FLAG8 GND DATA0 DATA1 DATA2 VDD DATA3 DATA4 DATA5 GND DATA6 DATA7 DATA8 VDD GND VDD DATA9 DATA10 DATA11 GND DATA12 DATA13 NC NC DATA14 VDD RSF0 GND RCLK0 DR0A DR0B TFS0 TCLK0 VDD GND DT0A DT0B RFS1 GND RCLK1 DR1A DR1B TFS1 TCLK1 VDD VDD DT1A DT1B PWM EVENT1 GND PWM EVENT0 BR1 BR2 VDD CLKIN XTAL VDD GND SDCLK1 GND VDD SDCLK0 DMAR1 DMAR2 HBR GND RAS CAS SDWE VDD DQM SDCKE SDA10 GND DMAG1 DMAG2 HBG 206 IRQ1 205 IRQ0 208 NC 207 IRQ2 208-LEAD MQFP PIN CONFIGURATIONS NC = NO CONNECT –4– REV. 0 SST-Melody-SHARC 196-BALL CSPBGA PIN CONFIGURATION REV. 0 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NC7 NC8 ADDR18 ADDR17 ADDR14 ADDR11 ADDR8 ADDR7 ADDR6 ADDR3 ADDR0 FLAG2 NC2 NC1 A TCK GND ADDR23 ADDR21 ADDR19 ADDR15 ADDR12 ADDR9 ADDR5 ADDR2 FLAG0 IRQ0 RFS0 DR0A B TDO BSEL RESET ADDR22 ADDR20 ADDR16 ADDR13 ADDR10 ADDR4 ADDR1 FLAG3 IRQ2 RCLK0 TCLK0 C EMU TRST TMS BMS VDD VDD VDD VDD VDD FLAG1 IRQ1 DR0B TFS0 RCLK1 D FLAG4 ID1 TDI ID0 VDD GND GND GND GND VDD RFS1 DT0A DT0B TFS1 E FLAG7 FLAG5 FLAG6 VDD GND GND GND GND GND GND VDD DR1A DR1B TCLK1 F DATA29 DATA30 DATA31 VDD GND GND GND GND GND GND VDD DT1A DT1B PWM_ EVENT1 G DATA26 DATA27 DATA28 VDD GND GND GND GND GND GND VDD BR2 BR1 PWM_ EVENT0 H DATA23 DATA25 DATA24 VDD GND GND GND GND GND GND VDD SDCLK1 XTAL CLKIN J DATA22 DATA20 DATA21 DATA19 VDD GND GND GND GND VDD SDWE HBR SDCLK0 DMAR1 K DATA18 DATA17 DATA16 DATA13 DATA8 VDD VDD VDD VDD VDD DMAG2 SDA10 CAS DMAR2 L DATA15 DATA14 DATA12 DATA9 DATA5 DATA2 FLAG10 ACK CPA RD CS DMAG1 SDCKE RAS M NC6 DATA11 DATA10 DATA7 DATA4 DATA1 FLAG11 MS1 GND REDY SBTS BMSTR HBG DQM N NC5 DATA6 DATA3 DATA0 FLAG8 FLAG9 MS3 MS2 MS0 SW WR GND NC4 NC3 P –5– SST-Melody-SHARC 208-LEAD MQFP PIN CONFIGURATION Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 VDD RFS0 GND RCLK0 DR0A DR0B TFS0 TCLK0 VDD GND DT0A DT0B RFS1 GND RCLK1 DR1A DR1B TFS1 TCLK1 VDD VDD DT1A DT1B PWM_EVENT1 GND PWM_EVENT0 BR1 BR2 VDD CLKIN XTAL VDD GND SDCLK1 GND VDD SDCLK0 DMAR1 DMAR2 HBR GND RAS CAS SDWE VDD DQM SDCKE SDA10 GND DMAG1 DMAG2 HBG 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 BMSTR VDD CS SBTS GND WR RD GND VDD GND REDY SW CPA VDD VDD GND ACK MS0 MS1 GND GND MS2 MS3 FLAG11 VDD FLAG10 FLAG9 FLAG8 GND DATA0 DATA1 DATA2 VDD DATA3 DATA4 DATA5 GND DATA6 DATA7 DATA8 VDD GND VDD DATA9 DATA10 DATA11 GND DATA12 DATA13 NC NC DATA14 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 VDD GND DATA15 DATA16 DATA17 VDD DATA18 DATA19 DATA20 GND NC DATA21 DATA22 DATA23 GND VDD DATA24 DATA25 DATA26 VDD GND DATA27 DATA28 DATA29 GND VDD VDD DATA30 DATA31 FLAG7 GND FLAG6 FLAG5 FLAG4 GND VDD VDD NC ID1 ID0 EMU TDO TRST TDI TMS GND TCK BSEL BMS GND GND VDD 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 RESET VDD GND ADDR23 ADDR22 ADDR21 VDD ADDR20 ADDR19 ADDR18 GND GND ADDR17 ADDR16 ADDR15 VDD ADDR14 ADDR13 ADDR12 VDD GND ADDR11 ADDR10 ADDR9 GND VDD ADDR8 ADDR7 ADDR6 GND GND ADDR5 ADDR4 ADDR3 VDD VDD ADDR2 ADDR1 ADDR0 GND FLAG0 FLAG1 FLAG2 VDD FLAG3 NC NC GND IRQ0 IRQ1 IRQ2 NC –6– REV. 0 SST-Melody-SHARC 196-BALL CSPBGA PIN CONFIGURATION Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic Ball No. Mnemonic A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 NC1 NC2 FLAG2 ADDR0 ADDR3 ADDR6 ADDR7 ADDR8 ADDR11 ADDR14 ADDR17 ADDR18 NC8 NC7 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 DR0A RFS0 IRQ0 FLAG0 ADDR2 ADDR5 ADDR9 ADDR12 ADDR15 ADDR19 ADDR21 ADDR23 GND TCK C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 TCLK0 RCLK0 IRQ2 FLAG3 ADDR1 ADDR4 ADDR10 ADDR13 ADDR16 ADDR20 ADDR22 RESET BSEL TDO D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 RCLK1 TFS0 DR0B IRQ1 FLAG1 VDD VDD VDD VDD VDD BMS TMS TRST EMU E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 TFS1 DT0B DT0A RFS1 VDD GND GND GND GND VDD ID0 TDI ID1 FLAG4 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 TCLK1 DR1B DR1A VDD GND GND GND GND GND GND VDD FLAG6 FLAG5 FLAG7 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 PWM_EVENT1 DT1B DT1A VDD GND GND GND GND GND GND VDD DATA31 DATA30 DATA29 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 PWM_EVENT0 BR1 BR2 VDD GND GND GND GND GND GND VDD DATA28 DATA27 DATA26 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 CLKIN XTAL SDCLK1 VDD GND GND GND GND GND GND VDD DATA24 DATA25 DATA23 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 DMAR1 SDCLK0 HBR SDWE VDD GND GND GND GND VDD DATA19 DATA21 DATA20 DATA22 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 DMAR2 CAS SDA10 DMAG2 VDD VDD VDD VDD VDD DATA8 DATA13 DATA16 DATA17 DATA18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 RAS SDCKE DMAG1 CS RD CPA ACK FLAG10 DATA2 DATA5 DATA9 DATA12 DATA14 DATA15 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 DQM HBG BMSTR SBTS REDY GND MS1 FLAG11 DATA1 DATA4 DATA7 DATA10 DATA11 NC6 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 NC3 NC4 GND WR SW MS0 MS2 MS3 FLAG9 FLAG8 DATA0 DATA3 DATA6 NC5 REV. 0 –7– SST-Melody-SHARC PIN FUNCTION DESCRIPTIONS SST-Melody-SHARC pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR23–0, DATA31–0, FLAG11–0, SW, and inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI), which can be left floating. These pins have a logic-level hold circuit that prevents the input from floating internally. Mnemonic Type Function ADDR23–0 I/O/T External Bus Address. The SST-Melody-SHARC outputs addresses for external memory and peripherals on these pins. In a multiprocessor system, the bus master outputs addresses for read/writes of the IOP registers of the other SST-Melody-SHARC. The SST-Melody-SHARC inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers. DATA31–0 I/O/T External Bus Data. The SST-Melody-SHARC inputs and outputs data and instructions on these pins. The external databus transfers 32-bit, single-precision, floating-point data and 32-bit fixed-point data over bits 31-0. 16-Bit short word data is transferred over Bits 15-0 of the bus. Pull-up resistors on unused DATA pins are not necessary. MS3–0 I/O/T Memory Select Lines. These lines are asserted as chip selects for the corresponding banks of external memory. Internal ADDR 25–24 are decoded into MS3–0. The MS3–0 lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring, the MS3–0 lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. Additionally, an MS3–0 line that is mapped to SDRAM may be asserted even when no SDRAM access is active. In a multiprocessor system, the MS3–0 lines are output by the bus master. RD I/O/T Memory Read Strobe. This pin is asserted when the SST-Melody-SHARC reads from external memory devices or from the IOP register of another SST-Melody-SHARC. External devices (including another SST-Melody-SHARC) must assert RD to read from the SST-Melody-SHARC’s IOP registers. In a multiprocessor system, RD is output by the bus master and is input by another SST-Melody-SHARC. WR I/O/T Memory Write Strobe. This pin is asserted when the SST-Melody-SHARC writes to external memory devices or to the IOP register of another SST-Melody-SHARC. External devices must assert WR to write to the SST-Melody-SHARC’s IOP registers. In a multiprocessor system, WR is output by the bus master and is input by the other SST-Melody-SHARC. SW I/O/T Synchronous Write Select. This signal interfaces the SST-Melody-SHARC to synchronous memory devices (including another SST-Melody-SHARC). The SST-Melody-SHARC asserts SW to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessor system, SW is output by the bus master and is input by the other SST-Melody-SHARC to determine if the multiprocessor access is a read or write. SW is asserted at the same time as the address output. ACK I/O/S Memory Acknowledge. External devices can deassert ACK to add wait states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory access. The SST-Melody-SHARC deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a slave SST-Melody-SHARC deasserts the bus master’s ACK input to add wait state(s) to an access of its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven. SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the external bus address, data, selects, and strobes—but not SDRAM control pins—in a high impedance state for the following cycle. If the SST-Melody-SHARC attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not finish until SBTS is deasserted. SBTS should only be used to recover from host processor/SST-Melody-SHARC deadlock. IRQ2–0 I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive. FLAG11–0 I/O/A Flag Pins. Each is configured via control bits as either an input or an output. As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals. HBR I/A Host Bus Request. Must be asserted by a host processor to request control of the SST-Melody-SHARC’s external bus. When HBR is asserted in a multiprocessing system, the SST-Melody- SHARC that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the SST-Melody-SHARC places the address, data, select, and strobe lines in a high impedance state. It does, however, continue to drive the SDRAM control pins. HBR has priority over all SST-Melody-SHARC bus requests (BR2–1) in a multiprocessor system. –8– REV. 0 SST-Melody-SHARC Mnemonic Type Function HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of the external bus. HBG is asserted by the SST-Melody-SHARC until HBR is released. In a multiprocessor system, HBG is output by the SST-Melody-SHARC bus master. CS I/A Chip Select. Asserted by host processor to select the SST-Melody-SHARC. REDY (O/D) O Host Bus Acknowledge. The SST-Melody-SHARC deasserts REDY to add wait states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted. DMAR1 DMAR2 I/A I/A DMA Request 1 (DMA Channel 9) DMA Request 2 (DMA Channel 8) DMAG1 DMAG2 O/T O/T DMA Grant 1 (DMA Channel 9) DMA Grant 2 (DMA Channel 8) BR2–1 I/O/S Multiprocessing Bus Requests. Used by multiprocessing SST-Melody-SHARCs to arbitrate for bus mastership. An SST-Melody-SHARC drives its own BRx line (corresponding to the value of its ID2–0 inputs) only and monitors all others. In a uniprocessor system, tie both BRx pins to VDD. ID1–0 I Multiprocessing ID. Determines which multiprocessor bus request ( BR1 – BR2) is used by SST-Melody-SHARC. ID = 01 corresponds to BR1, ID = 10 corresponds to BR2. ID = 00 in singleprocessor systems. These lines are a system configuration selection that should be hard-wired or changed only at reset. CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an SST-Melody-SHARC bus slave to interrupt background DMA transfers and gain access to the external bus. CPA is an open drain output that is connected to both SST-Melody-SHARCs in the system. The CPA pin has an internal 5 kΩ pull-up resistor. If core access priority is not required in a system, leave the CPA pin unconnected. DTxX O Data Transmit (Serial Ports 0, 1; Channels A, B). Each DTxX pin has a 50 kΩ internal pull-up resistor. DRxX I Data Receive (Serial Ports 0, 1; Channels A, B). Each DRxX pin has a 50 kΩ internal pull-up resistor. TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 kΩ internal pull-up resistor. RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 kΩ internal pull-up resistor. TFSx I/O Transmit Frame Sync (Serial Ports 0, 1) RFSx I/O Receive Frame Sync (Serial Ports 0, 1) BSEL I EPROM Boot Select. When BSEL is high , the SST-Melody-SHARC is configured for booting from an 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs determine booting mode. See BMS for details. This signal is a system configuration selection that should be hardwired. BMS I/O/T* Boot Memory Select. Output: used as chip select for boot EPROM devices (when BSEL = 1). In a multiprocessor system, BMS is output by the bus master. Input: When low, indicates that no booting will occur and that the SST-Melody-SHARC will begin executing instructions from external memory. See following table. This input is a system configuration selection that should be hardwired. BSEL 1 0 0 CLKIN I BMS Output 1 (Input) 0 (Input) Booting Mode EPROM (connect BMS to EPROM chip select). Host processor (HBW [SYSCON] bit selects host bus width). No booting. Processor executes from external memory. Clock In. Used in conjunction with XTAL, configures the SST-Melody-SHARC to use either its internal clock generators or an external clock source. The external crystal should be rated at 1× frequency. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. The SST-Melody-SHARC’s internal clock generator multiplies the 1× clock to generate 2× clock for its core and SDRAM. It drives 2× clock out on the SDCLKx pins for the SDRAM interface to use. See also SDCLKx. Connecting the 1× external clock to CLKIN while leaving XTAL unconnected configures the SST-Melody-SHARC to use the external clock source. The instruction cycle rate is equal to 2× CLKIN. CLKIN may not be halted, changed, or operated below the specified frequency. RESET I/A Processor Reset. Resets the SST-Melody-SHARC to a known state and begins execution at the program memory location specified by the hardware reset vector address. This input must be asserted at power-up. *Three-statable only in EPROM boot mode (when BMS is an output). REV. 0 –9– SST-Melody-SHARC PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Type Function TCK I Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan. TMS I/S Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor. TDI I/S Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up resistor. TDO O Test Data Output (JTAG). Serial scan output of the boundary scan path. TRST I/A Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) after power-up or held low for proper operation of the SST-Melody-SHARC. TRST has a 20 kΩ internal pull-up resistor. EMU (O/D) O Emulation Status. Must be connected to the SST-Melody-SHARC EZ-ICE target board connector only. BMSTR O Bus Master Output. In a multiprocessor system, indicates whether the SST-Melody-SHARC is current bus master of the shared external bus. The SST-Melody-SHARC drives BMSTR high only while it is the bus master. In a single-processor system (ID = 00), the processor drives this pin high. CAS I/O/T SDRAM Column Access Strobe. Provides the column address. In conjunction with RAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. RAS I/O/T SDRAM Row Access Strobe. Provides the row address. In conjunction with CAS, MSx, SDWE, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. SDWE I/O/T SDRAM Write Enable. In conjunction with CAS, RAS, MSx, SDCLKx, and sometimes SDA10, defines the operation for the SDRAM to perform. DQM O/T SDRAM Data Mask. In write mode, DQM has a latency of zero and is used to block write operations. SDCLK1–0 I/O/S/T SDRAM 2× Clock Output. In systems with multiple SDRAM devices connected in parallel, supports the corresponding increased clock load requirements, eliminating need of off-chip clock buffers. Either SDCLK1 or both SDCLKx pins can be three-stated. SDCKE I/O/T SDRAM Clock Enable. Enables and disables the CLK signal. For details, see the data sheet supplied with your SDRAM device. SDA10 O/T SDRAM A10 Pin. Enables applications to refresh an SDRAM in parallel with a host access. XTAL O Crystal Oscillator Terminal. Used in conjunction with CLKIN to enable the SST-Melody-SHARC’s internal clock generator or to disable it to use an external clock source. See CLKIN. PWM_EVENT1–0 I/O/A PWM Output/Event Capture. In PWMOUT mode, is an output pin and functions as a timer counter. In WIDTH_CNT mode, is an input pin and functions as a pulse counter/event capture. VDD P Power Supply; nominally 3.3 V dc (33 pins) GND G Power Supply Return (37 pins) NC Do Not Connect. Reserved pins that must be left open and unconnected (7). I = Input, S = Synchronous, P = Power Supply, (O/D) = Open Drain, O = Output, A = Asynchronous, G = Ground, (A/D) = Active Drive, T = Three-state (when SBTS is asserted, or when the SST-Melody-SHARC is a bus slave). –10– REV. 0 SST-Melody-SHARC GENERAL DESCRIPTION (continued from page 1) With 32-bit audio quality, the SST-Melody-SHARC audio processor auto-detects and decodes audio formats in real-time, enabling end users to enjoy a theater-quality audio experience in their homes. The solutions can be customized to meet the exact requirements of the application. This audio DSP system allows designers to make value additions to product features working off the high end base functionality that they are provided with. Evaluation boards, sample applications and all necessary software support (drivers, and so on) are available. The SST-Melody-SHARC enables OEMs to offer comprehensive and single chip solutions for advanced features in products for end users. SST-MelodySHARC audio processors enable OEMs to produce high quality, low cost designs featuring decoder algorithms and post processors for DTS-ES Extended Surround (including both DTS-ES Discreet 6.1 and DTS-ES Matrix 6.1), DTS Neo:6, Dolby Digital, Dolby Digital EX, Dolby Pro Logic, Dolby Pro Logic II, Dolby Headphone, DDCE, THX and THX Surround EX, HDCD, MPEG1 Audio Layer 3 (also known as MP3), MPEG2 Audio, AAC, MLP, WaveSurround, SRS 3D Sound and Stereo. The audio processors also include audio encoders for DDCE, MPEG, and MP3. The cost of development is reduced with the scalable family of code-compatible devices enabling common solutions across product lines. Field upgradeable products with programmable DSP and an optimized library of routines including Dolby and DTS suites, multichannel AAC and all others, along with the best development tools in the industry, reduce the time to market. SST-Melody-SHARC is the comprehensive answer to the needs of the high end, high quality digital audio market. It delivers a realistic high fidelity audio experience along with a maximum number of features, across price points in the high end DVD markets. HARDWARE ARCHITECTURE Hardware architecture covers the interface between DSP and host microcontroller, command processing, data transfer in serial and parallel form, data buffer management, algorithm combinations, MIPS, and memory requirements that are provided. The multichannel algorithms are implemented and tested on a demo board “PEGASUS II.” This stand-alone board accepts compressed digital bit streams as serial input from LD/DVD/CD players or any stream generator and decodes in real time to generate a 2-channel or multichannel PCM stream. It has a microcontroller to scan a small keypad to give commands and select various options, and an LCD for status display. The SST-Melody-SHARC family (SST-Melody-SHARC ) hardware architecture can be broken up into four blocks: • The Core Processor • Dual-Ported SAAM • External Port • Input/Output Processor The hardware architecture of the Melody SHARC is complex. It has four independent buses for dual data, one for instructions, and one for I/O fetch. Since the four buses are independent, multiple transactions take place in a single clock cycle. It has two REV. 0 external ports, DMA channels, and eight serial ports. It is a 0.35 µm technology IC operating at 3.3 V. The SST-Melody-SHARC processor can be interfaced to external peripherals with relative ease. The communication between the SST-Melody-SHARC processor and a host microcontroller utilizes the SPI bus. The host microcontroller can be the master and the SST-Melody-SHARC processor can act as a slave. The peripherals can be controlled by the host microcontroller using the SPI bus. The communication is based on commands and parameters. Status information regarding the SST-Melody-SHARC decoding is periodically updated and made available to the host microcontroller. The block diagram of the SST-Melody-SHARC illustrates the following architectural features: • • • • • • • • • • Computation units (ALU, multiplier, and shifter) with a shared data register file Data address generators (DAG1, DAG2) Program sequencer with instruction cache Timers with event capture modes On-chip, dual-ported SRAM External port for interfacing to off-chip memory and peripherals Host port and SDRAM interface DMA controller Enhanced serial ports JTAG test access port We will use the Functional Block Diagram as our reference. We assume the SST-Melody-SHARC communicates with host micro using either direct DMA access or a dual buffer hardware mechanism. SST-Melody-SHARC has an on-chip memory buffer that is used for storing commands/parameters sent by the host to SST-Melody-SHARC and also status information from SST-Melody-SHARC to be sent to host micro. SST-MelodySHARC has direct access to this memory buffer as it resides on-chip. Host micro has access to this memory using either direct DMA access or a dual buffer hardware mechanism. There is a definite protocol for passing commands and obtaining status information. Once SST-Melody-SHARC receives a command from host micro, it will process the same and inform host micro of the status. These commands initiate actions like encoding and decoding. Encoding and decoding will result in data processing and the processed data may be delivered over the serial port. For example, while encoding, the PCM data is accepted through the serial port from peripherals like an ADC or S/PDIF receiver. The PCM data is then encoded and stored in an on-chip compressed data buffer. These compressed frames are then accessible to host micro using a high speed DMA or USB port. SST-Melody-SHARC , will prepare the compressed frames in the form of IEC 958 format so that it can be sent out using the serial port or S/PDIF transmitter. Compressed frames can be downloaded by host micro to SST-Melody-SHARC and can be decoded and the resulting PCM data can be sent on serial port transmitter. While commands and data are transferred between host micro and SST-Melody-SHARC over a dual buffer/DMA we need the help of interrupts and a few general-purpose input/ output lines to provide reliable communication. –11– SST-Melody-SHARC SOFTWARE ARCHITECTURE Table I. Performance Benchmarks Cycles Cycle Time 1024-Pt Complex FFT (Radix 4, with Digit Reverse) Matrix Multiply (Pipelined) [3 ⫻ 3] ⫻ [3 ⫻ 1] [4 ⫻ 4] ⫻ [4 ⫻ 1] FIR Filter (per Tap) IIR Filter (per Biquad) Divide Y/X Inverse Square Root (1/√x) DMA Transfers 15.00 ns 1 0.274 ns 18221 135 ns 240 ns 15 ns 60 ns 90 ns 135 ns 264 MBytes/sec 9 16 1 4 6 9 The executive kernel gets executed as soon as booting takes place. The hardware resources are initialized in the beginning. The command buffer and general-purpose programmable flag pins are initialized. Various data buffers and memory variables are initialized. Interrupts are programmed and enabled. Then, definite signatures are written “Command buffer” to inform the host that SST-Melody-SHARC is ready to receive the commands. Once commands are issued by host micro, they are executed and appropriate action takes place. Decoding is handled by issuing appropriate commands by host micro. CLOCK CLKIN RESET RESET 01 ADDR23-0 SPORT0 SPORT1 EXECUTIVE KERNEL OUTPUT STREAM DECODING LIBRARY CS ADDR DATA TX1_A TX1_B RX1_A RX1_B CONTROL DATA31-0 RD WR ACK MS3-0 BMS SBTS SW CS HBR HBG REDY RAS CAS DQM SDWE SDCLK1-0 SDCKE SDA10 BOOT EPROM (OPTIONAL) HOST PROCESSOR (OPTIONAL) ID1-0 TX0_A TX0_B RX0_A RX0_B The kernel communicates with library module for a particular algorithm in a definite way. The details are found in the specific implementation documents. As the kernel is modular, it is easy to customize to different hardware platforms. Most of the time, the user needs to change the initialization code to suit the codec chosen. INPUT STREAM SST-MelodySHARC #1 ADDRESS Timing DATA The executive kernel has the following functions: • Power up hardware initialization • Serial port management • Automatic stream detect • Automatic code load • Command processing • Interrupt handling • Data buffer management • Calling library module • Status report Benchmark CONTROL The audio DSP chipsets from Analog Devices allows designers to make value additions to product features working off the high end base functionality that they are provided with. The SST-Melody-SHARC software has the following parts: • Executive kernel • Algorithm as library module CS ADDR DATA ADDR DATA CS SDRAM (OPTIONAL) RAS CAS DQM WE CLK CKE A10 CPA BR2 BR1 Figure 1. Software Figure 2. SST-Melody-SHARC Single-Processor System SST-MELODY-SHARC GENERAL DESCRIPTION The SST-Melody-SHARC is a powerful member of the SHARC family of 32-bit processors optimized for cost sensitive applications. The SHARC—Super Harvard Architecture—offers the highest levels of performance and memory integration of any 32-bit DSP in the industry—they are also the only DSPs in the industry that offer both fixed and floating-point capabilities without compromising precision or performance. Fabricated in a high speed, low power CMOS process, 0.35 µm technology, the SST-Melody-SHARC offers the highest performance by a 32-bit DSP—66 MIPS (198 MFLOPS). With its on-chip instruction cache, the processor can execute every instruction in a single cycle. Table I lists the performance benchmarks for the SST-Melody-SHARC. The SST-Melody-SHARC SHARC combines a floating-point DSP core with integrated, on-chip system features, including a 544 Kbit SRAM memory, host processor interface, DMA controller, SDRAM controller, and enhanced serial ports. –12– REV. 0 SST-Melody-SHARC The arithmetic/logic unit (ALU), multiplier, and shifter all perform single-cycle instructions. The three units are arranged in parallel, maximizing computational throughput. Single multifunction instructions execute parallel ALU and multiplier operations. These computation units support IEEE 32-bit single-precision floating-point, extended precision 40-bit floating-point, and 32-bit fixed-point data formats. The following clock operation ratings are based on 1× = 33 MHz (instruction rate/core = 66 MHz): SDRAM 66 MHz External SRAM 33 MHz Serial Ports 33 MHz Multiprocessing 33 MHz Host (Asynchronous) 33 MHz Data Register File SST-Melody-SHARC adds the following architectural features: A general-purpose data register file is used for transferring data between the computation units and the databuses, and for storing intermediate results. This 10-port, 32-register (16 primary, 16 secondary) register file, combined with the SST-Melody-SHARC Harvard architecture, allows unconstrained data flow between computation units and internal memory. Dual-Ported On-Chip Memory Independent, Parallel Computation Units Single-Cycle Fetch of Instruction and Two Operands The SST-Melody-SHARC features an enhanced Super Harvard Architecture in which the data memory (DM) bus transfers data and the program memory (PM) bus transfers both instructions and data. With its separate program and data memory buses and on-chip instruction cache, the processor can simultaneously fetch two operands and an instruction (from the cache), all in a single cycle. On the SST-Melody-SHARC, the memory can be configured as a maximum of 16K words of 32-bit data, 34K words for 16-bit data, 10K words of 48-bit instructions (and 40-bit data) or combinations of different word sizes up to 544 Kbits. All the memory can be accessed as 16-bit, 32-bit, or 48-bit. Instruction Cache The SST-Melody-SHARC includes an on-chip instruction cache that enables 3-bus operation for fetching an instruction and two data values. The cache is selective—only the instructions that fetches conflict with PM bus data accesses are cached. This allows full-speed execution of core, looped operations such as digital filter multiply-accumulates, and FFT butterfly processing. Data Address Generators with Hardware Circular Buffers The SST-Melody-SHARC’s two data address generators (DAGs) implement circular data buffers in hardware. Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Fourier transforms. The SST-MelodySHARC’s two DAGs contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reducing overhead, increasing performance, and simplifying implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations for concise programming. For example, the SSTMelody-SHARC can conditionally execute a multiply, an add, a subtract, and a branch all in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM and PM buses in this way, with one dedicated to each memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. Single cycle execution is also maintained when one of the data operands is transferred to or from off-chip, via the SST-Melody-SHARC’s external port. Off-Chip Memory and Peripherals Interface The SST-Melody-SHARC’s external port provides the processor’s interface to off-chip memory and peripherals. The 64 M-word’s, off-chip address space is included in the SSTMelody-SHARC’s unified address space. The separate on-chip buses—for program memory, data memory, and I/O—are multiplexed at the external port to create an external system bus with a single 24-bit address bus, four memory selects, and a single 32-bit databus. The on-chip Super Harvard Architecture provides 3-bus performance, while the off-chip unified address space gives flexibility to the designer. SDRAM Interface SST-MELODY-SHARC FEATURES The SST-Melody-SHARC is designed to achieve the highest system throughput to enable maximum system performance. It can be clocked by either a crystal or a TTL-compatible clock signal. The SST-Melody-SHARC uses an input clock with a frequency equal to half the instruction rate—a 33 MHz input clock yields a 15 ns processor cycle (which is equivalent to 66 MHz). Interfaces on the SST-Melody-SHARC operate as shown. Hereafter in this document, 1× = input clock frequency and 2× = processor’s instruction rate. REV. 0 The SST-Melody-SHARC contains 544 Kbits of on-chip SRAM organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has 256 Kbits. Bank 0 is configured with nine columns of 2K ⫻ 16 bits, and Bank 1 is configured with eight columns of 2K ⫻ 16 bits. Each memory block is dual-ported for single-cycle, independent accesses by the core processor and I/O processor or DMA controller. The dual-ported memory and separate on-chip buses allow two data transfers from the core and one from I/O, all in a single cycle (see Figure 4 for the SSTMelody-SHARC Memory Map). The SDRAM interface enables the SST-Melody-SHARC to transfer data to and from synchronous DRAM (SDRAM) at 2⫻ clock frequency. The synchronous approach coupled with 2⫻ clock frequency supports data transfer at a high throughput—up to 220 Mbytes/sec. The SDRAM interface provides a glueless interface with standard SDRAMs—16 Mbyte, 64 Mbyte, and 128 Mbyte—and includes options to support additional buffers between the SST-Melody-SHARC and SDRAM. The SDRAM interface is extremely flexible and provides capability for connecting SDRAMs to any one of the SST-Melody-SHARC’s four external memory banks. –13– SST-Melody-SHARC Systems with several SDRAM devices connected in parallel may require buffering to meet overall system timing requirements. The SST-Melody-SHARC supports pipelining of the address and control signals to enable such buffering between itself and multiple SDRAM devices. Host Processor Interface The SST-Melody-SHARC’s host interface provides easy connection to standard microprocessor buses—8-, 16-, and 32-bit—requiring little additional hardware. Supporting asynchronous transfers at speeds up to 1× clock frequency, the host interface is accessed through the SST-Melody-SHARC’s external port. Two channels of DMA are available for the host interface; code and data transfers are accomplished with low software overhead. The host processor requests the SST-Melody-SHARC’s external bus with the host bus request (HBR), host bus grant (HBG), and ready (REDY) signals. The host can directly read and write the IOP registers of the SST-Melody-SHARC and can access the DMA channel setup and mailbox registers. Vector interrupt support enables efficient execution of host commands. The SST-Melody-SHARC’s on-chip DMA controller allows zero-overhead, nonintrusive data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously executing its program instructions. Serial Ports The SST-Melody-SHARC features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices. The serial ports can operate at 1× clock frequency, providing each with a maximum data Programmable Timers and General-Purpose I/O Ports The SST-Melody-SHARC has two independent timer blocks, each of which performs two functions—Pulsewidth Generation and Pulse Count and Capture. In Pulse Counter mode, the SST-Melody-SHARC can measure either the high or low pulsewidth and the period of an input waveform. DMA transfers can occur between the SST-Melody-SHARC’s internal memory and either external memory, external peripherals, or a host processor. DMA transfers can also occur between the SST-Melody-SHARC’s internal memory and its serial ports. DMA transfers between external memory and external peripheral devices are another option. External bus packing to 16-, 32-, or 48bit internal words is performed during DMA transfers. Asynchronous off-chip peripherals can control two DMA channels using DMA Request/Grant lines (DMAR1–2, DMAG1–2). Other DMA features include interrupt generation on completion of DMA transfers and DMA chaining for automatically linked DMA transfers. The serial ports can operate with little-endian or big-endian transmission formats, with selectable word lengths of three bits to 32 bits. They offer selectable synchronization and transmit modes and optional µ-law or A-law companding. Serial port clocks and frame syncs can be internally or externally generated. The serial ports also include keyword and keymask features to enhance interprocessor communication. In Pulsewidth Generation mode, the SST-Melody-SHARC can generate a modulated waveform with an arbitrary pulsewidth within a maximum period of 71.5 secs. DMA Controller Ten channels of DMA are available on the SST-Melody-SHARC— eight via the serial ports, and two via the processor’s external port (for either host processor, other SST-Melody-SHARC, memory or I/O transfers). Programs can be downloaded to the SST-Melody-SHARC using DMA transfers. rate of 33 Mbit/s. Each serial port has a primary and a secondary set of transmit and receive channels. Independent transmit and receive functions provide greater flexibility for serial communications. Serial port data can be automatically transferred to and from on-chip memory via DMA. Each of the serial ports supports three operation modes: DSP serial port mode, I2S mode (an interface commonly used by audio codecs), and TDM (Time Division Multiplex) multichannel mode. The SST-Melody-SHARC also contains 12 programmable, general-purpose I/O pins that can function as either input or output. As output, these pins can signal peripheral devices; as input, these pins can provide the test for conditional branching. Program Booting The internal memory of the SST-Melody-SHARC can be booted at system power-up from an 8-bit EPROM, a host processor, or external memory. Selection of the boot source is controlled by the BMS (Boot Memory Select) and BSEL (EPROM Boot) pins. Either 8-, 16-, or 32-bit host processors can be used for booting. For details, see the descriptions of the BMS and BSEL pins in the Pin Function Descriptions section. Multiprocessing The SST-Melody-SHARC offers powerful features tailored to multiprocessing DSP systems. The unified address space allows direct interprocessor accesses of both SST-Melody-SHARC’s IOP registers. Distributed bus arbitration logic is included on-chip for simple, glueless connection of systems containing a maximum of two SST-Melody-SHARCs and a host processor. Master processor changeover incurs only one cycle of overhead. Bus lock allows indivisible read-modify-write sequences for semaphores. A vector interrupt is provided for interprocessor commands. Maximum throughput for interprocessor data transfer is 132 MBytes/s over the external port. –14– REV. 0 SST-Melody-SHARC POWER DISSIPATION These specifications apply to the internal power portion of VDD only. See the Power Dissipation section for calculation of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see the technical note SHARC Power Dissipation Measurements. Specifications are based on the following operating scenarios: Table II. Internal Current Measurements Operation Peak Activity (IDDINPEAK) High Activity (IDDINHIGH) Low Activity (IDDINLOW) Instruction Type Instruction Fetch Core Memory Access Internal Memory DMA Multifunction Cache 2 per Cycle (DM and PM) 1 per Cycle Multifunction Internal Memory 1 per Cycle (DM) 1 per 2 Cycles Single Function Internal Memory None 1 per 2 Cycles To estimate power consumption for a specific application, use the following equation where % is the amount of time your program spends in that state: %PEAK × I DDINPEAK + %HIGH × I DDINHIGH + %LOW × I DDINLOW + %IDLE16 × I DDIDLE16 = Power Consumption Table III. Internal Current Measurement Scenarios Parameter IDDINPEAK Supply Current (Internal)1 IDDINHIGH Supply Current (Internal)2 IDDINLOW Supply Current (Internal)3 IDDIDLE Supply Current (IDLE)4 IDDIDLE16 Supply Current (IDLE16)5 Test Conditions Max Unit tCK = 33 ns, VDD = max tCK = 30 ns, VDD = max tCK = 33 ns, VDD = max tCK = 30 ns, VDD = max tCK = 33 ns, VDD = max tCK = 30 ns, VDD = max tCK = 33 ns, VDD = max tCK = 30 ns, VDD = max VDD = max 470 510 275 300 240 260 150 155 50 mA mA mA mA mA mA mA mA mA NOTES 1 The test program used to measure I DDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal power measurements made using typical applications are less than specified. 2 IDDINHIGH is a composite average based on a range of high activity code. 3 IDDINLOW is a composite average based on a range of low activity code. 4 IDLE denotes SST-Melody-SHARC state during execution of IDLE instruction. 5 IDLE16 denotes SST-Melody-SHARC state during execution of IDLE16 instruction. REV. 0 –15– SST-Melody-SHARC OUTPUT DRIVE CURRENT REFERENCE SIGNAL SOURCE CURRENT – mA 80 60 3.6V, –40ⴗC 40 3.3V, +25ⴗC VOH 3.1V, +85ⴗC t MEASURED VOH (MEASURED) 20 3.1V, +100ⴗC OUTPUT 0 VOL (MEASURED) 3.1V, +100ⴗC –20 3.3V, +25ⴗC –40 3.6V, –40ⴗC VOH (MEASURED) – ⌬V 2.0V VOL (MEASURED) + ⌬V 1.0V 3.1V, +85ⴗC –80 –100 0.50 1.00 1.50 2.00 2.50 SOURCE VOLTAGE – V OUTPUT STARTS DRIVING 3.00 Figure 4. Output Enable 3.50 Figure 3. Typical Drive Currents IOL TEST CONDITIONS Output Disable Time TO OUTPUT PIN Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. The time for the voltage on the bus to decay by ∆V is dependent on the capacitive load, CL, and the load current, IL. This decay time can be approximated by the following equation: t DECAY VOL (MEASURED) HIGH IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE TO BE APPROXIMATELY 1.5V. VOL 0 VOH (MEASURED) t DECAY OUTPUT STOPS DRIVING –60 –120 t ENA t DIS 1.5V 50pF IOH Figure 5. Equivalent Device Loading for AC Measurements (Includes All Fixtures) C × ∆V = L IL The output disable time tDIS is the difference between tMEASURED and tDECAY as shown in Figure 5. The time tMEASURED is the interval from when the reference signal switches to when the output voltage decays ∆V from the measured output high or output low voltage. tDECAY is calculated with test loads CL and IL, and with ∆V equal to 0.5 V. Output Enable Time Output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driving. The output enable time tENA is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure 4. If multiple pins (such as the databus) are enabled, the measurement value is that of the first pin to start driving. INPUT OR OUTPUT 1.5V 1.5V Figure 6. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) Capacitive Loading Output delays and holds are based on standard capacitive loads: 50 pF on all pins. The delay and hold specifications given should be derated by a factor of l.8 ns/50 pF for loads other than the nominal value of 50 pF. Figure 7 and Figure 8 show how output rise time varies with capacitance. Figure 9 shows graphically how output delays and hold vary with load capacitance. (Note that this graph or derating does not apply to output disable delays; see the previous section Output Disable time under Test Conditions.) The graphs of Figures 7, 8, and 9 may not be linear outside the ranges shown. 18 Example System Hold Time Calculation 16 RISE AND FALL TIMES – ns To determine the data output hold time in a particular system, first calculate tDECAY using the previous equation. Choose ∆V to be the difference between the SST-Melody-SHARC’s output voltage and the input threshold for the device requiring the hold time. A typical ∆V will be 0.4 V. CL is the total bus capacitance (per data line), and IL is the total leakage or three-state current (per data line). The hold time will be tDECAY plus the minimum disable time (i.e., tDATRWH for the write cycle). 14 12 RISE TIME 10 8 FALL TIME 6 4 2 0 0 20 40 60 80 100 120 140 LOAD CAPACITANCE – pF 160 180 200 Figure 7. Typical Rise and Fall Time (10%–90% VDD) –16– REV. 0 SST-Melody-SHARC Power Dissipation 8.0 Total power dissipation has two components: one due to internal circuitry and one due to the switching of external output drivers. Internal power dissipation depends on the sequence in which instructions execute and the data operands involved. See IDDIN calculation in Electrical Characteristics section. Internal power dissipation is calculated this way: RISE AND FALL TIMES – ns 7.0 6.0 5.0 RISE TIME 4.0 3.0 PINT = IDDIN × VDD FALL TIME 2.0 1.0 0 0 20 40 60 80 100 120 140 LOAD CAPACITANCE – pF 160 180 200 Figure 8. Typical Rise and Fall Time (0.8 V–2.0 V) The external component of total power dissipation is caused by the switching of output pins. Its magnitude depends on: • Number of output pins that switch during each cycle (O) • Maximum frequency at which the pins can switch (f) • Load capacitance of the pins (C) • Voltage swing of the pins (VDD) The external component is calculated using: 6 2 PEXT = O × C × VDD × f OUTPUT DELAY OR HOLD – ns 5 The load capacitance should include the processor’s package capacitance (CIN). The frequency f includes driving the load high and then back low. Address and data pins can drive high and low at a maximum rate of 1/tCK while in SDRAM burst mode. 4 3 2 1 0 –1 –2 0 20 40 60 80 100 120 140 LOAD CAPACITANCE – pF 160 180 200 Example: Estimate PEXT with the following assumptions: • A system with one bank of external memory (32-bit) • Two 1 M ⫻ 16 SDRAM chips, each with a control signal load of 3 pF and a data signal load of 4 pF • External data writes occur in burst mode, two every 1/tCK cycles, a potential frequency of 1/tCK cycles/s. Assume 50% pin switching • The external SDRAM clock rate is 60 MHz (2/tCK) Figure 9. Typical Output Delay or Hold REV. 0 –17– SST-Melody-SHARC The PEXT equation is calculated for each class of pins that can drive: Table IV. External Power Calculations Pin Type No. of Pins % Switching ⴛC ⴛf (MHz) ⴛVDD2(V) = PEXT (W) Address MS0 SDWE Data SDRAM CLK 11 1 1 32 1 50 0 0 50 10.7 10.7 10.7 7.7 10.7 30 – – 30 30 10.9 10.9 10.9 10.9 10.9 0.019 0.000 0.000 0.042 0.007 PEXT = 0.068 W A typical power consumption can now be calculated for these conditions by adding a typical internal power dissipation (IDDIN, see calculation in Electrical Characteristics section): PTOTAL = PEXT + ( IDDIN × VDD ) Note that the conditions causing a worst-case PEXT differ from those causing a worst-case PINT. Maximum PINT cannot occur while 100% of the output pins are switching from all ones (1s) to all zeros (0s). Note also that it is not common for an application to have 100% or even 50% of the outputs switching simultaneously. TCASE = TAMB + ( PD × θ CA ) TCASE = Case temperature (measured on top surface of package) PD = Power Dissipation in W (this value depends upon the specific application; a method for calculating PD is shown under Power Dissipation) JC = 7.1°C/W for 208-lead MQFP JC = 5.1°C/W for 196-ball Mini-BGA Airflow Table V. Thermal Characteristics (208-Lead MQFP) ENVIRONMENTAL CONDITIONS Thermal Characteristics The SST-Melody-SHARC is offered in a 208-lead MQFP and a 196-ball Mini-BGA package. The SST-Melody-SHARC is specified for a case temperature (TCASE). To ensure that TCASE is not exceeded, an air flow source may be used. (Linear Ft/Min) 0 100 200 400 600 CA (°C/W) 24 20 19 17 13 Table VI. 196-Ball Mini-BGA –18– (Linear Ft/Min) 0 200 400 CA (°C/W) 38 29 23 REV. 0 SST-Melody-SHARC OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-196) Dimensions shown in millimeters A1 CORNER 15.00 BSC SQ 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P 1.00 BSC BALL PITCH 13.00 BSC SQ TOP VIEW BOTTOM VIEW 1.70 MAX DETAIL A 0.30 MIN 0.70 0.60 0.50 BALL DIAMETER 0.20 COPLANARITY SEATING PLANE DETAIL A COMPLIANT TO JEDEC STANDARDS MO-192AAE-1 208-Lead Plastic Quad Flatpack Package [MQFP] (S-208-2) Dimensions shown in millimeters 0.75 0.60 0.45 30.85 30.60 SQ 30.35 4.10 MAX 208 157 1 156 SEATING PLANE PIN 1 INDICATOR 28.20 28.00 SQ 27.80 TOP VIEW (PINS DOWN) VIEW A 3.60 3.40 3.20 0.50 0.25 53 0.50 BSC (LEAD PITCH) 0.08 (LEAD COPLANARITY) 0.27 0.17 (LEAD WIDTH) VIEW A ROTATED 90ⴗ CCW REV. 0 105 104 52 0.20 0.09 NOTES: 1. THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 FROM ITS IDEAL POSITION WHEN MEASURED IN THE LATERAL DIRECTION. 2. CENTER DIMENSIONS ARE NOMINAL. 3. DIMENSIONS ARE IN MILLIMETERS AND COMPLY WITH JEDEC STANDARD MS-029, FA-1. –19– –20– PRINTED IN U.S.A. C03052–0–10/02(0)