ST72521M/R/AR 8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE DATA BRIEFING ■ ■ ■ ■ ■ Memories – 32K to 60K dual voltage High Density Flash (HDFlash) or ROM with read-out protection capability. In-Application Programming and In-Circuit Programming for HDFlash devices – 1K to 2K RAM Cloc anced reset system – Enhanced low voltage supervisor (LVD) for main supply and auxiliary voltage detector (AVD) with interrupt capability – Clock sources: crystal/ceramic resonator oscillators, internal or external RC oscillator, clock security system and bypass for external clock – PLL for 2x frequency multiplication – Four power saving modes: Halt, Active-Halt, Wait and Slow Interrupt Management – Nested interrupt controller – 14 interrupt vectors plus TRAP and RESET – TLI dedicated top level interrupt pin – 15 external interrupt lines (on 4 vectors) Up to 64 I/O Ports – 48 multifunctional bidirectional I/O lines – 34 alternate function lines – 16 high sink outputs 5 Timers – Main Clock Controller with: Real time base, Beep and Clock-out capabilities – Configurable watchdog timer – Two 16-bit timers with: 2 input captures, 2 output compares, external clock input on one timer, PWM and pulse generator modes – 8-bit PWM Auto-Reload timer with: 2 input captures, 4 PWM outputs, output compare and time base interrupt, external clock with event detector TQFP64 14 x 14 TQFP64 10 x 10 TQFP80 14 x 14 ■ ■ 4 Communications Interfaces – SPI synchronous serial interface – SCI asynchronous serial interface (LIN compatible) – I2C multimaster interface – CAN interface (2.0B Passive) Analog peripheral – 10-bit ADC with 16 input pins ■ Instruction Set – 8-bit Data Manipulation – 63 Basic Instructions – 17 main Addressing Modes – 8 x 8 Unsigned Multiply Instruction – True Bit Manipulation ■ Development Tools – Full hardware/software development package – In-Circuit Testing capability Device Summary Features ST72(F)521(M/R/AR)9 ST72521(M/R/AR)7 ST72(F)521(R/AR)6 Program memory - bytes 60K 48K 32K RAM (stack) - bytes 2048 (256) 1536 (256) 1024 (256) Operating Voltage 3.8V to 5.5V Temp. Range (ROM) 0°C to 70°C / -10°C to +85 °C / -40°C to +85 °C / -40°C to +105°C / -40°C to +125°C Temp. Range (Flash) -40°C to +85 °C / -40°C to +125°C N/A -40°C to +125 °C Package TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR) TQFP64 14x14 (R), TQFP64 10x10 (AR) Rev. 1.5 April 2002 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/11 1 ST72521M/R/AR 1 INTRODUCTION The ST72521(A)R and ST72521M devices are members of the ST7 microcontroller family designed for mid-range applications with a CAN bus interface (Controller Area Network). All devices are based on a common industrystandard 8-bit core, featuring an enhanced instruction set and are available with FLASH or ROM program memory. Under software control, all devices can be placed in WAIT, SLOW, ACTIVE-HALT or HALT mode, reducing power consumption when the application is in idle or stand-by state. The enhanced instruction set and addressing modes of the ST7 offer both power and flexibility to software developers, enabling the design of highly efficient and compact application code. In addition to standard 8-bit data management, all ST7 microcontrollers feature true bit manipulation, 8x8 unsigned multiplication and indirect addressing modes. Figure 1. Device Block Diagram 8-BIT CORE ALU RESET VPP TLI VSS VDD CONTROL RAM (1024-2048 Bytes) LVD EVD AVD OSC1 OSC2 OSC PORT F TIMER A BEEP WATCHDOG ADDRESS AND DATA BUS MCC/RTC/BEEP PF7:0 (8-bits) PROGRAM MEMORY (32K - 60K Bytes) I2C PORT A PORT B PB7:0 (8-bits) PWM ART PORT C PORT E TIMER B PE7:0 (8-bits) PA7:0 (8-bits) PC7:0 (8-bits) CAN SPI SCI PORT D PORT G1 PG7:0 (8-bits) 10-BIT ADC PORT H1 PH7:0 (8-bits) PD7:0 (8-bits) VAREF VSSA 1 On 2/11 some devices only, see Device Summary on page 1 ST72521M/R/AR 2 PIN DESCRIPTION PA4 (HS) VPP / ICCSEL PA7 (HS) / SCLI PA6 (HS) / SDAI PA5 (HS) TLI EVD RESET PH4 PH7 PH6 PH5 OSC2 VSS_2 OSC1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PE3 / CANRX PE2 / CANTX PE1 / RDI PE0 / TDO VDD_2 Figure 2. 80-Pin TQFP 14x14 Package Pinout ei0 ei2 ei3 ei1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 VSS_1 VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK /ICCCLK PH3 PH2 PH1 PH0 PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA PC3 (HS) /ICAP1_B PC2(HS) / ICAP2_B PC1 / OCMP1_B / AIN13 PC0 / OCMP2_B /AIN12 VSS_0 VDD_0 MCO /AIN8 / PF0 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 /PF3 OCMP1_A/AIN10 /PF4 ICAP2_A/ AIN11 /PF5 ICAP1_A / (HS) / PF6 EXTCLK_A / (HS) PF7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PE4 PE5 PE6 PE7 PB0 PB1 PB2 PB3 PG0 PG1 PG2 PG3 ARTCLK / (HS) PB4 ARTIC1 / PB5 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 PG6 PG7 AIN4/PD4 AIN5 / PD5 AIN6 / PD6 AIN7 / PD7 VAREF VSSA VDD3 VSS3 PG4 PG5 (HS) (HS) (HS) (HS) PWM3 / PWM2 / PWM1 / PWM0 / (HS) 20mA high sink capability eix associated external interrupt vector 3/11 ST72521M/R/AR PIN DESCRIPTION (Cont’d) PA4 (HS) PA5 (HS) VPP / ICCSEL EVD RESET TLI OSC2 VSS_2 OSC1 PE0 / TDO VDD_2 PA7 (HS) / SCLI PA6 (HS) / SDAI VDD_1 PA3 (HS) PA2 PA1 PA0 PC7 / SS / AIN15 PC6 / SCK / ICCCLK PC3 PC2 PC1 PC0 (HS) / ICAP1_B (HS) / ICAP2_B / OCMP1_B / AIN13 / OCMP2_B / AIN12 VSS_0 VDD_0 ICAP1_A / (HS) PF6 EXTCLK_A / (HS) PF7 ICAP2_A / AIN11 / PF5 OCMP1_A / AIN10 / PF4 AIN4 / PD4 AIN5 / PD5 AIN3 / PD3 BEEP / (HS) PF1 (HS) PF2 OCMP2_A / AIN9 / PF3 AIN2 / PD2 PC5 / MOSI / AIN14 PC4 / MISO / ICCDATA MCO / AIN8 / PF0 ARTIC2 / PB6 PB7 AIN0 / PD0 AIN1 / PD1 40 39 ei3 38 37 36 13 35 14 ei1 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 9 10 11 12 VSSA ARTCLK /(HS) PB4 ARTIC1 / PB5 VDD_3 VSS_3 PWM3 / PB0 PWM2 / PB1 PWM1 / PB2 PWM0 /PB3 VSS_1 AIN7 / PD7 VAREF (HS) PE6 (HS) PE7 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 ei0 44 5 43 6 ei2 42 7 41 8 1 2 3 4 AIN6 / PD6 (HS) PE4 (HS) PE5 PE1 / RDI PE3 / CANRX PE2 / CANTX Figure 3. 64-Pin TQFP 14x14 and 10x10 Package Pinout (HS) 20mA high sink capability eix associated external interrupt vector 4/11 ST72521M/R/AR PIN DESCRIPTION (Cont’d) Legend / Abbreviations for Table 1: Type: I = input, O = output, S = supply Input level: A = Dedicated analog input In/Output level: C = CMOS 0.3VDD/0.7VDD CT= CMOS 0.3VDD/0.7VDD with input trigger TT= TTL 0.8V / 2V with Schmitt trigger Output level: HS = 20mA high sink (on N-buffer only) Port and control configuration: – Input: float = floating, wpu = weak pull-up, int = interrupt 1), ana = analog – Output: OD = open drain 2), PP = push-pull The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is in reset state. Table 1. Device Pin Description Level Input Output float wpu OD PP Main Output function (after reset) TQFP64 Port TQFP80 Type Pin n° 1 1 PE4 (HS) I/O CT HS X X X X Port E4 2 2 PE5 (HS) I/O CT HS X X X X Port E5 3 3 PE6 (HS) I/O CT HS X X X X Port E6 4 4 PE7 (HS) I/O CT HS X X X X Port E7 5 5 PB0/PWM3 I/O CT X ei2 X X Port B0 PWM Output 3 6 6 PB1/PWM2 I/O CT X ei2 X X Port B1 PWM Output 2 7 7 PB2/PWM1 I/O CT X ei2 8 8 PB3/PWM0 I/O CT X ana int Pin Name Input ei2 X X Port B2 PWM Output 1 X X Port B3 PWM Output 0 9 - PG0 I/O TT X X X X Port G0 10 - PG1 X X X X Port G1 11 - PG2 I/O TT I/O TT X X X X Port G2 12 - PG3 I/O TT X X 13 9 PB4 (HS)/ARTCLK I/O CT HS Alternate function X X Port G3 X ei3 X X Port B4 PWM-ART External Clock 14 10 PB5/ARTIC1 I/O CT X ei3 X X Port B5 PWM-ART Input Capture 1 15 11 PB6/ARTIC2 I/O CT X ei3 X X Port B6 PWM-ART Input Capture 2 16 12 PB7 I/O CT X X X Port B7 17 13 PD0 /AIN0 I/O CT X X X X X Port D0 ADC Analog Input 0 18 14 PD1/AIN1 I/O CT X X X X X Port D1 ADC Analog Input 1 19 15 PD2/AIN2 I/O CT X X X X X Port D2 ADC Analog Input 2 20 16 PD3/AIN3 I/O CT X X X X X Port D3 ADC Analog Input 3 21 - PG6 I/O TT X X X X Port G6 22 - PG7 X X X X Port G7 23 17 PD4/AIN4 I/O TT I/O CT X X X X X Port D4 ADC Analog Input 4 24 18 PD5/AIN5 I/O CT X X X X X Port D5 ADC Analog Input 5 25 19 PD6/AIN6 I/O CT X X X X X Port D6 ADC Analog Input 6 26 20 PD7/AIN7 I/O CT X X X X X Port D7 ADC Analog Input 7 ei3 5/11 ST72521M/R/AR Pin n° Main function Output (after reset) VAREF I Analog Reference Voltage for ADC 28 22 VSSA S Analog Ground Voltage 29 23 VDD_3 S Digital Main Supply Voltage 30 24 VSS_3 31 - PG4 32 - 33 Alternate function PP ana int wpu float Input OD 21 Output 27 Pin Name Input TQFP64 Port TQFP80 Type Level S Digital Ground Voltage X X X X Port G4 PG5 I/O TT I/O TT X X X X Port G5 25 PF0/MCO/AIN8 I/O CT X ei1 X X Port F0 Main clock out (fOSC/2) 34 26 PF1 (HS)/BEEP I/O CT HS X ei1 X X Port F1 Beep signal output 35 27 PF2 (HS) I/O CT HS X X X Port F2 36 28 PF3/OCMP2_A/AIN9 I/O CT X X X X Port F3 Timer A OutADC Analog put Compare Input 9 2 37 29 PF4/OCMP1_A/AIN10 I/O CT X X X X Port F4 Timer A OutADC Analog put Compare Input 10 1 38 30 PF5/ICAP2_A/AIN11 I/O CT X X X X Port F5 Timer A Input ADC Analog Capture 2 Input 11 39 31 PF6 (HS)/ICAP1_A I/O CT X X X X Port F6 Timer A Input Capture 1 Port F7 Timer A External Clock Source I/O CT HS HS X ei1 X X X ADC Analog Input 8 40 32 PF7 (HS)/EXTCLK_A 41 33 VDD_0 S Digital Main Supply Voltage 42 34 VSS_0 S Digital Ground Voltage 43 35 PC0/OCMP2_B/AIN12 I/O CT X X X X Port C0 Timer B OutADC Analog put Compare Input 12 2 44 36 PC1/OCMP1_B/AIN13 I/O CT X X X X Port C1 Timer B OutADC Analog put Compare Input 13 1 45 37 PC2 (HS)/ICAP2_B I/O CT HS X X X X Port C2 Timer B Input Capture 2 46 38 PC3 (HS)/ICAP1_B I/O CT HS X X X X Port C3 Timer B Input Capture 1 47 39 PC4/MISO/ICCDATA I/O CT X X X X Port C4 SPI Master In ICC Data In/ Slave Out put Data 48 40 PC5/MOSI/AIN14 I/O CT X X X X Port C5 SPI Master ADC Analog Out / Slave In Input 14 Data 49 - PH0 I/O TT X X X X Port H0 50 - PH1 X X X X Port H1 51 - PH2 I/O TT I/O TT X X X X Port H2 52 - PH3 I/O TT X X X X Port H3 53 41 PC6/SCK/ICCCLK I/O CT X X X X Port C6 6/11 SPI Serial Clock ICC Clock Output ST72521M/R/AR Level wpu 42 PC7/SS/AIN15 I/O CT X X 55 43 PA0 I/O CT X 56 44 PA1 I/O CT 57 45 PA2 I/O CT 58 46 PA3 (HS) I/O CT 59 47 VDD_1 S Digital Main Supply Voltage 60 48 VSS_1 S Digital Ground Voltage PP ana OD HS Input X X Port C7 ei0 X X Port A0 X ei0 X X Port A1 X ei0 X X Port A2 X X Port A3 X int Output 54 Pin Name Input float Main function Output (after reset) TQFP64 Port TQFP80 Type Pin n° ei0 Alternate function SPI Slave ADC Analog Select (active Input 15 low) 61 49 PA4 (HS) I/O CT HS X X X X Port A4 62 50 PA5 (HS) I/O CT HS X X X X Port A5 63 51 PA6 (HS)/SDAI I/O CT HS X T Port A6 I2C Data 1) 64 52 PA7 (HS)/SCLI I/O CT HS X T Port A7 I2C Clock 1) 65 53 VPP/ ICCSEL 66 54 RESET 67 55 EVD 68 56 TLI 69 - PH4 70 - PH5 71 - PH6 PH7 Must be tied low. In flash programming mode, this pin acts as the programming voltage input VPP. High voltage must not be applied to ROM devices I Top priority non maskable interrupt. I/O CT External voltage detector CT X I/O TT I/O TT X X X X Port H4 X X X X Port H5 I/O TT I/O TT X X X X Port H6 X X X X Port H7 I X Top level interrupt input pin 72 - 73 57 VSS_2 74 58 OSC23) I/O 75 59 OSC13) I External clock input or Resonator oscillator inverter input or resistor input for RC oscillator 76 60 VDD_2 S Digital Main Supply Voltage S Digital Ground Voltage Resonator oscillator inverter output or capacitor input for RC oscillator 77 61 PE0/TDO I/O CT X X X X Port E0 SCI Transmit Data Out 78 62 PE1/RDI I/O CT X X X X Port E1 SCI Receive Data In 79 63 PE2/CANTX I/O CT Port E2 CAN Transmit Data Output 80 64 PE3/CANRX I/O CT X X X X Port E3 CAN Receive Data Input X Notes: 1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD 7/11 ST72521M/R/AR are not implemented). 3. OSC1 and OSC2 pins connect a crystal/ceramic resonator, an RC oscillator, or an external source to the on-chip oscillator; 4. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up configuration after reset. The configuration of these pads must be kept at reset state to avoid added current consumption. 8/11 ST72521M/R/AR 3 PACKAGE CHARACTERISTICS 3.1 PACKAGE MECHANICAL DATA Figure 4. 80-Pin Thin Quad Flat Package Dim. D A D1 A2 b e E c L1 L Typ A A1 E1 mm Min Min Typ Max 1.60 0.063 0.15 0.002 0.006 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.22 0.32 0.38 0.009 0.013 0.015 C 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 E 16.00 0.630 E1 14.00 0.551 e 0.65 θ 0° 3.5° L 0.45 0.60 L1 h inches Max 0.026 7° 0° 3.5° 7° 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins N 80 Figure 5. 64-Pin Thin Quad Flat Package D A D1 A2 Dim. mm Min Typ A A1 b e E1 E L Min Typ Max 1.60 0.063 0.15 0.002 0.006 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 D 16.00 0.630 D1 14.00 0.551 E 16.00 0.630 E1 14.00 0.551 e 0.80 θ 0° 3.5° L 0.45 0.60 L1 L1 0.031 7° 0° 3.5° 7° 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins c h inches Max N 64 9/11 ST72521M/R/AR PACKAGE MECHANICAL DATA (Cont’d) Figure 6. 64-Pin Thin Quad Flat Package Dim. D A D1 A2 Typ A A1 b E1 mm Min E e c L1 h L inches Max Min Typ Max 1.60 0.063 0.15 0.002 0.006 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 E 12.00 0.472 E1 10.00 0.394 e 0.50 θ 0° 3.5° L 0.45 0.60 L1 0.020 7° 0° 3.5° 7° 0.75 0.018 0.024 0.030 1.00 0.039 Number of Pins N 64 Figure 7. 42-Pin Plastic Dual In-Line Package, Shrink 600-mil Width Dim. E mm Min Typ A A2 A1 b2 b D e A L c E1 eA eB E 0.015 GAGE PLANE eC inches Max Min Typ 5.08 Max 0.200 A1 0.51 A2 3.05 3.81 4.57 0.120 0.150 0.180 0.020 b 0.38 0.46 0.56 0.015 0.018 0.022 b2 0.89 1.02 1.14 0.035 0.040 0.045 c 0.23 0.25 0.38 0.009 0.010 0.015 D 36.58 36.83 37.08 1.440 1.450 1.460 E 15.24 E1 12.70 13.72 14.48 0.500 0.540 0.570 16.00 0.600 0.630 e 1.78 0.070 eA 15.24 0.600 eB 18.54 0.730 eC 1.52 0.000 0.060 eB L 2.54 3.30 3.56 0.100 0.130 0.140 Number of Pins N 10/11 42 ST72521M/R/AR Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in lif e support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2 C Patent. Rights to use these components in an I2 C system is granted provided that the system conforms to the I2 C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http:/ /www.st.com 11/11