STMICROELECTRONICS STR736FV1T7

STR73xF
ARM7TDMI™ 32-BIT MCU WITH FLASH, 3x CAN,
4 UARTs, 20 TIMERS, ADC, 12 COMM. INTERFACES
DATA BRIEF
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■
■
■
■
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Core
– ARM7TDMI 32-bit RISC CPU
– 32 MIPS @ 36 MHz
Temperature Range
– Operating temperature range -40 to 105 °C
Memories
– Up to 256 Kbytes FLASH program memory
(10,000 cycles endurance, data retention 20
years at 55°C)
– 16 Kbytes RAM
Clock, Reset and Supply Management
– 4.5 - 5.5V application supply and I/O interface
– Embedded 1.8V regulator for core supply
– Embedded oscillator running from external
4-8MHz crystal or ceramic resonator
– Up to 36 MHz CPU freq. with internal PLL
– Internal RC oscillator 32kHz or 2MHz software configurable for fast startup and backup
clock
– Realtime Clock for clock-calendar function
– Wakeup Timer driven by internal RC for wakeup from STOP mode
– 5 power saving modes: SLOW, WAIT,
LPWAIT, STOP and HALT modes
Nested interrupt controller
– Fast interrupt handling with multiple vectors
– 64 maskable IRQ with 64 vectors and
16 priority levels
– 2 maskable FIQ sources
– 16 external interrupts and up to 32 wake up
lines
Up to 112 I/O ports
– 72/112 multifunctional bidirectional I/O lines
TQFP100 14 x 14
TQFP144
20 x 20
LFBGA144 10 x 10 x 1.7
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■
■
■
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DMA
– 4 DMA controllers with 4 channels each
Timers
– 16-bit watchdog timer (WDG)
– 6/10 16-bit timers (TIM) each with: 2 input
captures, 2 output compares, PWM and pulse
counter modes
– 6 16-bit PWM modules (PWM)
– 3 16-bit timebase timers with 8-bit prescalers
12 Communications Interfaces
– 2 I2C interfaces
– 4 UART asynchronous serial communications
interfaces
– 3 BSPI synchronous serial interfaces
– Up to 3 CAN interfaces (2.0B Active)
10-bit A/D Converter
– 12/16 channels
– Conversion time: min 3µs, range: 0 to 5V
Development Tools Support
– JTAG interface
Table 1. Device Summary
Features
FLASH memory - bytes
STR730FZx
128K
256K
RAM - bytes
Peripheral Functions
CAN Peripherals
Operating Voltage
STR735FZx
128K
256K
STR731FVx
128K
256K
64K
STR736FVx
128K
256K
16K
16K
10 TIM Timers, 112 I/Os, 32
Wake-Up lines, 16 ADC channels
6 TIM Timers, 72 I/Os, 18 Wake-Up lines,
12 ADC channels
3
0
3
0
4.5 to 5.5V (optional 1.8V for core)
Operating Temperature
Packages
64K
-40 to +105°C
T=TQFP144 20 x 20
H=LFBGA144 10 x10
T=TQFP100 14x14
Rev. 1
July 2005
This is preliminary information on a new product now in development. Details are subject to change without notice.
1/22
1
STR73xF Data Brief
1 INTRODUCTION
This Data Brief provides the STR73xF feature summary, pin description and ordering
Information.
For complete information on the Mechanical and Electrical Device Characteristics please refer
to the Preliminary Datasheet.
For complete information on the STR73xF Microcontroller memory, registers and peripherals.
please refer to the STR73x Reference Manual.
For information on programming, erasing and protection of the internal Flash memory please
refer to the STR7 Flash Programming Reference Manual
For information on the ARM7TDMI core please refer to the ARM7TDMI Technical Reference
Manual.
1.1 Overview
ARM‚ core with embedded Flash & RAM
STR73xF family combines the high performance ARM7TDMI™ CPU with an extensive range
of peripheral functions and enhanced I/O capabilities. All devices have on-chip high-speed
single voltage FLASH memory and high-speed RAM. The STR73xF family has an embedded
ARM core and is therefore compatible with all ARM tools and software.
Extensive tools support
STMicroelectronics’ 32-bit, ARM core-based microcontrollers are supported by a complete
range of high-end and low-cost development tools to meet the needs of application
developers. This extensive line of hardware/software tools includes starter kits and complete
development packages all tailored for ST’s ARM core-based MCUs. The range of
development packages includes third-party solutions that come complete with a graphical
development environment and an in-circuit emulator/programmer featuring a JTAG application
interface. These support a range of embedded operating systems (OS), while several
royalty-free OSs are also available.
For more information, please refer to ST MCU site http://www.st.com/mcu
Figure 1 shows the general block diagram of the device family.
Package Choice: Reduced Pin-Count TQFP100 or Feature-Rich 144-pin TQFP or
LFBGA
The STR73xF family is available in 3 packages. The TQFP144 and LFBGA144 versions have
the full set of all features. The 100-pin version has fewer timers, I/Os and ADC channels. Refer
to the Device Summary on Page 1 for a comparison of the I/Os available on each package.
The family includes versions with and without CAN.
2/22
1
STR73xF Data Brief
High Speed Flash Memory
The Flash program memory is organized in 32-bit wide memory cells which can be used for
storing both code and data constants. It is accessed by CPU with zero wait states @ 36 MHz.
The STR7 embedded Flash memory can be programmed using In-Circuit Programming or
In-Application programming.
The Flash memory endurance is 10K write/erase cycles and the data retention is 20 years at
55°C.
IAP (In-Application Programming): The IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
ICP (In-Circuit Programming): The ICP is the ability to program the Flash memory of a microcontroller using JTAG protocol while the device is mounted on the user application board.
The Flash memory can be protected against different types of unwanted access (read/write/
erase). There are two types of protection:
•
Sector Write Protection
•
Flash Debug Protection (locks JTAG access)
Flexible Power Management
To minimize power consumption, you can program the STR73xF to switch to SLOW, WAIT
LPWAIT, STOP or HALT modes depending on the current system activity in the application.
Flexible Clock Control
Two clock sources are used to drive the microcontroller, a main clock driven by an external
crystal or ceramic resonator and an internal backup RC oscillator that operates at 2MHz or 32
kHz. The embedded PLL allows the internal system clock (up to 36 MHz) to be generated
from a main clock frequency of 10 MHz or less. The PLL output frequency can be
programmed using a wide selection of multipliers and dividers.
Voltage Regulators
The STR73xF requires an external 4.5 to 5.5V power supply. There are two internal Voltage
Regulators for generating the 1.8V power supply needed by the core and peripherals. The
main VR is switched off and the Low Power VR switched on when the application puts the
STR73xF in Low Power Wait (LPWAIT) mode.
3/22
STR73xF Data Brief
Low Voltage Detectors
The voltage regulator and Flash modules each have an embedded LVD that monitors the
internal 1.8V supply. If the voltage drops below a certain threshold, the LVD will reset the
STR73xF.
Note: An external power-on reset must be provided ensure the microcontroller starts-up
correctly.
On-Chip Peripherals
CAN Interfaces
The three CAN modules are compliant with the CAN specification V2.0 part B (active). The bit
rate can be programmed up to 1 MBaud. These are not available in the STR735 and STR736.
DMA
4 DMA controllers, each with 4 data streams manage memory to memory, peripheral to
memory and memory to peripheral transfers. The DMA requests are connected to TIM timers,
BSPI0, BSPI1, BSPI2 and ADC. One of the streams can be configured to be triggered by a
software request, independently from any peripheral activity.
16-bit Timers (TIM)
Each of the ten timers (six in 100-pin devices) have a 16-bit free-running counter with 7-bit
prescaler, up to two input capture/output compare functions, a pulse counter function, and a
PWM channel with selectable frequency. This provides a total of 16 independent PWMs (12 in
100-pin devices) when added with the PWM modules (see next paragraph).
PWM Modules (PWM)
The six 16-bit PWM modules have independently programmable periods and duty-cycles,
with 5+3 bit prescaler factor.
Timebase Timers (TB)
The three 16-bit Timebase Timers with 8-bit prescaler for general purpose time triggering
operations.
Realtime Clock (RTC)
The RTC provides a set of continuously running counters driven by separate clock signal
derived from the main oscillator. The RTC can be used as a general timebase or clock/
calendar/alarm function. When the STR73xF is in LPWFI mode the RTC keeps running,
powered by the low power voltage regulator.
UARTs
The 4 UARTs allow full duplex, asynchronous, communications with external devices with
independently programmable TX and RX baud rates up to 625K baud.
4/22
STR73xF Data Brief
Buffered Serial Peripheral Interfaces (BSPI)
Each of the three BSPIs allow full duplex, synchronous communications with external devices,
master or slave communication at up 6 Mb/s (@36 MHz System Clock).
I2C Interfaces
The two I2C Interfaces provide multi-master and slave functions, support normal and fast I2C
mode (400 kHz) and 7 or 10-bit addressing modes.
A/D Converter
The 10-bit Analog to Digital Converter, converts up to 16 channels in single-shot or
continuous conversion modes (12 channels in 100-pin devices). The minimum conversion
time is 3us.
Watchdog
The 16-bit Watchdog Timer protects the application against hardware or software failures and
ensures recovery by generating a reset.
I/O Ports
Up to 112 I/O ports (72 in 100-pin devices) are programmable as general purpose input/
output or Alternate Function.
External Interrupts and Wake-Up Lines
16 external interrupts lines are available for application use. In addition, up to 32 external
Wakeup lines (18 in 100-pin devices) can be used as general purpose interrupts or to
wake-up the application from STOP mode.
5/22
STR73xF Data Brief
Figure 1. STR730F/STR735F Block Diagram
RSTIN
PRCCU/PLL
FLASH
Program Memory
64/128/256K
ARM7TDMI
CPU
JTAG
V18
VDD
VSS
VDDA
VSSA
RAM
16K
ARM7 NATIVE BUS
JTDI
JTCK
JTMS
JTRST
JTDO
M0
M1
TEST
APB
BRIDGE 0
POWER SUPPLY
VREG
APB
BRIDGE 1
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
I2C0-1
4 AF
INTERRUPT CTL (EIC)
WAKEUP/INT (WIU)
32 AF
16 AF
A/D CONVERTER (ADC)
UART0, 1, 2, 3
8 AF
12 AF
TIMER (TIM) 2-4
12 AF
BSPI 0-2
WAKEUP TIMER
(WUT)
6 AF
CAN 0-2*
TIMER (TIM) 0-1
8 AF
6 AF
PWM 0-5
TIMER (TIM) 5-9
20 AF
122 ports
TIMEBASE TIMER
(TB) 0-2
GPIO PORTS 0-6
*CAN peripherals not available on STR735F.
6/22
APB BUS
RTC
APB BUS
OSC
AF: alternate function on I/O port pin
STR73xF Data Brief
Figure 2. STR731F/STR736 Device Block Diagram
RSTIN
PRCCU/PLL
FLASH
Program Memory
64/128/256K
ARM7TDMI
CPU
JTAG
V18
VDD
VSS
VDDA
VSSA
RAM
16K
ARM7 NATIVE BUS
JTDI
JTCK
JTMS
JTRST
JTDO
M0
M1
TEST
APB
BRIDGE 0
POWER SUPPLY
VREG
APB
BRIDGE 1
AHB
BRIDGE
AHB BUS
DMA0-3
WATCHDOG
CLOCK MGT (CMU)
XTAL1
XTAL2
I2C0-1
4 AF
INTERRUPT CTL (EIC)
WAKEUP/INT (WIU)
18 AF
12 AF
A/D CONVERTER (ADC)
UART0, 1, 2, 3
8 AF
12 AF
TIMER (TIM) 2-4
12 AF
BSPI 0-2
WAKEUP TIMER
(WUT)
6 AF
CAN 0-2*
TIMER (TIM) 0-1
8 AF
6 AF
PWM 0-5
TIMER (TIM) 5
4 AF
72 ports
APB BUS
RTC
APB BUS
OSC
TIMEBASE TIMER
(TB) 0-2
GPIO PORTS 0-6
*CAN peripherals not available on STR736F.
AF: alternate function on I/O port pin
7/22
STR73xF Data Brief
1.2 Related Documentation
Available from www.arm.com:
ARM7TDMI Technical Reference Manual
Available from http://www.st.com:
STR7 Flash Programming Reference Manual
STR73x Software Library User Manual
For a list of related application notes refer to http://www.st.com.
8/22
STR73xF Data Brief
1.3 Pin Description
1.3.1
STR730F/STR735F (TQFP144)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
STR730F/STR735F
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P4.14 / SS1
P4.13 / ICAPB9
P4.12 / ICAPA9 / WUP21
P4.11 / OCMPB8
P4.10 / ICAPA6 / WUP20
P4.9 / ICAPB6
P4.8 / OCMPA8
P4.7 / SDA1
P4.6 / SCL1 / WUP19
P4.5 / CAN2RX / WUP18
P4.4 / CAN2TX
P4.3 / ICAPB8 / WUP27
P4.2 / ICAPA8 / WUP26
P4.1 / ICAPB7 / WUP25
P4.0 / ICAPA7 / WUP24
VDD
VSS
JTDO
JTCK
JTMS
JTDI
JTRST
VSS
VDD
P3.15 / AIN15 / INT5
P3.14 / AIN14 / INT4
P3.13 / AIN13 / INT3
P3.12 / AIN12 / INT2
P3.11 / AIN11
P3.10 / AIN10
P3.9 / AIN9
P3.8 / AIN8
VDDA
VSSA
P3.7 / AIN7
P3.6 / AIN6
WUP12 / CAN0RX / P1.14
CAN0TX / P1.15
PWM0 / P2.0
WUP13 / CAN1RX / P2.1
CAN1TX / P2.2
PWM1 / P2.3
PWM2 / P2.4
PWM3 / P2.5
PWM4 / P2.6
PWM5 / P2.7
M0
RSTIN
M1
VDD
VSS
XTAL1
XTAL2
VSS
TDO1 / P2.8
WUP14 / RDI1 / P2.9
WUP16 / P2.10
WUP17 / P2.11
INT14 / P2.12
INT15 / P2.13
WUP15 / SCL0 / P2.14
SDA0 / P2.15
TEST
VBIAS
VSS
VDD
AIN0 / P3.0
AIN1 / P3.1
AIN2 / P3.2
AIN3 / P3.3
AIN4 / P3.4
AIN5 / P3.5
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
VSS
VDD
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
ICAPB5 / P0.7
OCMPA6 / P0.8
OCMPB6 / P0.9
OCMPA7 / P0.10
OCMPB7 / P0.11
VDD
VSS
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
VSS
VDD
P1.4
P1.5
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
P6.15 / WUP9
P6.14 / SS0
P6.13 / SCK0 / WUP11
P6.12 / MOSI0
P6.11 / MISO0
P6.10 / WUP8
P6.9 / TDO0
P6.8 / RDI0 / WUP10
P6.7 / WUP7
P6.6 / WUP6
P6.5 / WUP5
P6.4 / TDO3 / WUP4
P6.3 / WUP3
P6.2 / RDI3 / WUP2
P6.1 / WUP1
P6.0 / WUP0
VDD
VSS
V18
P5.15 / INT13
P5.14 / INT12
P5.13 / INT11
P5.12 / INT10
P5.11 / TDO2 / INT9
P5.10 / RDI2 / INT8
P5.9 / INT7
P5.8 / INT6
P5.7 / MISO2
P5.6 / MOSI2
P5.5 / SCK2 / WUP23
P5.4 / SS2
P5.3 / OCMPB9
P5.2 / OCMPA9
P5.1 / MISO1
P5.0 / MOSI1
P4.15 / SCK1 / WUP22
Figure 3. STR730F/STR735F Pin Configuration (top view)
Note 1: CAN alternate functions not available on STR735F.
9/22
STR73xF Data Brief
1.3.2
STR730F/STR735F (LFBGA144)
Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
Name
Ball
Name
Ball
Name
Ball
Name
A1
P0.0 / OCMPB2
B1
P0.4 / OCMPA5
C1
P0.5 / OCMPB5
D1
VSS
A2
P6.10 / WUP8
B2
P0.1 / OCMPA2
C2
P0.2 / ICAPA2
D2
VDD
A3
P6.9 / TDO0
B3
P6.15 / WUP9
C3
P0.3 / ICAPB2
D3
P0.6 / ICAPA5
A4
P6.12 / MOSI0
B4
P6.13 / SCKO / WUP11
C4
P6.14 / SSO
D4
P0.7 /ICAPB5
A5
P6.6 / WUP6
B5
P6.7 / WUP7
C5
P6.8 / RDI0 / WUP10
D5
P6.11 / MISO0
A6
V18
B6
P6.2 / WUP2 / RDI3
C6
P6.3 / WUP3
D6
P6.4 / WUP4 /TDO3
A7
P5.15 / INT13
B7
P5.14 / INT12
C7
VSS
D7
VDD
A8
P5.8 / INT6
B8
P5.9 / INT7
C8
P5.10 / INT8 / RDI2
D8
P5.12 / INT10
A9
P5.2 / OCMPA9
B9
P5.3 / OCMPB9
C9
P5.4 / SS2
D9
P5.5 / SCK2 / WUP23
A10
P5.7 / MISO2
B10
P5.0 / MOSI1
C10
P5.1 / MISO1
D10
P4.13 / ICAPB9
A11
P5.6 / MOSI2
B11
P4.15 / SCK1 / WUP22
C11
P4.14 / SS1
D11
P4.12 / ICAPA9 / WUP21
A12
P5.11 / TDO2 / INT9
B12
P4.8 / OCMPA8
C12
P4.7 / SDA1
D12
P4.11 / OCMPB8
E1
P0.8 / OCMPA6
F1
VDD
G1
VSS
H1
VDD
E2
P0.9 / OCMPB6
F2
P0.13 / ICAPB3
G2
P1.2 / ICAPB4
H2
P1.8 / OCMPA0 / INT0
E3
P0.10 / OCMPA7
F3
P0.14 / OCMPB3
G3
P1.3 / ICAPA4
H3
P1.9 / OCMPB0 / INT1
E4
P0.11 / OCMPB7
F4
P0.15 / OCMPA3
G4
VSS
H4
P1.10 / ICAPB0 / WUP28
E5
P0.12 / ICAPA3
F5
P1.0 / OCMPA4
G5
P1.5
H5
XTAL2
E6
P6.5 / WUP5
F6
P1.1 / OCMPB4
G6
P2.11 / WUP17
H6
P2.10 / WUP16
E7
P6.0 / WUP0
F7
P6.1 / WUP1
G7
P4.0 / ICAPA7 / WUP24
H7
P2.15 / SDA 0
E8
P5.13 / INT11
F8
P4.4 / CAN2TX1)
G8
VDD
H8
JTMS
E9
P4.10 / ICAPA6 / WUP20
F9
P4.3 / ICAPB8 / WUP27
G9
VSS
H9
VSS
10/22
STR73xF Data Brief
Table 2. STR730F/STR735F LFBGA Ball Connections
Ball
Name
Ball
Name
Ball
Name
Ball
Name
E10
P4.9 / ICAPB6
F10
P4.2 / ICAPA8 / WUP26
G10
JTDO
H10
VDD
E11
P4.6 / SCL1 / WUP19
F11
P4.1 / ICAPB7 / WUP25
G11
JTCK
H11
P3.15 / AIN15 / INT5
E12
P4.5 / WUP18 /
CAN2RX 1)
F12
JTDI
G12
nJTRST
H12
P3.14 / AIN14 / INT4
J1
P1.4
K1
P1.6 / OCMPB1
L1
P1.7 / OCMPA1
M1
P1.14 / CAN0RX 1) /
WUP12
J2
P1.11 / ICAPA0 / WUP29
K2
P1.13 / ICAPB1 / WUP31
L2
P1.15 / CAN0TX1)
M2
P2.4 / PWM2
L3
P2.0 / PWM0
M3
P2.5 / PWM3
P2.6 / PWM4
L4
P2.3 / PWM1
M4
P2.2 / CAN1TX1)
CAN1RX1)
P2.1 /
WUP13
/
J3
P1.12 / ICAPA1 / WUP30
K3
J4
P2.7 / PWM5
K4
J5
VDD
K5
M1
L5
RSTIN
M5
M0
J6
P2.9 / RDI1 / WUP14
K6
P2.8 / TDO1
L6
VSS
M6
VSS
J7
P2.14 / SCL 0 / WUP15
K7
P2.13 / INT15
L7
P2.12 / INT14
M7
XTAL1
J8
P3.1 / AIN1
K8
P3.0 / AIN0
L8
VBIAS
M8
TST
J9
P3.13 / AIN13 / INT3
K9
P3.4 / AIN4
L9
P3.3 / AIN3
M9
P3.2 / AIN2
J10
P3.12 / AIN12 / INT2
K10
VDDA
L10
P3.5 / AIN5
M10
VSS
J11
P3.9 / AIN9
K11
VSSA
L11
P3.7 / AIN7
M11
VDD
J12
P3.8 / AIN8
K12
P3.11 / AIN11
L12
P3.10 / AIN10
M12
P3.6 / AIN6
Note 1: CAN alternate functions not available on STR735F.
11/22
STR73xF Data Brief
1.3.3
STR731F/STR736F (TQFP100)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
STR731F/STR736F
WUP12 / CAN0RX / P1.14
CAN0TX / P1.15
PWM0 / P2.0
WUP13 / CAN1RX / P2.1
CAN1TX / P2.2
PWM1 / P2.3
PWM2 / P2.4
M0
RSTIN
M1
VDD
VSS
XTAL1
XTAL2
VSS
CAN2RX / TDO1 / P2.8
WUP14 / CAN2TX / RDI1 / P2.9
WUP15 / SCL0 / P2.14
SDA0 / P2.15
TEST
VBIAS
VSS
VDD
AIN0 / P3.4
AIN1 / P3.5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
OCMPB2 / P0.0
OCMPA2 / P0.1
ICAPA2 / P0.2
ICAPB2 / P0.3
OCMPA5 / P0.4
OCMPB5 / P0.5
ICAPA5 / P0.6
VDD
VSS
ICAPA3 / P0.12
ICAPB3 / P0.13
OCMPB3 / P0.14
OCMPA3 / P0.15
OCMPA4 / P1.0
OCMPB4 / P1.1
ICAPB4 / P1.2
ICAPA4 / P1.3
OCMPB1 / P1.6
OCMPA1 / P1.7
INT0 / OCMPA0 / P1.8
INT1 / OCMPB0 / P1.9
ICAPB0 / WUP28 / P1.10
ICAPA0 / WUP29 / P1.11
ICAPA1 / WUP30 / P1.12
ICAPB1 / WUP31 / P1.13
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P6.14 / SS0
P6.13 / SCK0 / WUP11
P6.12 / MOSI0
P6.11 / MISO0
P6.9 / TDO0
P6.8 / RDI0 / WUP10
P6.6 / WUP6
P6.4 / TDO3 / WUP4
P6.2 / RDI3 / WUP2
P6.0 / WUP0
VDD
VSS
V18
P5.12 / INT10
P5.11 / TDO2 / INT9
P5.10 / RDI2 / INT8
P5.9 / PWM5 / INT7
P5.8 / PWM4 / INT6
P5.7 / MISO2
P5.6 / MOSI2
P5.5 / SCK2 / WUP23
P5.4 / SS2 /PWM3
P5.1 / MISO1
P5.0 / MOSI1
P4.15 / SCK1 / WUP22
Figure 4. STR731F/STR736F Pin Configuration (top view)
Note 1: CAN alternate functions not available on STR736F.
12/22
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P4.14 / SS1
P4.10 / ICAPB5 / WUP20
P4.7 / SDA1
P4.6 / SCL1 / WUP19
VDD
VSS
JTDO
JTCK
JTMS
JTDI
JTRST
VSS
VDD
P3.15 / AIN11 / INT5
P3.14 / AIN10 / INT4
P3.13 / AIN9 / INT3
P3.12 / AIN8 / INT2
P3.11 / AIN7
P3.10 / AIN6
P3.9 / AIN5
P3.8 / AIN4
VDDA
VSSA
P3.7 / AIN3
P3.6 / AIN2
STR73xF Data Brief
Legend / Abbreviations for Table 3:
Type:
I = input, O = output, S = supply, HiZ= high impedance,
In/Output level: TT= TTL 0.8V / 2V with input trigger
CT= CMOS 0.3VDD/0.7VDD with input trigger
Port and control configuration:
– Input:
pu/pd = with internal 100kΩ weak pull-up or pull down
– Output:
OD = open drain (logic level)
PP = push-pull
Interrupts:
INTx =external interrupt line
WUPx =Wake-Up interrupt line
The reset state of the I/O ports is input floating. To avoid excess power consumption, unused I/O ports
must be tied to ground.
Table 3. STR73xF Pin Description
2
B2
2
3
C2
4
C3
5
D1
VSS
6
D2
VDD
7
B1
Alternate function
PP
Main
function
(after
reset)
OD
Capability
P0.0/OCMPB2
Output
interrupt
1
pu/pd
A1
Input Level
TQFP100
1
Pin Name
Type
LFBGA144
Input
TQFP144
Pin n°
2mA X
X
Port 0.0 TIM2: Output Compare B output
P0.1/OCMPA2
I/O TT
I/O TT
2mA X
X
Port 0.1 TIM2: Output Compare A output
3
P0.2/ICAPA2
I/O TT
2mA X
X
Port 0.2 TIM2: Input Capture A input
4
P0.3/ICAPB2
I/O TT
S
2mA X
X
Port 0.3 TIM2: Input Capture B input
Ground for digital I/O (5V)
S
Supply voltage for digital I/O (5V)
8
C1
6
P0.5/OCMPB5
I/O TT
I/O TT
2mA X
X
Port 0.5 TIM5: Output Compare B output
9
D3
7
P0.6/ICAPA5
I/O TT
2mA X
X
Port 0.6 TIM5: Input Capture A input
10
D4
P0.7/ICAPB5
2mA X
X
Port 0.7 TIM5: Input Capture B input
11
E1
P0.8/OCMPA6
I/O TT
I/O TT
2mA X
X
Port 0.8 TIM6: Output Compare A output
12
E2
P0.9/OCMPB6
I/O TT
2mA X
X
Port 0.9 TIM6: Output Compare B output
TIM7: Output Compare A output
TIM7: Output Compare B output
5
P0.4/OCMPA5
2mA X
X
Port 0.4 TIM5: Output Compare A output
13
E3
P0.10/OCMPA7 I/O TT
2mA X
X
Port
0.10
14
E4
P0.11/OCMPB7 I/O TT
2mA X
X
Port
0.11
15
F1
8
VDD
S
Supply voltage for digital I/O (5V)
16
G1
9
VSS
S
Ground for digital I/O (5V)
17
E5
10
P0.12/ICAPA3
I/O TT
2mA X
X
Port
0.12
TIM3: Input Capture A input
18
F2
11
P0.13/ICAPB3
I/O TT
2mA X
X
Port
0.13
TIM3: Input Capture B input
19
F3
12
P0.14/OCMPB3 I/O TT
2mA X
X
Port
0.14
TIM3: Output Compare B output
13/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Input
Output
OD
PP
P0.15/OCMPA3 I/O TT
2mA X
X
Port
0.15
21
F5
14
P1.0/OCMPA4
2mA X
X
Port 1.0 TIM4: Output Compare A output
22
F6
15
P1.1/OCMPB4
I/O TT
I/O TT
2mA X
X
Port 1.1 TIM4: Output Compare B output
23
G2
16
P1.2/ICAPB4
I/O TT
2mA X
X
Port 1.2 TIM4: Input Capture B input
24
G3
17
P1.3/ICAPA4
I/O TT
2mA X
X
Port 1.3 TIM4: Input Capture A input
Capability
13
interrupt
F4
pu/pd
TQFP100
20
Pin Name
Type
LFBGA144
Main
function
(after
reset)
TQFP144
Input Level
Pin n°
Alternate function
TIM3: Output Compare A output
25
G4
VSS
S
Ground for digital I/O (5V)
26
H1
VDD
S
Supply voltage for digital I/O (5V)
27
J1
P1.4
28
G5
29
K1
30
L1
31
H2
20
32
H3
33
2mA X
X
Port 1.4
P1.5
I/O TT
I/O TT
2mA X
X
Port 1.5
18
P1.6/OCMPB1
I/O TT
2mA X
X
Port 1.6 TIM1: Output Compare B output
19
P1.7/OCMPA1
2mA X
X
Port 1.7 TIM1: Output Compare A output
P1.8/OCMPA0
I/O TT
I/O TT
INT0
2mA X
X
Port 1.8 TIM0: Output Compare A output
21
P1.9/OCMPB0
I/O TT
INT1
2mA X
X
Port 1.9 TIM0: Output Compare B output
H4
22
P1.10/ICAPB0
I/O TT
WUP28 2mA X
X
Port
1.10
TIM0: Input Capture B input
34
J2
23
P1.11/ICAPA0
I/O TT
WUP29 2mA X
X
Port
1.11
TIM0: Input Capture A input
35
J3
24
P1.12/ICAPA1
I/O TT
WUP30 2mA X
X
Port
1.12
TIM1: Input Capture A input
36
K2
25
P1.13/ICAPB1
I/O TT
WUP31 2mA X
X
Port
1.13
TIM1: Input Capture B input
37
M1
26
P1.14/CAN0RX
I/O TT
WUP12 2mA X
X
Port
1.14
CAN0: Receive Data input
38
L2
27
P1.15/CAN0TX
I/O TT
2mA X
X
Port
1.15
CAN0: Transmit Data output
39
L3
28
P2.0/PWM0
2mA X
X
Port 2.0 PWM0: PWM output
40
K3
29
P2.1/CAN1RX
I/O TT
I/O TT
WUP13 2mA X
X
Port 2.1 CAN1: Receive Data input
41
M4
30
P2.2/CAN1TX
I/O TT
2mA X
X
Port 2.2 CAN1: Transmit Data output
42
L4
31
P2.3/PWM1
2mA X
X
Port 2.3 PWM1: PWM output
43
M2
32
P2.4/PWM2
I/O TT
I/O TT
2mA X
X
Port 2.4 PWM2: PWM output
44
M3
P2.5/PWM3
I/O TT
2mA X
X
Port 2.5 PWM3: PWM output
45
K4
P2.6/PWM4
I/O TT
2mA X
X
Port 2.6 PWM4: PWM output
46
J4
P2.7/PWM5
2mA X
X
Port 2.7 PWM5: PWM output
47
M5
33
M0
I/O TT
I TT
48
L5
34
RSTIN
49
K5
35
50
J5
36
14/22
pd
BOOT: Mode selection 0 input
I
CT pu
Reset input
M1
I
TT pd
BOOT: Mode selection 1 input
VDD
S
Supply voltage for digital I/O (5V)
STR73xF Data Brief
Table 3. STR73xF Pin Description
Input
Output
Ground for digital I/O (5V)
52
M7
38
XTAL1
I
Oscillator amplifier circuit input and internal
clock generator input.
53
H5
39
XTAL2
O
Oscillator amplifier circuit output.
54
L6
40
VSS
S
Ground for digital I/O (5V)
55
K6
41
P2.8/TDO1/
CAN2RX
I/O TT
2mA X
X
Port 2.8
CAN2: Receive
UART1: Transmit Data input
Data output
(TQFP100 only)
56
J6
42
P2.9/RDI1/
CAN2TX
I/O TT
WUP14 2mA X
X
Port 2.9
UART1: Receive
Data input
57
H6
P2.10
I/O TT
WUP16 2mA X
X
Port
2.10
58
G6
P2.11
I/O TT
WUP17 2mA X
X
Port
2.11
59
L7
P2.12
I/O TT
INT14 2mA X
X
Port
2.12
60
K7
P2.13
I/O TT
INT15 2mA X
X
Port
2.13
61
J7
43
P2.14/SCL0
I/O TT
WUP15 2mA X
X
Port
2.14
I2C0:Serial Clock
62
H7
44
P2.15/SDA0
I/O TT
2mA X
X
Port
2.15
I2C0:Serial Data
63
M8
45
Test
I
64
L8
46
VBIAS
S
Internal RC Oscillator bias. A 1.3MΩ external
resistor has to be connected to this pin when a
32kHZ RC oscillator frequency is used.
65 M10 47
VSS
S
Ground for digital I/O (5V)
66 M11 48
VDD
67
K8
P3.0/AIN0
68
J8
P3.1/AIN1
69
M9
P3.2/AIN2
70
L9
71
K9
PP
S
OD
VSS
Capability
37
interrupt
M6
pu/pd
TQFP100
51
Pin Name
Type
LFBGA144
Main
function
(after
reset)
TQFP144
Input Level
Pin n°
pd
Alternate function
CAN2: Transmit
Data output
(TQFP100 only)
Reserved pin. Must be tied to ground
S
Supply voltage for digital I/O (5V)
I/O TT
I/O TT
2mA X
X
Port 3.0 ADC: Analog input 0
2mA X
X
Port 3.1 ADC: Analog input 1
2mA X
X
Port 3.2 ADC: Analog input 2
P3.3/AIN3
I/O TT
I/O TT
2mA X
X
Port 3.3 ADC: Analog input 3
49
P3.4/AIN4
I/O TT
2mA X
X
Port 3.4
ADC: Analog input 4
(AIN0 in TQFP100)
72 L10 50
P3.5/AIN5
I/O TT
2mA X
X
Port 3.5
ADC: Analog input 5
(AIN1 in TQFP100)
73 M12 51
P3.6/AIN6
I/O TT
2mA X
X
Port 3.6
ADC: Analog input 6
(AIN2 in TQFP100)
74 L11 52
P3.7/AIN7
I/O TT
2mA X
X
Port 3.7
ADC: Analog input 7
(AIN3 in TQFP100)
15/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
PP
OD
Capability
Output
interrupt
pu/pd
Input Level
Pin Name
Type
Input
TQFP100
LFBGA144
TQFP144
Pin n°
Main
function
(after
reset)
Alternate function
75 K11 53
VSSA
S
Reference ground for A/D converter
76 K10 54
VDDA
S
Reference voltage for A/D converter
77 J12 55
P3.8/AIN8
I/O TT
2mA X
X
Port 3.8
ADC: Analog input 8
(AIN4 in TQFP100)
78 J11 56
P3.9/AIN9
I/O TT
2mA X
X
Port 3.9
ADC: Analog input 9
(AIN5 in TQFP100)
79 L12 57
P3.10/AIN10
I/O TT
2mA X
X
Port
3.10
ADC: Analog input 10
(AIN6 in TQFP100)
80 K12 58
P3.11/AIN11
I/O TT
2mA X
X
Port
3.11
ADC: Analog input 11
(AIN7 in TQFP100)
81 J10 59
P3.12/AIN12
I/O TT
INT2
2mA X
X
Port
3.12
ADC: Analog input 12
(AIN8 in TQFP100)
82
60
P3.13/AIN13
I/O TT
INT3
2mA X
X
Port
3.13
ADC: Analog input 13
(AIN9 in TQFP100)
83 H12 61
P3.14/AIN14
I/O TT
INT4
2mA X
X
Port
3.14
ADC: Analog input 14
(AIN10 in TQFP100)
84 H11 62
P3.15/AIN15
I/O TT
INT5
2mA X
X
Port
3.15
ADC: Analog input 15
(AIN11 in TQFP100)
85 H10 63
VDD
S
86
J9
H9
64
Supply voltage for digital I/O (5V)
VSS
S
87 G12 65
JTRST
I
TT
JTAG Reset Input
88 F12 66
JTDI
I
TT pu
JTAG Data input
89
Ground for digital I/O (5V)
67
JTMS
I
TT pu
JTAG Mode Selection Input
90 G11 68
JTCK
I
TT pd
JTAG Clock Input
91 G10 69
JTDO
O
92
S
H8
G9
70
VSS
93
G8
71
VDD
94
G7
P4.0/ICAPA7
95 F11
JTAG data output.
Note: Reset state = HiZ
4mA
Ground for digital I/O (5V)
S
Supply voltage for digital I/O (5V)
WUP24 2mA X
X
Port 4.0 TIM7: Input Capture A input
P4.1/ICAPB7
I/O TT
I/O TT
WUP25 2mA X
X
Port 4.1 TIM7: Input Capture B input
96 F10
P4.2/ICAPA8
I/O TT
WUP26 2mA X
X
Port 4.2 TIM8: Input Capture A input
97
F9
P4.3/ICAPB8
WUP27 2mA X
X
Port 4.3 TIM8: Input Capture B input
98
F8
P4.4/CAN2TX
I/O TT
I/O TT
2mA X
X
Port 4.4 CAN2: Transmit Data output
I/O TT
I/O TT
WUP18 2mA X
X
Port 4.5 CAN2: Receive Data input
WUP19 2mA X
X
Port 4.6 I2C1:Serial Clock
2mA X
X
Port 4.7 I2C1:Serial Data
2mA X
X
Port 4.8 TIM8: Output Compare A output
2mA X
X
Port 4.9 TIM6: Input Capture B input
99 E12
P4.5/CAN2RX
100 E11 72
P4.6/SCL1
101 C12 73
P4.7/SDA1
102 B12
P4.8/OCMPA8
I/O TT
I/O TT
103 E10
P4.9/ICAPB6
I/O TT
16/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
Alternate function
PP
Main
function
(after
reset)
OD
Capability
Output
interrupt
pu/pd
Input Level
74
Pin Name
Type
104 E9
TQFP144
TQFP100
Input
LFBGA144
Pin n°
I/O TT
WUP20 2mA X
X
Port
4.10
TIM6: Input
TIM5: Input
Capture A input
Capture B input
(144-pin pkg only) (TQFP100 only)
105 D12
P4.11/OCMPB8 I/O TT
2mA X
X
Port
4.11
TIM8: Output Compare B output
106 D11
P4.12/ICAPA9
I/O TT
WUP21 2mA X
X
Port
4.12
TIM9: Input Capture A input
107 D10
P4.13/ICAPB9
I/O TT
2mA X
X
Port
4.13
TIM9: Input Capture B input
108 C11 75
P4.14/SS1
I/O TT
2mA X
X
Port
4.14
BSPI1: Slave Select
109 B11 76
P4.15/SCK1
I/O TT
WUP22 2mA X
X
Port
4.15
BSPI1: Serial Clock
110 B10 77
P5.0/MOSI1
2mA X
X
Port 5.0 BSPI1: Master Output/Slave input
111 C10 78
P5.1/MISO1
I/O TT
I/O TT
2mA X
X
Port 5.1 BSPI1: Master input/Slave output
112 A9
P5.2/OCMPA9
I/O TT
2mA X
X
Port 5.2 TIM9: Output Compare A output
113 B9
P5.3/OCMPB9
I/O TT
2mA X
X
Port 5.3 TIM9: Output Compare B output
I/O TT
2mA X
X
Port 5.4
I/O TT
I/O TT
WUP23 2mA X
X
Port 5.5 BSPI2: Serial Clock
2mA X
X
Port 5.6 BSPI2: Master Output/Slave input
2mA X
X
Port 5.7 BSPI2: Master input/Slave output
INT6
2mA X
X
Port 5.8 PWM4: PWM output (TQFP100 only)
P4.10/ICAPA6/
ICAPB5
114 C9
79
P5.4/SS2/
PWM3
115 D9
80
P5.5/SCK2
BSPI2: Slave
Select
PWM3: PWM
output
(TQFP100 only)
116 A11 81
P5.6/MOSI2
117 A10 82
P5.7/MISO2
118 A8
83
P5.8/PWM4
I/O TT
I/O TT
119 B8
84
P5.9/PWM5
I/O TT
INT7
2mA X
X
Port 5.9 PWM5: PWM output (TQFP100 only)
120 C8
85
P5.10/RDI2
I/O TT
INT8
2mA X
X
Port
5.10
UART2: Receive Data input
121 A12 86
P5.11/TDO2
I/O TT
INT9
2mA X
X
Port
5.11
UART2: Transmit Data output
122 D8
P5.12
I/O TT
INT10 2mA X
X
Port
5.12
123 E8
P5.13
I/O TT
INT11 2mA X
X
Port
5.13
124 B7
P5.14
I/O TT
INT12 2mA X
X
Port
5.14
125 A7
P5.15
I/O TT
INT13 2mA X
X
Port
5.15
87
126 A6
88
V18
S
Supply voltage for core provided by
internal voltage regulator
127 C7
89
VSS
S
Ground for digital I/O (5V)
128 D7
90
VDD
S
Supply voltage for digital I/O (5V)
17/22
STR73xF Data Brief
Table 3. STR73xF Pin Description
92
133 D6
93
134 E6
135 A5
Capability
interrupt
pu/pd
WUP0 8mA X
X
Port 6.0
WUP1 2mA X
X
Port 6.1
P6.2/RDI3
I/O TT
WUP2 2mA X
X
Port 6.2 UART3: Receive Data input
P6.3
I/O TT
I/O TT
WUP3 2mA X
X
Port 6.3
WUP4 2mA X
X
Port 6.4 UART3: Transmit Data output
I/O TT
I/O TT
WUP5 2mA X
X
Port 6.5
WUP6 2mA X
X
Port 6.6
WUP7 2mA X
X
Port 6.7
WUP10 2mA X
X
Port 6.8 UART0: Receive Data input
P6.4/TDO3
P6.5
94
Alternate function
I/O TT
I/O TT
P6.0
P6.1
132 C6
Main
function
(after
reset)
PP
131 B6
Output
OD
130 F7
Input Level
91
Pin Name
Type
129 E7
TQFP144
TQFP100
Input
LFBGA144
Pin n°
P6.6
137 C5
95
P6.8/RDI0
I/O TT
I/O TT
138 A3
96
P6.9/TDO0
I/O TT
2mA X
X
Port 6.9 UART0: Transmit Data output
P6.10
I/O TT
WUP8 2mA X
X
Port
6.10
136 B5
P6.7
139 A2
140 D5
97
P6.11/MISO0
I/O TT
2mA X
X
Port
6.11
BSPI0: Master input/Slave output
141 A4
98
P6.12/MOSI0
I/O TT
2mA X
X
Port
6.12
BSPI0: Master Output/Slave input
142 B4
99
P6.13/SCK0
I/O TT
WUP11 2mA X
X
Port
6.13
BSPI0: Serial Clock
143 C4 100 P6.14/SS0
I/O TT
2mA X
X
Port
6.14
BSPI0: Slave Select
144 B3
I/O TT
WUP9 2mA X
X
Port
6.15
18/22
P6.15
STR73xF Data Brief
1.4 Memory Mapping
Figure 5 shows the various memory configurations of the STR73xF system. The system
memory map (from 0x0000_0000 to 0xFFFF_FFFF) is shown on the left part of the figure, the
right part shows maps of the Flash and APB areas. For flexibility the Flash or RAM addresses
can be aliased to Block 0 addresses using the remapping feature
Most reserved memory spaces (gray shaded areas in Figure 5) are protected from access by
the user code. When an access this memory space is attempted, an ABORT signal is
generated. Depending on the type of access, the ARM processor will enter “prefetch abort”
state (Exception vector 0x0000_000C) or “data abort” state (Exception vector 0x0000_0010).
It is up to the application software to manage these abort exceptions.
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STR73xF Data Brief
Figure 5. Memory Map
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
0xFFFF 8000
APB TO ARM7
BRIDGE
APB Memory Space
32 Kbytes
0xFFFF FFFF
32K
0xFFFF FC00
0xFFFF FBFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
7
FLASH Memory Space
64K/128/256 Kbytes
0xE000 0000
0xDFFF FFFF
F800
F7FF
F600
F400
F3FF
0xFFFF F000
0xFFFF EFFF
EIC
1K
ADC
1K
CMU
RTC
1K
DMA 0-3
1K
TIM 4
1K
TIM 3
1K
TIM 2
1K
BSPI 2
1K
BSPI 1
1K
0xFFFF EC00
0xFFFF EBFF
0x8010 DFFF
6
0x8010 C000
0x8010 0017
0x8010 0000
System Memory
Flash registers
8K
20B
0xFFFF E800
0xFFFF E7FF
0xFFFF E400
0xFFFF E3FF
0xFFFF E000
0xFFFF DFFF
0xC000 0000
0xBFFF FFFF
0xFFFF DC00
0xFFFF DBFF
0xFFFF D800
0xFFFF D7FF
5
0xA000 3FFF
0xA000 0000
0x9FFF FFFF
0xFFFF D400
0xFFFF D3FF
RAM
16K
0xFFFF D000
0xFFFF CFFF
0xFFFF CC00
0xFFFF CBFF
0xFFFF C800
0xFFFF C7FF
4
0x8010 0017
0x8000 0000
0x7FFF FFFF
0xFFFF C400
0xFFFF C3FF
FLASH
64K/128K/256K
0xFFFF C000
0xFFFF BFFF
0xFFFF BC00
0xFFFF BBFF
0xFFFF B800
0xFFFF B7FF
3
0x6000 03FF
0x6000 0000
0x5FFF FFFF
0xFFFF B400
0xFFFF B3FF
PRCCU
1K
0x8003 FFFF
0xFFFF B000
0xFFFF AFFF
B0F7(2)
2
0x4000 003F
0x4000 0000
0x3FFF FFFF
64K
0xFFFF AC00
0xFFFF ABFF
64K
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x8003 0000
0x8002 FFFF
CONFIG. REGS
B0F6(2)
64B
0x8002 0000
0x8001 FFFF
1
0x2000 000F
0x2000 0000
0x1FFF FFFF
B0F5(3)
1K
1K
PWM 0-5
1K
CAN 2(4)
1K
CAN 1(4)
1K
CAN 0(4)
1K
APB BRIDGE 1 REGS
1K
reserved
1K
WAKEUP
1K
reserved
1K
TIM 5-9
1K
TIM 1
1K
TIM 0
WAKEUPTIM
WDG
UART 3
UART 1
UART 2
UART 0
NATIVE ARBITER
16B
0
FLASH (1)
64K/128K/256K
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
8000
7FFF
6000
5FFF
4000
3FFF
2000
1FFF
0000
B0F3
B0F2
B0F1
B0TF
32K
8K
8K
8K
8K
0xFFFF 8C00
0xFFFF 8BFF
0xFFFF 8800
0xFFFF 87FF
0xFFFF 8400
0xFFFF 83FF
1K
1K
1K
reserved
1K
reserved
1K
reserved
1K
I2C 1
1K
0xFFFF 9800
0xFFFF 97FF
0xFFFF 9000
0xFFFF 8FFF
1K
1K
TB 0-2
0xFFFF 9400
0xFFFF 93FF
0x8001 0000
0x8000 FFFF
B0F4
0x0010 0017
0x0000 0000
64K
A800
A7FF
A600
A400
A3FF
A200
A000
9FFF
9E00
9C00
9BFF
BSPI 0
GP I/O 0-6
2
I C0
1K
APB BRIDGE 0 REGS
1K
0xFFFF 8000
(1) FLASH aliased at 0x0000 0000h by system decoder for booting with valid instruction upon RESET from Block B0 (8 Kbytes)
(2) Only available in STR73xZ2/V2
(3) Only available in STR73xZ2/V2 and STR73xZ1/V1
(4) Only available in STR730/STR731
Drawing not to scale
access to gray shaded area will return an ABORT
20/22
STR73xF Data Brief
2 ORDER CODES
Table 4. Order Codes
Partnumber
FLASH
Kbytes
STR730FZ1T7
STR730FZ2T7
STR730FZ1H7
STR730FZ2H7
STR735FZ1T7
STR735FZ2T7
STR735FZ1H7
STR735FZ2H7
128
256
128
256
128
256
128
256
STR731FV0T7
64
STR731FV1T7
128
STR731FV2T7
256
STR736FV0T7
64
STR736FV1T7
128
STR736FV2T7
256
Package
TIM
CAN
RAM
Kbytes Timers Periph.
TQFP144
20x20
10
TQFP144
20x20
I/O
Ports
Temp.
Range
16
32
112
0
-40 to
+105°C
16
TQFP100
14x14
3
6
TQFP100
14x14
Wake-up
Lines
Chan.
3
LFBGA144
10x10
LFBGA144
10x10
A/D
12
18
72
0
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STR73xF Data Brief
Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
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