STMICROELECTRONICS STD12N10L

STD12N10L

N - CHANNEL 100V - 0.12 Ω - 12A TO-252
LOW THRESHOLD POWER MOS TRANSISTOR
TYPE
STD12N10L
■
■
■
■
■
■
■
V DSS
R DS(o n)
ID
100 V
< 0.15 Ω
12 A
TYPICAL RDS(on) = 0.12 Ω
AVALANCHE RUGGED TECHNOLOGY
100% AVALANCHE TESTED
HIGH CURRENT CAPABILITY
175 oC OPERATING TEMPERATURE
LOW THRESHOLD DRIVE
FOR THROUGH-HOLE VERSION CONTACT
SALES OFFICE
3
1
DPAK
TO-252
(Suffix ”T4”)
APPLICATIONS
■ HIGH CURRENT, HIGH SPEED SWITCHING
■ SOLENOID AND RELAY DRIVERS
■ MOTOR CONTROL, AUDIO AMPLIFIERS
■ DC-DC & DC-AC CONVERTERS
■ AUTOMOTIVE ENVIRONMENT(INJECTION,
ABS, AIR-BG, LAMPDRIVERS, Etc.)
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symb ol
V DS
V DGR
VGS
Value
Unit
Drain-source Voltage (VGS = 0)
Parameter
100
V
Drain- gate Voltage (R GS = 20 kΩ)
100
V
± 15
V
Gate-source Voltage
o
ID
Drain Current (continuous) at Tc = 25 C
12
A
ID
Drain Current (continuous) at Tc = 100 C
8
A
Drain Current (pulsed)
48
A
50
W
0.33
W /o C
I DM (•)
P tot
o
o
Total Dissipation at T c = 25 C
Derating F actor
T st g
Tj
Storage T emperature
Max. Operating Junction Temperature
-65 to 175
o
C
175
o
C
(•) Pulse width limited by safe operating area
November 1999
1/9
STD12N10L
THERMAL DATA
R thj -case
R thj -amb
R thc-sink
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature F or Soldering Purpose
Max
Max
T yp
o
3
100
1.5
275
C/W
C/W
o
C/W
o
C
o
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
100
Unit
V
T c = 125 oC
V GS = ± 15 V
1
10
µA
µA
± 100
nA
Max.
Unit
ON (∗)
Symbo l
Parameter
Test Con ditions
V GS(th)
Gate Threshold Voltage V DS = V GS
ID = 250 µA
R DS(on)
Static Drain-source On
Resistance
V GS = 10V
V GS = 5V
ID = 6 A
ID = 6 A
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
1
Typ.
1.6
2.5
V
0.12
0.17
0.15
0.2
Ω
Ω
12
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/9
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
ID = 6 A
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
V GS = 0
f = 1 MHz
Min.
Typ.
Max.
Unit
6.5
10
S
800
150
50
pF
pF
pF
STD12N10L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Delay T ime
Rise Time
V DD = 50 V
ID = 6 A
R G = 4.7 Ω
V GS = 5 V
(Resistive Load, see fig. 3)
15
40
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 80 V ID = 12 A V GS = 5 V
20
6
10
30
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbo l
tr (Voff)
tf
tc
Parameter
Off-voltage Rise T ime
Fall T ime
Cross-over Time
Test Con ditions
Min.
12
12
25
V DD = 80 V
I D = 12 A
V GS = 5 V
R G = 4.7 Ω
(Induct ive Load, see fig. 5)
ns
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 12 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 12 A
di/dt = 100 A/µs
o
T j = 150 C
V DD = 30 V
(see test circuit, fig. 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
12
48
A
A
1.5
V
145
ns
580
µC
8
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
3/9
STD12N10L
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/9
STD12N10L
TO-252 (DPAK) MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.2
2.4
0.086
0.094
A1
0.9
1.1
0.035
0.043
A2
0.03
0.23
0.001
0.009
B
0.64
0.9
0.025
0.035
B2
5.2
5.4
0.204
0.212
C
0.45
0.6
0.017
0.023
C2
0.48
0.6
0.019
0.023
D
6
6.2
0.236
0.244
E
6.4
6.6
0.252
0.260
G
4.4
4.6
0.173
0.181
H
9.35
10.1
0.368
0.397
L2
0.8
L4
0.031
0.6
1
0.023
0.039
A1
C2
A
H
A2
C
DETAIL ”A”
L2
D
=
1
=
G
2
=
=
=
E
=
B2
3
B
DETAIL ”A”
L4
0068772-B
5/9
STD12N10L
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granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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6/9
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