STP4N20 N - CHANNEL 200V - 1.3 Ω - 4A TO-220 POWER MOS TRANSISTOR T YPE STP4N20 ■ ■ ■ ■ ■ ■ ■ V DSS R DS(on) ID 200 V < 1.5 Ω 4A TYPICAL RDS(on) = 1.3 Ω AVALANCHE RUGGED TECHNOLOGY 100% AVALANCHE TESTED LOW GATE CHARGE HIGH CURRENT CAPABILITY 150 oC OPERATING TEMPERATURE APPLICATION ORIENTED CHARACTERIZATION 3 1 APPLICATIONS ■ HIGH CURRENT, HIGH SPEED SWITCHING ■ SOLENOID AND RELAY DRIVERS ■ DC-DC CONVERTERS & DC-AC INVERTERS ■ TELECOMMUNICATION POWER SUPPLIES ■ INDUSTRIAL MOTOR DRIVERS 2 TO-220 INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS Value Un it Drain-source Voltage (VGS = 0) Parameter 200 V Drain- gate Voltage (R GS = 20 kΩ) 200 V ± 20 V G ate-source Voltage o ID Drain Current (continuous) at Tc = 25 C 4 A ID Drain Current (continuous) at Tc = 100 C 2.5 A Drain Current (pulsed) 16 A 60 W 0.48 W /o C I DM (•) P tot o o T otal Dissipation at Tc = 25 C Derating Factor Ts tg Tj Storage Temperature Max. Operating Junction Temperature -65 to 150 o C 150 o C (•) Pulse width limited by safe operating area February 1999 1/8 STP4N20 THERMAL DATA R thj -case Rthj -amb R thc-sink Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose o 2.08 62.5 0.5 300 C/W oC/W o C/W o C Max Value Unit 4 A 150 mJ AVALANCHE CHARACTERISTICS Symbo l Parameter IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 50 V) ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 µA V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 200 Unit V T c = 125 oC V GS = ± 20 V 1 10 µA µA ± 100 nA Max. Unit ON (∗) Symbo l Parameter Test Con ditions V GS(th) Gate Threshold Voltage V DS = V GS ID = 250 µA R DS(on) Static Drain-source On Resistance V GS = 10V ID = 30 A I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 2 Typ. 3 4 V 1.3 1.5 Ω 4 A DYNAMIC Symbo l g f s (∗) C iss C os s C rss 2/8 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =2 A V GS = 0 Min. Typ. Max. Unit 0.8 1.3 S 290 50 9 pF pF pF STP4N20 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 100 V ID = 2 A R G = 4.7 Ω V GS = 10 V (Resistive Load, see fig. 3) 7 6 ns ns Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 160 V 13 7 4 nC nC nC ID = 4 A V GS = 10 V SWITCHING OFF Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(of f) tf Turn-off Delay T ime Fall T ime V DD = 15 V I D = 40 A V GS = 10 V R G =4.7 Ω (Resistive Load, see fig. 3) 105 120 ns ns tr (Voff) tf tc Off-voltage Rise T ime Fall T ime Cross-over Time V clamp = 160 V ID = 4 A V GS = 10 V R G = 4.7 Ω (Induct ive Load, see fig. 5) 6 5 13 ns ns ns SOURCE DRAIN DIODE Symbo l Parameter Test Con ditions ISD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 160 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 4 A di/dt = 100 A/µs V DD = 30 V (see test circuit, fig. 5) t rr Q rr I RRM Min. Typ. V GS = 0 Max. Unit 4 16 A A 1.5 V 70 ns 1 µC 13 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STP4N20 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP4N20 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STP4N20 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP4N20 TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP4N20 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. 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