STD16NF06L N-CHANNEL 60V - 0.060 Ω - 24A DPAK/IPAK STripFET™ II POWER MOSFET Table 1: General Features TYPE STD16NF06L ■ ■ ■ ■ Figure 1:Package VDSS RDS(on) ID 60 V < 0.070 Ω 24 A TYPICAL RDS(on) = 0.060 Ω LOGIC LEVEL DEVICE THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX “-1") SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4") DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size™" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility 3 3 2 1 1 IPAK TO-251 (Suffix “-1”) DPAK TO-252 (Suffix “T4”) Figure 2: Internal Schematic Diagram APPLICATIONS ■ SWITCHING APPLICATIONS Table 2: Order Codes SALES TYPE STD16NF06LT4 STD16NF06L-1 MARKING D16NF06L D16NF06L PACKAGE TO-252 TO-251 PACKAGING TAPE & REEL TUBE Table 3: ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID ID IDM(•) Ptot dv/dt (1) EAS (2) Tstg Tj Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 kΩ) Gate- source Voltage Drain Current (continuous) at TC = 25°C Drain Current (continuous) at TC = 100°C Drain Current (pulsed) Total Dissipation at TC = 25°C Derating Factor Peak Diode Recovery voltage slope Single Pulse Avalanche Energy Storage Temperature Operating Junction Temperature (•) Pulse width limited by safe operating area. March 2005 Value 60 60 ± 18 24 17 96 40 0.27 11.5 200 Unit V V V A A A W W/°C V/ns mJ -55 to 175 °C (1) ISD ≤16A, di/dt ≤200A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX (2) Starting Tj = 25 oC, ID = 20A, VDD= 48V Rev. 3.0 1/11 STD16NF06L Table 4: THERMAL DATA Rthj-case Rthj-pcb Tl Thermal Resistance Junction-case (*)Thermal Resistance Junction-PCB Maximum Lead Temperature For Soldering Purpose (1.6 mm from case, for 10 sec) Max Max °C/W °C/W °C 3.75 62 275 (*) When Mounted on 1 inch2 FR-4 board, 2 oz of Cu ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) Table 5: OFF Symbol Parameter Test Conditions Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating VDS = Max Rating TC = 125°C IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 18V V(BR)DSS Min. Typ. Max. 60 Unit V 1 10 µA µA ±100 nA Max. Unit Table 6: ON (5) Symbol Parameter Test Conditions VGS(th) Gate Threshold Voltage VDS = VGS RDS(on) Static Drain-source On Resistance VGS = 10 V VGS = 5 V ID = 250 µA Min. Typ. 1 ID = 8 A ID = 8 A V 0.060 0.070 0.070 0.085 Ω Ω Typ. Max. Unit Table 7: DYNAMIC Symbol 2/11 Parameter Test Conditions gfs (*) Forward Transconductance VDS = 15 V Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance VDS = 25V f = 1 MHz VGS = 0 ID = 12 A Min. 12 S 370 69 30 pF pF pF STD16NF06L ELECTRICAL CHARACTERISTICS (continued) Table 8: SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 30 V ID = 8 A VGS = 5 V RG = 4.7 Ω (Resistive Load, Figure 17) 12 30 ns ns Qg Qgs Qgd Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD= 30 V ID= 16 A VGS= 5 V 7.5 2.5 4.2 nC nC nC Table 9: SWITCHING OFF Symbol td(off) tf Parameter Test Conditions Min. VDD = 30 V ID = 8 A VGS = 5 V RG = 4.7Ω, (Resistive Load, Figure 17) Turn-off Delay Time Fall Time Typ. Max. 20 6 Unit ns ns Table 10: SOURCE DRAIN DIODE Symbol Parameter ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) VSD (*) Forward On Voltage ISD = 64 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD =16 A di/dt = 100A/µs Tj = 150°C VDD = 25 V (see test circuit, Figure 19) trr Qrr IRRM (1 )Pulse width limited by safe operating area. (2) Pulsed: Pulse duration = 300 µs, duty cycle Figure 3: Safe Operating Area Test Conditions Min. Typ. VGS = 0 53 85 3.2 Max. Unit 16 64 A A 1.5 V ns µC A 1.5 %. Figure 4: Thermal Impedance 3/11 STD16NF06L Figure 5: Output Characteristics Figure 6: Transfer Characteristics Figure 7: Transconductance Figure 8: Static Drain-source On Resistance Figure 9: Gate Charge vs Gate-source Voltage Figure 10: Capacitance Variations 4/11 STD16NF06L Figure 11: Normalized Gate Threshold Voltage vs Temperature Figure 12: Normalized on Resistance vs Temperature Figure 13: Source-drain Diode Forward Characteristics Figure 14: Normalized Breakdown Voltage vs Temperature. . . 5/11 STD16NF06L Figure 15: Unclamped Inductive Load Test Circuit Figure 16: Unclamped Inductive Waveform Figure 17: Switching Times Test Circuits For Resistive Load Figure 18: Gate Charge test Circuit Figure 19: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/11 STD16NF06L TO-252 (DPAK) MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 L4 0.031 0.6 1 0.023 0.039 A1 C2 A H A2 C DETAIL "A" L2 D = 1 = G 2 = = = E = B2 3 B DETAIL "A" L4 0068772-B 7/11 STD16NF06L TO-251 (IPAK) MECHANICAL DATA mm DIM. MIN. inch MAX. MIN. A 2.2 TYP. 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 TYP. MAX. 0.85 B5 0.033 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A1 C2 A3 A C H B B3 = 1 = 2 G = = = E B2 = 3 B5 L D B6 L2 L1 0068771-E 8/11 STD16NF06L *on sales type 9/11 STD16NF06L Table 11:Revision History 10/11 Date Revision March 2005 3.0 Description of Changes ADDED PACKAGE TO-251 STD16NF06L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. © 2005 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco -Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America. www.st.com 11/11