STN3NE06 N - CHANNEL 60V - 0.08Ω - 3A - SOT-223 STripFET POWER MOSFET TYPE V DSS R DS(on) ID ST N3NE06 60 V < 0.100 Ω 3 A ■ ■ ■ ■ ■ TYPICAL RDS(on) = 0.08 Ω EXCEPTIONAL dv/dt CAPABILITY AVALANCHE RUGGED TECHNOLOGY 100 % AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION 2 DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique ”Single Feature Size ” stip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 1 2 3 SOT-223 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ DC MOTOR CONTROL (DISK DRIVES,etc.) ■ DC-DC & DC-AC CONVERTERS ■ SYNCHRONOUS RECTIFICATION ABSOLUTE MAXIMUM RATINGS Symbol V DS Parameter Drain-source Voltage (VGS = 0) V DGR Drain- gate Voltage (RGS = 20 kΩ) V GS Gate-source Voltage o ID Drain Current (continuous) at T c = 25 C ID Drain Current (continuous) at T c = 100 C I DM (•) P to t o Drain Current (pulsed) o Total Dissipation at Tc = 25 C Derating Factor dv/dt( 1 ) T st g Tj Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction T emperature (•) Pulse width limited by safe operating area New RDS (on) spec. starting from JULY 98 August 1998 Value Unit 60 V 60 V ± 20 V 3 A 1.8 A 12 A 2.5 W 0.02 W/ o C 6 V/ns -65 to 150 o C 150 o C (1) ISD ≤ 12 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/9 STN3NE06 THERMAL DATA R thj -pcb R t hj- amb Tl Thermal Resistance Junction-PC Board Max Thermal Resistance Junction-ambient Max (Surface Mounted) Maximum Lead Temperature For Soldering Purpose o 50 60 o C/W C/W o 260 C AVALANCHE CHARACTERISTICS Symb ol Parameter Max Valu e Unit I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 3 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 25 V) 20 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 µA V DS = Max Rating Zero G ate Voltage Drain Current (VGS = 0) V DS = Max Rating o C Gate-body Leakage Current (V DS = 0) Min. Typ . Max. 60 V GS = 0 Un it V T c = 125 V GS = ± 20 V 1 10 µA µA ± 100 nA ON (∗) Symb ol Parameter Test Cond ition s ID = 250 µA V GS(th) Gate Threshold Voltage R DS( on) Static Drain-source On V GS = 10 V Resistance ID(o n) V DS = VGS Min. Typ . Max. Un it 2 3 4 V 0.080 0.100 Ω I D = 6A 3 On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/9 Parameter Test Cond ition s Forward Transconductance V DS > I D(on) x R DS(on) max Input Capacitance Output Capacitance Reverse T ransfer Capacitance V DS = 25 V f = 1 MHz I D = 1.5 A VGS = 0 V Min. Typ . 1 3 760 100 30 Max. Un it S 1000 140 45 pF pF pF STN3NE06 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol Typ . Max. Un it t d(on) tr Turn-on Time Rise Time Parameter V DD = 30 V R G = 4.7 Ω Test Cond ition s ID = 6 A VGS = 10 V Min. 10 35 15 50 ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 40 V I D = 12 A 20 5 7 25 nC nC nC Typ . Max. Un it 7 18 30 10 25 45 ns ns ns Typ . Max. Un it 3 12 A A 1.5 V V GS = 10 V SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s V DD = 48 V R G = 4.7 W Min. I D = 12 A V GS = 10 V SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 3 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 12 A V DD = 30 V t rr Q rr I RRM Min. VGS = 0 di/dt = 100 A/µs o T j = 150 C 65 ns 0.18 µC 5.5 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/9 STN3NE06 Derating Curve Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage 4/9 STN3NE06 Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Cross-over Time Source-drain Diode Forward Characteristics 5/9 STN3NE06 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STN3NE06 SOT-223 MECHANICAL DATA mm DIM. mils MIN. TYP. MAX. MIN. TYP. MAX. a 2.27 2.3 2.33 89.4 90.6 91.7 b 4.57 4.6 4.63 179.9 181.1 182.3 c 0.2 0.4 0.6 7.9 15.7 23.6 d 0.63 0.65 0.67 24.8 25.6 26.4 e1 1.5 1.6 1.7 59.1 63 66.9 e4 0.32 12.6 f 2.9 3 3.1 114.2 118.1 122.1 g 0.67 0.7 0.73 26.4 27.6 28.7 l1 6.7 7 7.3 263.8 275.6 287.4 l2 3.5 3.5 3.7 137.8 137.8 145.7 L 6.3 6.5 6.7 248 255.9 263.8 L e1 l2 d a c b e4 f l1 C B C E g P008B 7/9 STN3NE06 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1998 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. . 8/9