STMICROELECTRONICS STW50N10

STW50N10
N - CHANNEL ENHANCEMENT MODE
POWER MOS TRANSISTOR
TYPE
ST W50N10
■
■
■
■
■
■
■
V DSS
R DS(on)
ID
100 V
< 0.035 Ω
50 A
TYPICAL RDS(on) = 0.027 Ω
AVALANCHE RUGGED TECHNOLOGY
100% AVALANCHE TESTED
REPETITIVE AVALANCHE DATA AT 100oC
HIGH CURRENT CAPABILITY
175oC OPERATING TEMPERATURE
APPLICATION ORIENTED
CHARACTERIZATION
3
2
1
APPLICATIONS
■
HIGH CURRENT, HIGH SPEED SWITCHING
■
POWER MOTOR CONTROL
■
DC-DC & DC-AC CONVERTERS
■
SYNCRONOUS RECTIFICATION
TO-247
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Uni t
V DS
Drain-source Voltage (V GS = 0)
Parameter
100
V
VDGR
Drain- gate Voltage (R GS = 20 kΩ)
100
V
V GS
Gate-source Voltage
± 20
V
o
ID
Drain Current (continuous) at T c = 25 C
50
A
ID
Drain Current (continuous) at T c = 100 o C
35
A
Drain Current (pulsed)
200
A
Total Dissipation at Tc = 25 C
180
W
Derating Factor
1.2
W/ o C
I DM (•)
P t ot
T stg
Tj
o
St orage Temperature
Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
January 1998
-65 to 175
o
C
175
o
C
ISD ≤ 60 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
1/8
STW50N10
THERMAL DATA
R t hj-ca se
R t hj- amb
R thc- si nk
Tl
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Thermal Resistance Case-sink
Maximum Lead Temperature For Soldering Purpose
Max
Max
T yp
o
0.83
30
0.1
300
C/W
C/W
o
C/W
o
C
o
AVALANCHE CHARACTERISTICS
Symb ol
Parameter
I AR
Avalanche Current, Repetitive or Not-Repetitive
(pulse width limited by Tj max, δ < 1%)
E AS
Single Pulse Avalanche Energy
(starting Tj = 25 o C, I D = IAR , VDD = 25 V)
Max Valu e
Unit
50
A
400
mJ
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symb ol
V (BR)DSS
I DSS
I GSS
Parameter
Drain-source
Breakdown Voltage
Test Cond ition s
I D = 250 µA
Gate-body Leakage
Current (V DS = 0)
Typ .
Max.
100
V GS = 0
Zero G ate Voltage
V DS = Max Rating
Drain Current (VGS = 0) V DS = Max Rating
o
C
Min.
Un it
V
T c = 125
V GS = ± 20 V
1
10
µA
µA
± 100
nA
ON (∗)
Symb ol
Parameter
Test Cond ition s
ID = 250 µA
V GS(th)
Gate Threshold
Voltage
R DS( on)
Static Drain-source On V GS = 10 V
Resistance
ID(o n)
V DS = VGS
Min.
Typ .
Max.
Un it
2
3
4
V
0.027
0.035
Ω
ID = 25 A
On State Drain Current V DS > I D(on) x R DS(on) max
V GS = 10 V
50
A
DYNAMIC
Symb ol
g fs (∗)
C iss
C oss
C rss
2/8
Parameter
Test Cond ition s
Forward
Transconductance
V DS > I D(on) x R DS(on) max
Input Capacitance
Output Capacitance
Reverse T ransfer
Capacitance
V DS = 25 V
f = 1 MHz
I D = 25 A
VGS = 0
Min.
Typ .
20
45
4100
600
150
Max.
Un it
S
5200
800
200
pF
pF
pF
STW50N10
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symb ol
Parameter
Test Cond ition s
t d(on)
tr
Turn-on Time
Rise Time
V DD = 50 V
R G = 4.7 Ω
Qg
Q gs
Q gd
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 80 V
Min.
ID = 25 A
VGS = 10 V
I D = 50 A
V GS = 10 V
Typ .
Max.
Un it
25
75
35
105
ns
ns
120
20
50
170
nC
nC
nC
Typ .
Max.
Un it
30
35
65
45
50
95
ns
ns
ns
Typ .
Max.
Un it
50
200
A
A
1.5
V
200
ns
1.4
µC
14
A
SWITCHING OFF
Symb ol
t r(Vof f)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Cond ition s
Min.
V DD = 80 V I D = 50 A
R G = 4.7 Ω V GS = 10 V
SOURCE DRAIN DIODE
Symb ol
Parameter
Test Cond ition s
I SD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD = 50 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 50 A
V DD = 30 V
t rr
Q rr
I RRM
Min.
V GS = 0
di/dt = 100 A/µs
o
Tj = 150 C
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
( 1) ISD ≤ 60 A, di/dt ≤ 200 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX
Safe Operating Area
Thermal Impedance
3/8
STW50N10
Output Characteristics
Transfer Characteristics
Transconductance
Static Drain-source On Resistance
Gate Charge vs Gate-source Voltage
Capacitance Variations
4/8
STW50N10
Normalized Gate Threshold Voltage vs
Temperature
Normalized On Resistance vs Temperature
Source-drain Diode Forward Characteristics
5/8
STW50N10
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
6/8
STW50N10
TO-247 MECHANICAL DATA
mm
DIM.
MIN.
TYP.
inch
MAX.
MIN.
TYP.
MAX.
A
4.7
5.3
0.185
0.209
D
2.2
2.6
0.087
0.102
E
0.4
0.8
0.016
0.031
F
1
1.4
0.039
0.055
F3
2
2.4
0.079
0.094
F4
3
3.4
0.118
0.134
G
10.9
0.429
H
15.3
15.9
0.602
0.626
L
19.7
20.3
0.776
0.779
L3
14.2
14.8
0.559
0.413
L4
34.6
1.362
L5
5.5
0.217
0.582
M
2
3
0.079
0.118
Dia
3.55
3.65
0.140
0.144
P025P
7/8
STW50N10
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectonics.
 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES
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