STP20NE10 N - CHANNEL 100V - 0.07Ω - 20A - TO-220 STripFET MOSFET TYPE ST P20NE10 ■ ■ ■ ■ V DSS R DS(on) ID 100 V < 0.1 Ω 20 A TYPICAL RDS(on) = 0.07 Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION DESCRIPTION This Power MOSFET is the latest development of SGS-THOMSON unique ”Single Feature Size ” strip-based process.The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 1 2 3 TO-220 INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ SOLENOID AND RELAY DRIVERS ■ MOTOR CONTROL, AUDIO AMPLIFIERS ■ DC-DC CONVERTERS ■ AUTOMOTIVE ENVIRONMENT ABSOLUTE MAXIMUM RATINGS Symbol Value Uni t Drain-source Voltage (V GS = 0) 100 V V DGR Drain- gate Voltage (R GS = 20 kΩ) 100 V V GS Gate-source Voltage ± 20 V V DS Parameter o ID Drain Current (continuous) at Tc = 25 C 20 A ID Drain Current (continuous) at Tc = 100 oC 14 A Drain Current (pulsed) 80 A Total Dissipation at Tc = 25 C 90 W Derating F actor 0.6 W/ o C 7 V/ ns IDM (•) P t ot dv/dt( 1 ) T stg Tj o Peak Diode Recovery voltage slope Storage T emperature Max. O perating Junction Temperature (•) Pulse width limited by safe operating area July 1998 -65 to 175 o C 175 o C ( 1) ISD ≤ 20 A, di/dt ≤ 300 A/µs, VDD ≤ V(BR)DSS, Tj ≤ TJMAX 1/8 STP20NE10 THERMAL DATA R t hj-ca se Rthj -amb R thc- si nk Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose o 1.67 62.5 0.5 300 C/W oC/W o C/W o C Max Valu e Unit 20 A 170 mJ AVALANCHE CHARACTERISTICS Symb ol Parameter I AR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ < 1%) E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, I D = IAR , VDD = 30 V) ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symb ol V (BR)DSS I DSS I GSS Parameter Drain-source Breakdown Voltage Test Cond ition s I D = 250 µA Gate-body Leakage Current (V DS = 0) Typ . Max. 100 V GS = 0 Zero G ate Voltage V DS = Max Rating Drain Current (VGS = 0) V DS = Max Rating o C Min. Un it V T c = 125 V GS = ± 20 V 1 10 µA µA ± 100 nA ON (∗) Symb ol Parameter Test Cond ition s ID = 250 µA V GS(th) Gate Threshold Voltage R DS( on) Static Drain-source On V GS = 10V Resistance ID(o n) V DS = VGS Min. Typ . Max. Un it 2 3 4 V 0.07 0.1 Ω ID = 10 A On State Drain Current V DS > I D(on) x R DS(on) max V GS = 10 V 20 A DYNAMIC Symb ol g fs (∗) C iss C oss C rss 2/8 Parameter Test Cond ition s Forward Transconductance V DS > I D(on) x R DS(on) max Input Capacitance Output Capacitance Reverse T ransfer Capacitance V DS = 25 V f = 1 MHz I D =10 A VGS = 0 Min. Typ . Max. 6 Un it S 1600 180 50 2100 250 70 pF pF pF STP20NE10 ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symb ol Typ . Max. Un it t d(on) tr Turn-on Time Rise Time Parameter V DD = 30 V ID = 10 A VGS = 10 V R G =4.7 Ω (see test circuit, figure 3) Test Cond ition s 17 37 23 50 ns ns Qg Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 80 V 38 10 12 50 nC nC nC Typ . Max. Un it 11 18 32 15 25 44 ns ns ns Typ . Max. Un it 16 64 A A 1.5 V I D = 20 A Min. V GS = 10 V SWITCHING OFF Symb ol t r(Vof f) tf tc Parameter Off-voltage Rise Time Fall Time Cross-over Time Test Cond ition s Min. V DD = 80 V I D = 20 A R G =4.7 Ω VGS = 10 V (see test circuit, figure 5) SOURCE DRAIN DIODE Symb ol Parameter Test Cond ition s I SD I SDM (•) Source-drain Current Source-drain Current (pulsed) V SD (∗) Forward On Voltage I SD = 20 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current di/dt = 100 A/µs I SD = 20 A o Tj = 150 C V DD = 30 V (see test circuit, figure 5) t rr Q rr I RRM Min. V GS = 0 110 ns 440 µC 8 A (∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance 3/8 STP20NE10 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP20NE10 Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/8 STP20NE10 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP20NE10 TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 0.551 L2 16.4 L4 0.645 13.0 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP20NE10 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. 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