STMICROELECTRONICS STP36NF03L

STP36NF03L

N-CHANNEL 30V - 0.015 Ω - 36A TO-220
LOW GATE CHARGE STripFET POWER MOSFET
PRELIMINARY DATA
T YPE
STP36NF03L
■
■
■
■
■
V DSS
R DS(on)
ID
30 V
< 0.02 Ω
36 A
TYPICAL RDS(on) = 0.015 Ω
TYPICAL Qg = 18 nC @ 10V
OPTIMAL RDS(on) x Qg TRADE-OFF
CONDUCTION LOSSES REDUCED
SWITCHING LOSSES REDUCED
DESCRIPTION
This application specific Power Mosfet is the third
generation of STMicroelectronics unique ”Single
Feature Size” strip-based process. The resulting transistor shows the best trade-off between
on-resistance and gate charge. When used as
high and low side in buck regulators, it gives the
best performance in terms of both conduction and
switching losses. This is extremely important for
motherboards where fast switching and high efficiency are of paramount importance.
3
1
2
TO-220
INTERNAL SCHEMATIC DIAGRAM
APPLICATIONS
■ SPECIFICALLY DESIGNED AND
OPTIMISED FOR HIGH EFFICIENCY CPU
CORE DC/DC CONVERTERS
ABSOLUTE MAXIMUM RATINGS
Symbol
V DS
V DGR
V GS
Value
Un it
Drain-source Voltage (VGS = 0)
Parameter
30
V
Drain- gate Voltage (R GS = 20 kΩ)
30
V
± 20
V
G ate-source Voltage
o
ID
Drain Current (continuous) at Tc = 25 C
36
A
ID
Drain Current (continuous) at Tc = 100 C
o
25
A
Drain Current (pulsed)
144
A
T otal Dissipation at Tc = 25 C
75
W
Derating Factor
0.5
W /o C
I DM (•)
P tot
Ts tg
Tj
o
Storage Temperature
Max. Operating Junction Temperature
-65 to 175
o
C
175
o
C
(•) Pulse width limited by safe operating area
January 2000
1/6
STP36NF03L
THERMAL DATA
R thj -case
R thj -amb
Tl
Thermal Resistance Junction-case
Max
Thermal Resistance Junction-ambient
Max
Maximum Lead Temperature F or Soldering Purpose
o
2
62.5
300
o
C/W
C/W
o
C
ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified)
OFF
Symbo l
V (BR)DSS
Parameter
Drain-source
Breakdown Voltage
Test Con ditions
I D = 250 µA
V GS = 0
I DSS
V DS = Max Rating
Zero Gate Voltage
Drain Current (V GS = 0) V DS = Max Rating
IGSS
Gate-body Leakage
Current (VDS = 0)
Min.
Typ.
Max.
30
Unit
V
T c =125 oC
V GS = ± 20 V
1
10
µA
µA
± 100
nA
Max.
Unit
2.5
V
0.020
0.035
Ω
Ω
ON (∗)
Symbo l
Parameter
Test Con ditions
ID = 250 µA
V GS(th)
Gate Threshold Voltage V DS = V GS
R DS(on)
Static Drain-source On
Resistance
V GS = 10V
V GS = 5V
I D(o n)
On State Drain Current
V DS > ID(o n) x R DS(on )ma x
V GS = 10 V
Min.
Typ.
1
ID = 18 A
ID = 9 A
0.015
0.026
36
A
DYNAMIC
Symbo l
g f s (∗)
C iss
C os s
C rss
2/6
Parameter
Test Con ditions
Forward
Transconductance
V DS > ID(o n) x R DS(on )ma x
Input Capacitance
Output Capacitance
Reverse Transfer
Capacitance
V DS = 25 V
f = 1 MHz
I D =18 A
V GS = 0
Min.
Typ.
Max.
Unit
20
S
750
270
60
pF
pF
pF
STP36NF03L
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbo l
Parameter
Test Con ditions
Min.
Typ.
Max.
Unit
t d(on)
tr
Turn-on Delay T ime
Rise Time
V DD = 15 V
I D = 18 A
R G = 4.7 Ω
V GS = 4.5 V
(Resistive Load, see fig. 3)
16
200
Qg
Q gs
Q gd
Total G ate Charge
Gate-Source Charge
Gate-Drain Charge
V DD = 24 V ID = 32 A V GS = 10 V
18
3
5
21
nC
nC
nC
Typ.
Max.
Unit
ns
ns
SWITCHING OFF
Symbo l
t d(of f)
tf
Parameter
Turn-off Delay T ime
Fall T ime
Test Con ditions
Min.
35
40
V DD = 15 V
I D = 18 A
V GS = 4.5 V
R G = 4.7 Ω
(Resistive Load, see fig. 3)
ns
ns
SOURCE DRAIN DIODE
Symbo l
Parameter
Test Con ditions
ISD
I SDM (•)
Source-drain Current
Source-drain Current
(pulsed)
V SD (∗)
Forward On Voltage
I SD =36 A
Reverse Recovery
Time
Reverse Recovery
Charge
Reverse Recovery
Current
I SD = 36 A
di/dt = 100 A/µs
o
T j = 150 C
V DD = 15 V
(see test circuit, fig. 5)
t rr
Q rr
I RRM
Min.
Typ.
V GS = 0
Max.
Unit
36
144
A
A
1.5
V
38
ns
30
nC
1.6
A
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
3/6
STP36NF03L
Fig. 1: Unclamped Inductive Load Test Circuit
Fig. 2: Unclamped Inductive Waveform
Fig. 3: Switching Times Test Circuits For
Resistive Load
Fig. 4: Gate Charge test Circuit
Fig. 5: Test Circuit For Inductive Load Switching
And Diode Recovery Times
4/6
STP36NF03L
TO-220 MECHANICAL DATA
mm
DIM.
MIN.
inch
TYP.
MAX.
MIN.
TYP.
MAX.
A
4.40
4.60
0.173
0.181
C
1.23
1.32
0.048
0.051
D
2.40
2.72
0.094
D1
0.107
1.27
0.050
E
0.49
0.70
0.019
0.027
F
0.61
0.88
0.024
0.034
F1
1.14
1.70
0.044
0.067
F2
1.14
1.70
0.044
0.067
G
4.95
5.15
0.194
0.203
G1
2.4
2.7
0.094
0.106
H2
10.0
10.40
0.393
0.409
14.0
0.511
L2
16.4
L4
0.645
13.0
0.551
2.65
2.95
0.104
0.116
L6
15.25
15.75
0.600
0.620
L7
6.2
6.6
0.244
0.260
L9
3.5
3.93
0.137
0.154
DIA.
3.75
3.85
0.147
0.151
D1
C
D
A
E
L5
H2
G
G1
F1
L2
F2
F
Dia.
L5
L9
L7
L6
L4
P011C
5/6
STP36NF03L
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are
subjec t to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
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