STP40NF10L N-CHANNEL 100V - 0.028Ω - 40A TO-220 LOW GATE CHARGE STripFET™ POWER MOSFET TYPE STP40NF10L ■ ■ ■ ■ VDSS RDS(on) ID 100 V < 0.033 Ω 40 A TYPICAL RDS(on) = 0.028Ω EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED APPLICATION ORIENTED CHARACTERIZATION 3 1 2 TO-220 DESCRIPTION This Power Mosfet series realized with STMicroelectronics unique STripFET process has specifically been designed to minimize input capacitance and gate charge. It is therefore suitable as primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer application. It is also intended for any application with low gate charge drive requirements. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS ■ HIGH-EFFICIENCY DC-DC CONVERTERS ■ UPS AND MOTOR CONTROL ■ AUTOMOTIVE ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS Parameter Value Unit 100 V Drain-gate Voltage (RGS = 20 kΩ) 100 V Gate- source Voltage ± 17 V Drain-source Voltage (VGS = 0) ID Drain Current (continuos) at TC = 25°C 40 A ID Drain Current (continuos) at TC = 100°C 25 A Drain Current (pulsed) 160 A Total Dissipation at TC = 25°C 150 W 1 W/°C 430 mJ IDM (l) PTOT Derating Factor EAS (1) Tstg Tj Single Pulse Avalanche Energy Storage Temperature Max. Operating Junction Temperature (●) Pulse width limited by safe operating area June 2002 –65 to 175 °C 175 °C (1) Starting T j = 25°C, I D = 20A, VDD = 40V 1/8 STP40NF10L THERMAL DATA Rthj-case Thermal Resistance Junction-case Max Rthj-amb Tl 1 °C/W Thermal Resistance Junction-ambient Max 62.5 °C/W Maximum Lead Temperature For Soldering Purpose 300 °C ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Test Conditions Min. Typ. Max. 100 Unit Drain-source Breakdown Voltage ID = 250 µA, VGS = 0 V Zero Gate Voltage Drain Current (VGS = 0) VDS = Max Rating 1 µA VDS = Max Rating, TC = 125 °C 10 µA Gate-body Leakage Current (VDS = 0) VGS = ± 17V ±100 nA ON (1) Symbol Parameter VGS(th) Gate Threshold Voltage RDS(on) Static Drain-source On Resistance Test Conditions Min. Typ. Max. Unit 1 1.7 2.5 V VGS = 10V, ID = 20 A 0.028 0.033 Ω VGS = 5V, ID = 20 A 0.030 0.036 Ω Typ. Max. Unit VDS = VGS, ID = 250µA DYNAMIC Symbol gfs (1) 2/8 Parameter Forward Transconductance Test Conditions VDS = 15V, ID = 20 A VDS = 25V, f = 1 MHz, VGS = 0 Min. 25 S 2300 pF Ciss Input Capacitance Coss Output Capacitance 290 pF Crss Reverse Transfer Capacitance 125 pF STP40NF10L ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit 25 ns Rise Time VDD = 50 V, ID = 20 A RG = 4.7Ω VGS = 4.5V (see test circuit, Figure 3) 82 ns Qg Total Gate Charge VDD = 80V, ID =40A,VGS = 5V 46 Qgs Gate-Source Charge 12 nC Qgd Gate-Drain Charge 22 nC td(on) tr Turn-on Delay Time 64 nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off-Delay Time Fall Time VDD = 50 V, ID = 20 A, RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 64 24 ns ns td(off) tf tc Off-voltage Rise Time Fall Time Cross-over Time Vclamp =80V, ID = 40 A RG = 4.7Ω, VGS = 4.5V (see test circuit, Figure 3) 51 29 53 ns ns ns SOURCE DRAIN DIODE Symbol ISD Parameter Test Conditions Source-drain Current (pulsed) VSD (2) Forward On Voltage ISD = 40 A, VGS = 0 Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 40 A, di/dt = 100A/µs, VDD = 30V, Tj = 150°C (see test circuit, Figure 5) IRRM Typ. Source-drain Current ISDM (1) trr Qrr Min. 110 467 8 Max. Unit 40 A 160 A 1.3 V ns nC A Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. 2. Pulse width limited by safe operating area. Safe Operating Area Thermal Impedance 3/8 STP40NF10L Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STP40NF10L Normalized Gate Threshold Voltage vs Temperature Source-drain Diode Forward Characteristics Normalized On Resistance vs Temperature Normalized Drain-Source Breakdown vs Temperature 5/8 STP40NF10L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STP40NF10L TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 D1 0.107 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 L2 16.4 0.645 13.0 14.0 0.511 0.551 L5 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L4 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/8 STP40NF10L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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